MIPS: ralink: Add missing pinmux.

The mt7620 has a pin that can be used to generate an external reference
clock. The pinmux setup was missing the definition of said pin. This patch
adds it.

Signed-off-by: John Crispin <john@phrozen.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14898/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
index a73350b07fdf0bca66443d480ff2139def92c758..66af4ccb5c6c1e3cc3ec11cff3bc89e60e40842f 100644 (file)
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
@@ -115,9 +115,14 @@
 #define MT7620_GPIO_MODE_WDT_MASK      0x3
 #define MT7620_GPIO_MODE_WDT_SHIFT     21
 
+#define MT7620_GPIO_MODE_MDIO          0
+#define MT7620_GPIO_MODE_MDIO_REFCLK   1
+#define MT7620_GPIO_MODE_MDIO_GPIO     2
+#define MT7620_GPIO_MODE_MDIO_MASK     0x3
+#define MT7620_GPIO_MODE_MDIO_SHIFT    7
+
 #define MT7620_GPIO_MODE_I2C           0
 #define MT7620_GPIO_MODE_UART1         5
-#define MT7620_GPIO_MODE_MDIO          8
 #define MT7620_GPIO_MODE_RGMII1                9
 #define MT7620_GPIO_MODE_RGMII2                10
 #define MT7620_GPIO_MODE_SPI           11

diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index 6f0fdfd1e32a9f699d31225fab960a85a871e1c1..2503878824b882449f8082e85b52f51c3bb6619d 100644 (file)
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -55,7 +55,10 @@ static int dram_type;
 static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 1, 2) };
 static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
 static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
-static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
+static struct rt2880_pmx_func mdio_grp[] = {
+       FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2),
+       FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2),
+};
 static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
 static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
 static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
@@ -92,7 +95,8 @@ static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
        GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
        GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
                MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
-       GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
+       GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK,
+               MT7620_GPIO_MODE_MDIO_GPIO, MT7620_GPIO_MODE_MDIO_SHIFT),
        GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
        GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
        GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,