gpu: ipu-v3: prg: remove counter load enable

The counter load enable bit has no effect when the shadow register
set is activated. As we always operate the PRG with shadow enabled
it is safe to remove this.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>

diff --git a/drivers/gpu/ipu-v3/ipu-prg.c b/drivers/gpu/ipu-v3/ipu-prg.c
index caca57febbd6d5be91ffb0ea0cf4c1fe49f1a990..ecc9ea44dc50fc4f5b815564ae54f46884f93a2e 100644 (file)
--- a/drivers/gpu/ipu-v3/ipu-prg.c
+++ b/drivers/gpu/ipu-v3/ipu-prg.c
@@ -318,8 +318,6 @@ int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan,
        writel(val, prg->regs + IPU_PRG_BADDR(prg_chan));
 
        val = readl(prg->regs + IPU_PRG_CTL);
-       /* counter load enable */
-       val |= IPU_PRG_CTL_CNT_LOAD_EN(prg_chan);
        /* config AXI ID */
        val &= ~(IPU_PRG_CTL_SOFT_ARID_MASK <<
                 IPU_PRG_CTL_SOFT_ARID_SHIFT(prg_chan));