ath9k_hw: Enable hw PLL power save for AR9462
authorRajkumar Manoharan <rmanohar@qca.qualcomm.com>
Thu, 25 Oct 2012 11:41:31 +0000 (17:11 +0530)
committerJohn W. Linville <linville@tuxdriver.com>
Mon, 29 Oct 2012 19:30:29 +0000 (15:30 -0400)
This reduced the power consumption to half in full and network sleep.

Cc: stable@vger.kernel.org
Cc: Paul Stewart <pstew@chromium.org>
Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/ath/ath9k/ar9003_hw.c

index 1a36fa26263966e34bc6b952ffc64a0426387b11..0a6b7a3385df98d1219671748c62e6bcbfd7d780 100644 (file)
@@ -219,10 +219,10 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
 
                /* Awake -> Sleep Setting */
                INIT_INI_ARRAY(&ah->iniPcieSerdes,
-                              ar9462_pciephy_pll_on_clkreq_disable_L1_2p0);
+                              ar9462_pciephy_clkreq_disable_L1_2p0);
                /* Sleep -> Awake Setting */
                INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
-                              ar9462_pciephy_pll_on_clkreq_disable_L1_2p0);
+                              ar9462_pciephy_clkreq_disable_L1_2p0);
 
                /* Fast clock modal settings */
                INIT_INI_ARRAY(&ah->iniModesFastClock,