if (!IS_ERR(hws[n]))
continue;
- pr_err("%s: Unable to register leaf clock %d\n",
- np->full_name, n);
+ pr_err("%pOF: Unable to register leaf clock %d\n", np, n);
goto bg2_fail;
}
gbase = of_iomap(parent_np, 0);
if (!gbase) {
- pr_err("%s: Unable to map global base\n", np->full_name);
+ pr_err("%pOF: Unable to map global base\n", np);
return;
}
/* BG2Q CPU PLL is not part of global registers */
cpupll_base = of_iomap(parent_np, 1);
if (!cpupll_base) {
- pr_err("%s: Unable to map cpupll base\n", np->full_name);
+ pr_err("%pOF: Unable to map cpupll base\n", np);
iounmap(gbase);
return;
}
if (!IS_ERR(hws[n]))
continue;
- pr_err("%s: Unable to register leaf clock %d\n",
- np->full_name, n);
+ pr_err("%pOF: Unable to register leaf clock %d\n", np, n);
goto bg2q_fail;
}
if (!IS_ERR(hws[n]))
continue;
- pr_err("%s: Unable to register leaf clock %d\n",
- np->full_name, n);
+ pr_err("%pOF: Unable to register leaf clock %d\n",
+ np, n);
goto fail;
}
num_parents = of_count_phandle_with_args(node, "assigned-clock-parents",
"#clock-cells");
if (num_parents == -EINVAL)
- pr_err("clk: invalid value of clock-parents property at %s\n",
- node->full_name);
+ pr_err("clk: invalid value of clock-parents property at %pOF\n",
+ node);
for (index = 0; index < num_parents; index++) {
rc = of_parse_phandle_with_args(node, "assigned-clock-parents",
pclk = of_clk_get_from_provider(&clkspec);
if (IS_ERR(pclk)) {
if (PTR_ERR(pclk) != -EPROBE_DEFER)
- pr_warn("clk: couldn't get parent clock %d for %s\n",
- index, node->full_name);
+ pr_warn("clk: couldn't get parent clock %d for %pOF\n",
+ index, node);
return PTR_ERR(pclk);
}
clk = of_clk_get_from_provider(&clkspec);
if (IS_ERR(clk)) {
if (PTR_ERR(clk) != -EPROBE_DEFER)
- pr_warn("clk: couldn't get assigned clock %d for %s\n",
- index, node->full_name);
+ pr_warn("clk: couldn't get assigned clock %d for %pOF\n",
+ index, node);
rc = PTR_ERR(clk);
goto err;
}
clk = of_clk_get_from_provider(&clkspec);
if (IS_ERR(clk)) {
if (PTR_ERR(clk) != -EPROBE_DEFER)
- pr_warn("clk: couldn't get clock %d for %s\n",
- index, node->full_name);
+ pr_warn("clk: couldn't get clock %d for %pOF\n",
+ index, node);
return PTR_ERR(clk);
}
base = of_iomap(node, 0);
if (!base) {
- pr_err("%s: of_iomap failed\n", node->full_name);
+ pr_err("%pOF: of_iomap failed\n", node);
return;
}
ref_clk = of_clk_get(node, 0);
if (IS_ERR(ref_clk)) {
- pr_err("%s: of_clk_get failed\n", node->full_name);
+ pr_err("%pOF: of_clk_get failed\n", node);
return;
}
hw = clk_hw_register_fixed_factor(NULL, name, parent_name, 0, mul, 1);
if (IS_ERR(hw)) {
- pr_err("%s: failed to register clock\n", node->full_name);
+ pr_err("%pOF: failed to register clock\n", node);
return;
}
base = of_iomap(node, 0);
if (!base) {
- pr_err("%s: of_iomap failed\n", node->full_name);
+ pr_err("%pOF: of_iomap failed\n", node);
return;
}
pll_clk = of_clk_get(node, 0);
if (IS_ERR(pll_clk)) {
- pr_err("%s: of_clk_get failed\n", node->full_name);
+ pr_err("%pOF: of_clk_get failed\n", node);
return;
}
hw = clk_hw_register_fixed_factor(NULL, name, parent_name, 0, 1, div);
if (IS_ERR(hw)) {
- pr_err("%s: failed to register clock\n", node->full_name);
+ pr_err("%pOF: failed to register clock\n", node);
return;
}
}
if (i == ARRAY_SIZE(chipinfo)) {
- pr_err("%s: unknown clockgen node %s\n", __func__,
- np->full_name);
+ pr_err("%s: unknown clockgen node %pOF\n", __func__, np);
goto err;
}
clockgen.info = chipinfo[i];
if (guts) {
clockgen.guts = of_iomap(guts, 0);
if (!clockgen.guts) {
- pr_err("%s: Couldn't map %s regs\n", __func__,
- guts->full_name);
+ pr_err("%s: Couldn't map %pOF regs\n", __func__,
+ guts);
}
}
base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock);
if (IS_ERR(clks[idx])) {
- pr_err("%s: Unable to register leaf clock %s\n",
- np->full_name, gd->name);
+ pr_err("%pOF: Unable to register leaf clock %s\n",
+ np, gd->name);
goto fail;
}
}
reg = of_iomap(np, 0);
if (reg == NULL) {
- pr_err("Unable to map CSR register for %s\n", np->full_name);
+ pr_err("Unable to map CSR register for %pOF\n", np);
return;
}
of_property_read_string(np, "clock-output-names", &clk_name);
/* Parse the DTS register for resource */
rc = of_address_to_resource(np, 0, &res);
if (rc != 0) {
- pr_err("no DTS register for %s\n", np->full_name);
+ pr_err("no DTS register for %pOF\n", np);
return;
}
csr_reg = of_iomap(np, 0);
if (!csr_reg) {
- pr_err("Unable to map resource for %s\n", np->full_name);
+ pr_err("Unable to map resource for %pOF\n", np);
return;
}
of_property_read_string(np, "clock-output-names", &clk_name);
rc = of_address_to_resource(np, i, &res);
if (rc != 0) {
if (i == 0) {
- pr_err("no DTS register for %s\n",
- np->full_name);
+ pr_err("no DTS register for %pOF\n", np);
return;
}
break;
}
map_res = of_iomap(np, i);
if (map_res == NULL) {
- pr_err("Unable to map resource %d for %s\n",
- i, np->full_name);
+ pr_err("Unable to map resource %d for %pOF\n", i, np);
goto err;
}
if (strcmp(res.name, "div-reg") == 0)
pr_debug("Add %s clock\n", clk_name);
rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
if (rc != 0)
- pr_err("%s: could register provider clk %s\n", __func__,
- np->full_name);
+ pr_err("%s: could register provider clk %pOF\n", __func__, np);
return;
mutex_lock(&of_clk_mutex);
list_add(&cp->link, &of_clk_providers);
mutex_unlock(&of_clk_mutex);
- pr_debug("Added clock from %s\n", np->full_name);
+ pr_debug("Added clock from %pOF\n", np);
ret = of_clk_set_defaults(np, true);
if (ret < 0)
mutex_lock(&of_clk_mutex);
list_add(&cp->link, &of_clk_providers);
mutex_unlock(&of_clk_mutex);
- pr_debug("Added clk_hw provider from %s\n", np->full_name);
+ pr_debug("Added clk_hw provider from %pOF\n", np);
ret = of_clk_set_defaults(np, true);
if (ret < 0)
break;
} else if (name && index >= 0) {
if (PTR_ERR(clk) != -EPROBE_DEFER)
- pr_err("ERROR: could not get clock %s:%s(%i)\n",
- np->full_name, name ? name : "", index);
+ pr_err("ERROR: could not get clock %pOF:%s(%i)\n",
+ np, name ? name : "", index);
return clk;
}
regmap = syscon_node_to_regmap(node);
if (IS_ERR(regmap)) {
- pr_err("Cannot find regmap for %s: %ld\n", node->full_name,
+ pr_err("Cannot find regmap for %pOF: %ld\n", node,
PTR_ERR(regmap));
return PTR_ERR(regmap);
}
regmap = syscon_node_to_regmap(node);
if (IS_ERR(regmap)) {
- pr_err("Cannot find regmap for %s: %ld\n", node->full_name,
+ pr_err("Cannot find regmap for %pOF: %ld\n", node,
PTR_ERR(regmap));
return PTR_ERR(regmap);
}
regmap = syscon_node_to_regmap(np);
if (IS_ERR(regmap)) {
- pr_err("Cannot find regmap for %s: %ld\n", np->full_name,
+ pr_err("Cannot find regmap for %pOF: %ld\n", np,
PTR_ERR(regmap));
return;
}
u32 ncells;
if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
- pr_warn("%s lacks #power-domain-cells\n", np->full_name);
+ pr_warn("%pOF lacks #power-domain-cells\n", np);
return;
}
if (rcar_rst_read_mode_pins(&cpg_mode)) {
/* Backward-compatibility with old DT */
- pr_warn("%s: failed to obtain mode pins from RST\n",
- np->full_name);
+ pr_warn("%pOF: failed to obtain mode pins from RST\n", np);
cpg_mode = rcar_gen2_read_mode_pins();
}
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
if (IS_ERR(reg)) {
- pr_err("%s: Could not map the clock registers\n",
- of_node_full_name(node));
+ pr_err("%pOF: Could not map the clock registers\n", node);
return;
}
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
if (IS_ERR(reg)) {
- pr_err("%s: Could not map the clock registers\n",
- of_node_full_name(node));
+ pr_err("%pOF: Could not map the clock registers\n", node);
return;
}
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
if (IS_ERR(reg)) {
- pr_err("%s: Could not map the clock registers\n",
- of_node_full_name(node));
+ pr_err("%pOF: Could not map the clock registers\n", node);
return;
}
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
if (IS_ERR(reg)) {
- pr_err("%s: Could not map the clock registers\n",
- of_node_full_name(node));
+ pr_err("%pOF: Could not map the clock registers\n", node);
return;
}
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
if (IS_ERR(reg)) {
- pr_err("%s: Could not map the clock registers\n",
- of_node_full_name(node));
+ pr_err("%pOF: Could not map the clock registers\n", node);
return;
}
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
if (IS_ERR(reg)) {
- pr_err("%s: Could not map the clock registers\n",
- of_node_full_name(node));
+ pr_err("%pOF: Could not map the clock registers\n", node);
return;
}
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
if (IS_ERR(reg)) {
- pr_err("%s: Could not map the clock registers\n",
- of_node_full_name(node));
+ pr_err("%pOF: Could not map the clock registers\n", node);
return;
}
reg = of_iomap(node, 0);
if (!reg) {
- pr_err("Could not map registers for mux-clk: %s\n",
- of_node_full_name(node));
+ pr_err("Could not map registers for mux-clk: %pOF\n", node);
return NULL;
}
i = of_clk_parent_fill(node, parents, SUNXI_MAX_PARENTS);
if (of_property_read_string(node, "clock-output-names", &clk_name)) {
- pr_err("%s: could not read clock-output-names from \"%s\"\n",
- __func__, of_node_full_name(node));
+ pr_err("%s: could not read clock-output-names from \"%pOF\"\n",
+ __func__, node);
goto out_unmap;
}
reg = of_iomap(node, 0);
if (!reg) {
- pr_err("Could not map registers for mux-clk: %s\n",
- of_node_full_name(node));
+ pr_err("Could not map registers for mux-clk: %pOF\n", node);
return;
}
clk_parent = of_clk_get_parent_name(node, 0);
if (of_property_read_string(node, "clock-output-names", &clk_name)) {
- pr_err("%s: could not read clock-output-names from \"%s\"\n",
- __func__, of_node_full_name(node));
+ pr_err("%s: could not read clock-output-names from \"%pOF\"\n",
+ __func__, node);
goto out_unmap;
}
reg = of_iomap(node, 0);
if (!reg) {
- pr_err("Could not map registers for divs-clk: %s\n",
- of_node_full_name(node));
+ pr_err("Could not map registers for divs-clk: %pOF\n", node);
return NULL;
}
err = of_property_read_u32(node, "clock-frequency", &tmp);
if (err) {
- pr_err("timing %s: failed to read rate\n", node->full_name);
+ pr_err("timing %pOF: failed to read rate\n", node);
return err;
}
err = of_property_read_u32(node, "nvidia,parent-clock-frequency", &tmp);
if (err) {
- pr_err("timing %s: failed to read parent rate\n",
- node->full_name);
+ pr_err("timing %pOF: failed to read parent rate\n", node);
return err;
}
timing->parent = of_clk_get_by_name(node, "emc-parent");
if (IS_ERR(timing->parent)) {
- pr_err("timing %s: failed to get parent clock\n",
- node->full_name);
+ pr_err("timing %pOF: failed to get parent clock\n", node);
return PTR_ERR(timing->parent);
}
}
}
if (timing->parent_index == 0xff) {
- pr_err("timing %s: %s is not a valid parent\n",
- node->full_name, __clk_get_name(timing->parent));
+ pr_err("timing %pOF: %s is not a valid parent\n",
+ node, __clk_get_name(timing->parent));
clk_put(timing->parent);
return -EINVAL;
}
for (i = 0; i < num_clks; i++) {
clk = of_clk_get(node, i);
if (IS_ERR(clk)) {
- pr_err("%s: Failed get %s' clock nr %d (%ld)\n",
- __func__, node->full_name, i, PTR_ERR(clk));
+ pr_err("%s: Failed get %pOF' clock nr %d (%ld)\n",
+ __func__, node, i, PTR_ERR(clk));
continue;
}
clk_hw = __clk_get_hw(clk);