clk: spear3xx: Use proper control register offset
authorThomas Gleixner <tglx@linutronix.de>
Thu, 19 Jun 2014 21:52:23 +0000 (21:52 +0000)
committerMike Turquette <mturquette@linaro.org>
Sun, 13 Jul 2014 14:11:40 +0000 (07:11 -0700)
The control register is at offset 0x10, not 0x0. This is wreckaged
since commit 5df33a62c (SPEAr: Switch to common clock framework).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: stable@vger.kernel.org
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
drivers/clk/spear/spear3xx_clock.c

index c2d204315546b5398e79b698615645c9568e445e..125eba86c84486ffcf08abebe72c7d4b85a850a1 100644 (file)
@@ -211,7 +211,7 @@ static inline void spear310_clk_init(void) { }
 /* array of all spear 320 clock lookups */
 #ifdef CONFIG_MACH_SPEAR320
 
-#define SPEAR320_CONTROL_REG           (soc_config_base + 0x0000)
+#define SPEAR320_CONTROL_REG           (soc_config_base + 0x0010)
 #define SPEAR320_EXT_CTRL_REG          (soc_config_base + 0x0018)
 
        #define SPEAR320_UARTX_PCLK_MASK                0x1