drm/i915: Move pll power state to crtc power domains.
authorMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Mon, 14 Mar 2016 08:27:54 +0000 (09:27 +0100)
committerMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Thu, 17 Mar 2016 08:27:55 +0000 (09:27 +0100)
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1457944075-14123-4-git-send-email-maarten.lankhorst@linux.intel.com
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_dpll_mgr.c

index 80aa51c98a2d4c2d19d52cc2a20b67f9d9174c60..e3e158175256b8f39761553e80c1a03f352f6d8f 100644 (file)
@@ -5273,6 +5273,9 @@ static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
                mask |= BIT(intel_display_port_power_domain(intel_encoder));
        }
 
+       if (crtc_state->shared_dpll)
+               mask |= BIT(POWER_DOMAIN_PLLS);
+
        return mask;
 }
 
@@ -15703,9 +15706,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 
                DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
                              pll->name, pll->config.crtc_mask, pll->on);
-
-               if (pll->config.crtc_mask)
-                       intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
        }
 
        for_each_intel_encoder(dev, encoder) {
index 2c98610213f493687e6b1b785e84f4344a348224..fc5cfc89a026648dc7a1b770d1bad38453972469 100644 (file)
@@ -135,8 +135,6 @@ void intel_enable_shared_dpll(struct intel_crtc *crtc)
        }
        WARN_ON(pll->on);
 
-       intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
-
        DRM_DEBUG_KMS("enabling %s\n", pll->name);
        pll->funcs.enable(dev_priv, pll);
        pll->on = true;
@@ -173,8 +171,6 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc)
        DRM_DEBUG_KMS("disabling %s\n", pll->name);
        pll->funcs.disable(dev_priv, pll);
        pll->on = false;
-
-       intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
 }
 
 static struct intel_shared_dpll *