Author: Ralf Baechle <ralf@linux-mips.org>
authorRalf Baechle <ralf@linux-mips.org>
Tue, 9 Oct 2007 14:15:21 +0000 (15:15 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Mon, 29 Oct 2007 19:35:37 +0000 (19:35 +0000)
[MIPS] MSP71xx: Fix bitrot.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/pci/fixup-pmcmsp.c
arch/mips/pci/ops-pmcmsp.c
arch/mips/pmc-sierra/msp71xx/msp_serial.c

index 00261211dbfae199b8f9ce98a826b411ad915254..65735b1b7665b08291fc11f30f0fcac66e5ef522 100644 (file)
@@ -202,7 +202,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
  *  RETURNS:     IRQ number
  *
  ****************************************************************************/
-int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
 #if !defined(CONFIG_PMC_MSP7120_GW) && !defined(CONFIG_PMC_MSP7120_EVAL)
        printk(KERN_WARNING "PCI: unknown board, no PCI IRQs assigned.\n");
index 059eade96f2e74fdd3aa29da8fe30919f5a84379..109c95ca698bb9cb3aefde8b584d4f1bfa7d834d 100644 (file)
@@ -404,7 +404,7 @@ int msp_pcibios_config_access(unsigned char access_type,
        if (pciirqflag == 0) {
                request_irq(MSP_INT_PCI,/* Hardcoded internal MSP7120 wiring */
                                bpci_interrupt,
-                               SA_SHIRQ | SA_INTERRUPT,
+                               IRQF_SHARED | IRQF_DISABLED,
                                "PMC MSP PCI Host",
                                preg);
                pciirqflag = ~0;
index 15e7b8000b4c34413b5a9a8a121dc270aac06101..9de34302e5f4004ef21ba4b8de6c4f1771fb47f3 100644 (file)
@@ -122,7 +122,7 @@ void __init msp_serial_setup(void)
        up.uartclk      = uartclk;
        up.regshift     = 2;
        up.iotype       = UPIO_DWAPB; /* UPIO_MEM like */
-       up.flags        = STD_COM_FLAGS;
+       up.flags        = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
        up.type         = PORT_16550A;
        up.line         = 0;
        up.private_data         = (void*)UART0_STATUS_REG;