drm/i915: enable RC6 workaround on Haswell
authorEugeni Dodonov <eugeni.dodonov@intel.com>
Mon, 2 Jul 2012 14:51:10 +0000 (11:51 -0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 5 Jul 2012 07:56:03 +0000 (09:56 +0200)
For Haswell, on some of the early hardware revisions, it is possible to
run into issues when RC6 state is enabled and when pipes change state.

v2: add comment saying that this is for early revisions only.

v3: beautify as suggested by Daniel Vetter.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_pm.c

index 3be31a4cb8fb5c6b543f9bffaa32acb0f4cfb627..4ddc62ecf839d01d3392da70c5f878c541b67762 100644 (file)
 #define  SFUSE_STRAP_DDIC_DETECTED     (1<<1)
 #define  SFUSE_STRAP_DDID_DETECTED     (1<<0)
 
+#define WM_DBG                         0x45280
+#define  WM_DBG_DISALLOW_MULTIPLE_LP   (1<<0)
+#define  WM_DBG_DISALLOW_MAXFIFO       (1<<1)
+#define  WM_DBG_DISALLOW_SPRITE                (1<<2)
+
 #endif /* _I915_REG_H_ */
index 3c2724e4297523421419877cb735dda0e034155f..6e02698e9a3d806effae1a736cb61959f7e977d6 100644 (file)
@@ -3467,6 +3467,16 @@ static void haswell_init_clock_gating(struct drm_device *dev)
        /* WaDisable4x2SubspanOptimization */
        I915_WRITE(CACHE_MODE_1,
                   _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
+
+       /* XXX: This is a workaround for early silicon revisions and should be
+        * removed later.
+        */
+       I915_WRITE(WM_DBG,
+                       I915_READ(WM_DBG) |
+                       WM_DBG_DISALLOW_MULTIPLE_LP |
+                       WM_DBG_DISALLOW_SPRITE |
+                       WM_DBG_DISALLOW_MAXFIFO);
+
 }
 
 static void ivybridge_init_clock_gating(struct drm_device *dev)