MIPS: SEAD3: Disable L2 cache on SEAD-3.

The cores used on the SEAD-3 platform do not have L2 caches, so
this option should not be turned on. Originally fixed on public
'linux-mti-3.8' release branch.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5559/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 3a3e54cc7703db5f471d72e9847f50d211eb9ba7..567c45b336519772d58dc8107e60b9fc1b82a637 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -342,7 +342,6 @@ config MIPS_SEAD3
        select DMA_NONCOHERENT
        select IRQ_CPU
        select IRQ_GIC
-       select MIPS_CPU_SCACHE
        select MIPS_MSC
        select SYS_HAS_CPU_MIPS32_R1
        select SYS_HAS_CPU_MIPS32_R2