clk/exynos5420: fix the order of parents of hdmi mux

Listing sclk_hdmiphy at 0th position in the list of parents is
causing wrong configuration in reg SRC_DISP10.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 4e0c13e8856975b9f8c66a53d68e7e0a7c255610..522c033f52574019999506378d10ea4539b25add 100644 (file)
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -286,7 +286,7 @@ PNAME(audio2_p)     = { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll",
                  "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
 PNAME(spdif_p) = { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2",
                  "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" };
-PNAME(hdmi_p)  = { "sclk_hdmiphy", "dout_hdmi_pixel" };
+PNAME(hdmi_p)  = { "dout_hdmi_pixel", "sclk_hdmiphy" };
 PNAME(maudio0_p)       = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll",
                          "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };