tegra_host->ddr_signaling = false;
}
-static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width)
-{
- u32 ctrl;
-
- ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
- if ((host->mmc->caps & MMC_CAP_8_BIT_DATA) &&
- (bus_width == MMC_BUS_WIDTH_8)) {
- ctrl &= ~SDHCI_CTRL_4BITBUS;
- ctrl |= SDHCI_CTRL_8BITBUS;
- } else {
- ctrl &= ~SDHCI_CTRL_8BITBUS;
- if (bus_width == MMC_BUS_WIDTH_4)
- ctrl |= SDHCI_CTRL_4BITBUS;
- else
- ctrl &= ~SDHCI_CTRL_4BITBUS;
- }
- sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
-}
-
static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
{
u32 val;
.read_w = tegra_sdhci_readw,
.write_l = tegra_sdhci_writel,
.set_clock = tegra_sdhci_set_clock,
- .set_bus_width = tegra_sdhci_set_bus_width,
+ .set_bus_width = sdhci_set_bus_width,
.reset = tegra_sdhci_reset,
.platform_execute_tuning = tegra_sdhci_execute_tuning,
.set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
.write_w = tegra_sdhci_writew,
.write_l = tegra_sdhci_writel,
.set_clock = tegra_sdhci_set_clock,
- .set_bus_width = tegra_sdhci_set_bus_width,
+ .set_bus_width = sdhci_set_bus_width,
.reset = tegra_sdhci_reset,
.platform_execute_tuning = tegra_sdhci_execute_tuning,
.set_uhs_signaling = tegra_sdhci_set_uhs_signaling,