iwlwifi: move uCode API definitions to iwl-4965-commands.h
authorBen Cahill <ben.m.cahill@intel.com>
Thu, 29 Nov 2007 03:09:59 +0000 (11:09 +0800)
committerDavid S. Miller <davem@davemloft.net>
Mon, 28 Jan 2008 23:05:26 +0000 (15:05 -0800)
Move uCode API definitions to iwl-4965-commands.h

Signed-off-by: Ben Cahill <ben.m.cahill@intel.com>
Signed-off-by: Zhu Yi <yi.zhu@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
drivers/net/wireless/iwlwifi/iwl-4965-commands.h
drivers/net/wireless/iwlwifi/iwl-4965-hw.h

index bd55709e48f26f577004df1880eac46eec8d738e..49582b90f8cfdb438ceb759225a3b2dc6c962f2d 100644 (file)
@@ -335,6 +335,21 @@ enum {
        RXON_DEV_TYPE_SNIFFER = 6,
 };
 
+
+#define RXON_RX_CHAIN_DRIVER_FORCE_MSK         __constant_cpu_to_le16(0x1<<0)
+#define RXON_RX_CHAIN_VALID_MSK                        __constant_cpu_to_le16(0x7<<1)
+#define RXON_RX_CHAIN_VALID_POS                        (1)
+#define RXON_RX_CHAIN_FORCE_SEL_MSK            __constant_cpu_to_le16(0x7<<4)
+#define RXON_RX_CHAIN_FORCE_SEL_POS            (4)
+#define RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK       __constant_cpu_to_le16(0x7<<7)
+#define RXON_RX_CHAIN_FORCE_MIMO_SEL_POS       (7)
+#define RXON_RX_CHAIN_CNT_MSK                  __constant_cpu_to_le16(0x3<<10)
+#define RXON_RX_CHAIN_CNT_POS                  (10)
+#define RXON_RX_CHAIN_MIMO_CNT_MSK             __constant_cpu_to_le16(0x3<<12)
+#define RXON_RX_CHAIN_MIMO_CNT_POS             (12)
+#define RXON_RX_CHAIN_MIMO_FORCE_MSK           __constant_cpu_to_le16(0x1<<14)
+#define RXON_RX_CHAIN_MIMO_FORCE_POS           (14)
+
 /* rx_config flags */
 /* band & modulation selection */
 #define RXON_FLG_BAND_24G_MSK           __constant_cpu_to_le32(1 << 0)
@@ -358,6 +373,21 @@ enum {
 * (according to ON_AIR deassertion) */
 #define RXON_FLG_TSF2HOST_MSK           __constant_cpu_to_le32(1 << 15)
 
+
+/* HT flags */
+#define RXON_FLG_CTRL_CHANNEL_LOC_POS          (22)
+#define RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK       __constant_cpu_to_le32(0x1<<22)
+
+#define RXON_FLG_HT_OPERATING_MODE_POS         (23)
+
+#define RXON_FLG_HT_PROT_MSK                   __constant_cpu_to_le32(0x1<<23)
+#define RXON_FLG_FAT_PROT_MSK                  __constant_cpu_to_le32(0x2<<23)
+
+#define RXON_FLG_CHANNEL_MODE_POS              (25)
+#define RXON_FLG_CHANNEL_MODE_MSK              __constant_cpu_to_le32(0x3<<25)
+#define RXON_FLG_CHANNEL_MODE_PURE_40_MSK      __constant_cpu_to_le32(0x1<<25)
+#define RXON_FLG_CHANNEL_MODE_MIXED_MSK                __constant_cpu_to_le32(0x2<<25)
+
 /* rx_config filter flags */
 /* accept all data frames */
 #define RXON_FILTER_PROMISC_MSK         __constant_cpu_to_le32(1 << 0)
@@ -431,6 +461,15 @@ struct iwl4965_tx_power {
 #define POWER_TABLE_NUM_ENTRIES                        33
 #define POWER_TABLE_NUM_HT_OFDM_ENTRIES                32
 #define POWER_TABLE_CCK_ENTRY                  32
+
+union iwl4965_tx_power_dual_stream {
+       struct {
+               u8 radio_tx_gain[2];
+               u8 dsp_predis_atten[2];
+       } s;
+       u32 dw;
+};
+
 struct tx_power_dual_stream {
        __le32 dw;
 } __attribute__ ((packed));
index 02ea71ec1d3e11c51214502833b28bf93863b5d9..962aef2f1ef2491c73eddba7691d9415035ad7a0 100644 (file)
@@ -698,45 +698,8 @@ enum {
 #define CALIB_IWL_TX_ATTEN_GR5_FCH 1
 #define CALIB_IWL_TX_ATTEN_GR5_LCH 20
 
-union iwl4965_tx_power_dual_stream {
-       struct {
-               u8 radio_tx_gain[2];
-               u8 dsp_predis_atten[2];
-       } s;
-       u32 dw;
-};
-
 /********************* END TXPOWER *****************************************/
 
-/* HT flags */
-#define RXON_FLG_CTRL_CHANNEL_LOC_POS          (22)
-#define RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK       __constant_cpu_to_le32(0x1<<22)
-
-#define RXON_FLG_HT_OPERATING_MODE_POS         (23)
-
-#define RXON_FLG_HT_PROT_MSK                   __constant_cpu_to_le32(0x1<<23)
-#define RXON_FLG_FAT_PROT_MSK                  __constant_cpu_to_le32(0x2<<23)
-
-#define RXON_FLG_CHANNEL_MODE_POS              (25)
-#define RXON_FLG_CHANNEL_MODE_MSK              __constant_cpu_to_le32(0x3<<25)
-#define RXON_FLG_CHANNEL_MODE_PURE_40_MSK      __constant_cpu_to_le32(0x1<<25)
-#define RXON_FLG_CHANNEL_MODE_MIXED_MSK                __constant_cpu_to_le32(0x2<<25)
-
-#define RXON_RX_CHAIN_DRIVER_FORCE_MSK         __constant_cpu_to_le16(0x1<<0)
-#define RXON_RX_CHAIN_VALID_MSK                        __constant_cpu_to_le16(0x7<<1)
-#define RXON_RX_CHAIN_VALID_POS                        (1)
-#define RXON_RX_CHAIN_FORCE_SEL_MSK            __constant_cpu_to_le16(0x7<<4)
-#define RXON_RX_CHAIN_FORCE_SEL_POS            (4)
-#define RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK       __constant_cpu_to_le16(0x7<<7)
-#define RXON_RX_CHAIN_FORCE_MIMO_SEL_POS       (7)
-#define RXON_RX_CHAIN_CNT_MSK                  __constant_cpu_to_le16(0x3<<10)
-#define RXON_RX_CHAIN_CNT_POS                  (10)
-#define RXON_RX_CHAIN_MIMO_CNT_MSK             __constant_cpu_to_le16(0x3<<12)
-#define RXON_RX_CHAIN_MIMO_CNT_POS             (12)
-#define RXON_RX_CHAIN_MIMO_FORCE_MSK           __constant_cpu_to_le16(0x1<<14)
-#define RXON_RX_CHAIN_MIMO_FORCE_POS           (14)
-
-
 /* Flow Handler Definitions */
 
 /**********************/