{AM_MESON_CPU_MAJOR_ID_SM1, "sm1"},
{AM_MESON_CPU_MAJOR_ID_TL1, "tl1"},
{AM_MESON_CPU_MAJOR_ID_TM2, "tm2"},
+ {AM_MESON_CPU_MAJOR_ID_SC2, "sc2"},
{0, NULL},
};
AM_MESON_CPU_MAJOR_ID_RES_0x2d,
AM_MESON_CPU_MAJOR_ID_TL1,
AM_MESON_CPU_MAJOR_ID_TM2,
+ AM_MESON_CPU_MAJOR_ID_RES_0x30,
+ AM_MESON_CPU_MAJOR_ID_RES_0x31,
+ AM_MESON_CPU_MAJOR_ID_SC2,
};
static const struct of_device_id cpu_ver_of_match[] = {
.compatible = "amlogic, cpu-major-id-tm2",
.data = &cpu_ver_info[AM_MESON_CPU_MAJOR_ID_TM2 - MAJOR_ID_START],
},
+ {
+ .compatible = "amlogic, cpu-major-id-sc2",
+ .data = &cpu_ver_info[AM_MESON_CPU_MAJOR_ID_SC2 - MAJOR_ID_START],
+ },
{},
};
AM_MESON_CPU_MAJOR_ID_RES_0x2d,
AM_MESON_CPU_MAJOR_ID_TL1 = 0x2e,
AM_MESON_CPU_MAJOR_ID_TM2 = 0x2f,
+ AM_MESON_CPU_MAJOR_ID_RES_0x30,
+ AM_MESON_CPU_MAJOR_ID_RES_0x31,
+ AM_MESON_CPU_MAJOR_ID_SC2 = 0x32,
AM_MESON_CPU_MAJOR_ID_MAX,
};
{AM_MESON_CPU_MAJOR_ID_SM1, "sm1"},
{AM_MESON_CPU_MAJOR_ID_TL1, "tl1"},
{AM_MESON_CPU_MAJOR_ID_TM2, "tm2"},
+ {AM_MESON_CPU_MAJOR_ID_SC2, "sc2"},
};
const char *get_fw_format_name(unsigned int format)
void set_clock_gate(struct gate_switch_node *nodes, int num)
{
struct gate_switch_node *node = NULL;
+ char *hevc_mux_str = NULL;
+
+ if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SC2)
+ hevc_mux_str = "clk_hevc_mux";
+ else
+ hevc_mux_str = "clk_hevcf_mux";
do {
node = &nodes[num - 1];
- if (IS_ERR_OR_NULL(node))
+ if (IS_ERR_OR_NULL(node) || (IS_ERR_OR_NULL(node->clk)))
pr_info("get mux clk err.\n");
if (!strcmp(node->name, "clk_vdec_mux"))
gclk.vdec_mux_node = node;
else if (!strcmp(node->name, "clk_hcodec_mux"))
gclk.hcodec_mux_node = node;
- else if (!strcmp(node->name, "clk_hevc_mux"))
- gclk.hevc_mux_node = node;
+ else if (!strcmp(node->name, hevc_mux_str))
+ gclk.hevc_mux_node = node;
else if (!strcmp(node->name, "clk_hevcb_mux"))
gclk.hevc_back_mux_node = node;
} while(--num);
clk = hevcb_frq;
}
- if (get_cpu_major_id() >= MESON_CPU_MAJOR_ID_TXLX) {
+ if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_TXLX) &&
+ (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SC2)) {
if ((READ_EFUSE_REG(EFUSE_LIC1) >> 28 & 0x1) && clk > 333) {
pr_info("The hevcb clock limit to 333MHz.\n");
clk = 333;
AM_MESON_CPU_MAJOR_ID_SM1,\
AM_MESON_CPU_MAJOR_ID_TL1,\
AM_MESON_CPU_MAJOR_ID_TM2,\
+ AM_MESON_CPU_MAJOR_ID_SC2,\
0}
#include "clk.h"
{
.name = "asyncfifo",
},
+ {
+ .name = "clk_hevcf_mux",
+ },
};
/*
#include "../utils/firmware.h"
#include "../utils/vdec_v4l2_buffer_ops.h"
#include "../utils/config_parser.h"
+#include "../../../common/chips/decoder_cpu_ver_info.h"
#include <media/v4l2-mem2mem.h>
#define DRIVER_NAME "ammvdec_mpeg4"
/* reset VLD fifo for all vdec */
WRITE_VREG(DOS_SW_RESET0, (1<<5) | (1<<4) | (1<<3));
WRITE_VREG(DOS_SW_RESET0, 0);
-
- dummy = READ_RESET_REG(RESET0_REGISTER);
+ if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SC2)
+ dummy = READ_RESET_REG(RESET0_REGISTER);
WRITE_VREG(POWER_CTL_VLD, 1 << 4);
/*
#include <linux/amlogic/power_ctrl.h>
#endif
+#include <dt-bindings/power/sc2-pd.h>
+#include <linux/amlogic/pwr_ctrl.h>
+
static DEFINE_MUTEX(vdec_mutex);
#define MC_SIZE (4096 * 4)
int decode_underflow = 0;
-int enable_stream_mode_multi_dec;
+static int enable_stream_mode_multi_dec;
#define CANVAS_MAX_SIZE (AMVDEC_CANVAS_MAX1 - AMVDEC_CANVAS_START_INDEX + 1 + AMVDEC_CANVAS_MAX2 + 1)
}
EXPORT_SYMBOL(VDEC_PRINT_FUN_LINENO);
+bool is_support_no_parser(void)
+{
+ if ((enable_stream_mode_multi_dec) ||
+ (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SC2))
+ return true;
+ return false;
+}
+EXPORT_SYMBOL(is_support_no_parser);
+
unsigned char is_mult_inc(unsigned int type)
{
unsigned char ret = 0;
codec_dmcbus_read(DMC_REQ_CTRL) & ~mask);
spin_unlock_irqrestore(&vdec_spin_lock, flags);
- if (is_cpu_tm2_revb()) {
+ if (is_cpu_tm2_revb() ||
+ (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SC2)) {
while (!(codec_dmcbus_read(TM2_REVB_DMC_CHAN_STS)
& mask))
;
return;
if (vdec->input.target == VDEC_INPUT_TARGET_VLD) {
- if (enable_stream_mode_multi_dec) {
+ if (is_support_no_parser()) {
if (!vdec->master) {
WRITE_VREG(VLD_MEM_VIFIFO_WP,
STBUF_READ(&vdec->vbuf, get_wp));
STBUF_READ(&vdec->vbuf, get_wp));
}
} else if (vdec->input.target == VDEC_INPUT_TARGET_HEVC) {
- if (enable_stream_mode_multi_dec) {
+ if (is_support_no_parser()) {
if (!vdec->master) {
WRITE_VREG(HEVC_STREAM_WR_PTR,
STBUF_READ(&vdec->vbuf, get_wp));
/* reset VLD fifo for all vdec */
WRITE_VREG(DOS_SW_RESET0, (1<<5) | (1<<4) | (1<<3));
WRITE_VREG(DOS_SW_RESET0, 0);
-
- dummy = READ_RESET_REG(RESET0_REGISTER);
+ if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SC2)
+ dummy = READ_RESET_REG(RESET0_REGISTER);
WRITE_VREG(POWER_CTL_VLD, 1 << 4);
} else if (input->target == VDEC_INPUT_TARGET_HEVC) {
#if 0
codec_dmcbus_read(DMC_REQ_CTRL) & ~mask);
spin_unlock_irqrestore(&vdec_spin_lock, flags);
- if (is_cpu_tm2_revb()) {
+ if (is_cpu_tm2_revb() ||
+ (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SC2)) {
while (!(codec_dmcbus_read(TM2_REVB_DMC_CHAN_STS)
& mask))
;
*todo: VFM patch control should be configurable,
* for now all stream based input uses default VFM path.
*/
- if (!enable_stream_mode_multi_dec) {
+ if (!is_support_no_parser()) {
if (vdec_stream_based(vdec) && !vdec_dual(vdec)) {
if (vdec_core->vfm_vdec == NULL) {
pr_debug("vdec_init set vfm decoder %p\n", vdec);
/* todo */
if (!vdec_dual(vdec)) {
p->use_vfm_path =
- enable_stream_mode_multi_dec ?
+ (is_support_no_parser()) ?
vdec_single(vdec) :
vdec_stream_based(vdec);
}
/* create IONVIDEO instance and connect decoder's
* vf_provider interface to it
*/
- if (!enable_stream_mode_multi_dec) {
+ if (!is_support_no_parser()) {
if (p->type != VDEC_TYPE_FRAME_BLOCK) {
r = -ENODEV;
pr_err("vdec: Incorrect decoder type\n");
}
EXPORT_SYMBOL(vdec_power_reset);
+
void vdec_poweron(enum vdec_type_e core)
{
void *decomp_addr = NULL;
return;
}
+ if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SC2) {
+ if (core == VDEC_1)
+ pwr_ctrl_psci_smc(PDID_DOS_VDEC, PWR_ON);
+ else if (core == VDEC_HEVC) {
+ pwr_ctrl_psci_smc(PDID_DOS_HEVC, PWR_ON);
+
+ /* wait 10uS */
+ udelay(10);
+ /* hevc soft reset */
+ WRITE_VREG(DOS_SW_RESET3, 0xffffffff);
+ WRITE_VREG(DOS_SW_RESET3, 0);
+ /* enable hevc clock */
+ amports_switch_gate("clk_hevcf_mux", 1);
+ if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
+ amports_switch_gate("clk_hevcb_mux", 1);
+ hevc_clock_hi_enable();
+ hevc_back_clock_hi_enable();
+ /* power up hevc memories */
+ WRITE_VREG(DOS_MEM_PD_HEVC, 0);
+ /* remove hevc isolation */
+ } else if (core == VDEC_HCODEC)
+ pwr_ctrl_psci_smc(PDID_DOS_HCODEC, PWR_ON);
+
+ mutex_unlock(&vdec_mutex);
+
+ return;
+ }
+
if (vdec_on(core)) {
mutex_unlock(&vdec_mutex);
return;
return;
}
+ if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SC2) {
+ if (core == VDEC_1)
+ pwr_ctrl_psci_smc(PDID_DOS_VDEC, PWR_OFF);
+ else if (core == VDEC_HEVC) {
+ pwr_ctrl_psci_smc(PDID_DOS_HEVC, PWR_OFF);
+
+ /* disable hevc clock */
+ hevc_clock_off();
+ if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A)
+ hevc_back_clock_off();
+ }
+ else if (core == VDEC_HCODEC)
+ pwr_ctrl_psci_smc(PDID_DOS_HCODEC, PWR_OFF);
+
+ mutex_unlock(&vdec_mutex);
+ return;
+ }
+
is_power_ctrl_ver2 =
((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SM1) &&
(get_cpu_major_id() != AM_MESON_CPU_MAJOR_ID_TL1)) ? true : false;
codec_dmcbus_read(DMC_REQ_CTRL) & ~mask);
spin_unlock_irqrestore(&vdec_spin_lock, flags);
- if (is_cpu_tm2_revb()) {
+ if (is_cpu_tm2_revb() ||
+ (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SC2)) {
while (!(codec_dmcbus_read(TM2_REVB_DMC_CHAN_STS)
& mask))
;
codec_dmcbus_read(DMC_REQ_CTRL) & ~mask);
spin_unlock_irqrestore(&vdec_spin_lock, flags);
- if (is_cpu_tm2_revb()) {
+ if (is_cpu_tm2_revb() ||
+ (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SC2)) {
while (!(codec_dmcbus_read(TM2_REVB_DMC_CHAN_STS)
& mask))
;
* 19:sao
* 24:hevc_afifo
*/
- WRITE_VREG(DOS_SW_RESET3,
+ if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SC2) &&
+ (vdec->format == VFORMAT_AVS2)) {
+ WRITE_VREG(DOS_SW_RESET3,
(1<<3)|(1<<4)|(1<<8)|(1<<11)|
- (1<<12)|(1<<13)|(1<<14)|(1<<15)|
- (1<<17)|(1<<18)|(1<<19)|(1<<24));
+ (1<<12)|(1<<14)|(1<<15)|
+ (1<<17)|(1<<18)|(1<<19));
+ } else {
+ WRITE_VREG(DOS_SW_RESET3,
+ (1<<3)|(1<<4)|(1<<8)|(1<<11)|
+ (1<<12)|(1<<13)|(1<<14)|(1<<15)|
+ (1<<17)|(1<<18)|(1<<19)|(1<<24));
+ }
WRITE_VREG(DOS_SW_RESET3, 0);
int show_stream_buffer_status(char *buf,
int (*callback) (struct stream_buf_s *, char *));
+bool is_support_no_parser(void);
+
#endif /* VDEC_H */
//LpfSuperblockInfo neighbor_sb_lpf_info;
//#endif // LOOP_FILTER_BITMASK
};
-
+#ifdef DBG_LPF_DBLK_LVL
static int32_t myclamp(int32_t value, int32_t low, int32_t high) {
return value < low ? low : (value > high ? high : value);
}
-
+#endif
/*static int8_t extend_sign_7bits(uint8_t value) {
return (((value>>6) & 0x1)<<7) | (value&0x7f);
}*/
struct loopfilter *lf,
int32_t pic_width) {
BuffInfo_t* buf_spec = pbi->work_space_buf;
- int32_t i,dir;
+ int32_t i;
+#ifdef DBG_LPF_DBLK_LVL
+ int32_t dir;
int32_t filt_lvl[MAX_MB_PLANE], filt_lvl_r[MAX_MB_PLANE];
int32_t plane;
int32_t seg_id;
+#endif
// n_shift is the multiplier for lf_deltas
// the multiplier is 1 for when filter_lvl is between 0 and 31;
// 2 when filter_lvl is between 32 and 63
| (lfi->lfthr[i*2].mblim & 0xff);
WRITE_VREG(HEVC_DBLK_CFG9, thr);
}
-
+#ifdef DBG_LPF_DBLK_LVL
filt_lvl[0] = lf->filter_level[0];
filt_lvl[1] = lf->filter_level_u;
filt_lvl[2] = lf->filter_level_v;
level = 0;
WRITE_VREG(HEVC_DBLK_CFGA, level);
}
+#endif // DBG_LPF_DBLK_LVL
+
#ifdef DBG_LPF_DBLK_FORCED_OFF
if (lf->lf_pic_cnt == 2) {
printk("LF_PRINT: pic_cnt(%d) dblk forced off !!!\n", lf->lf_pic_cnt);
{
uint32_t cdef_data32 = (READ_VREG(HEVC_DBLK_CDEF1) & 0xffffff00);
cdef_data32 |= 17; // TODO ERROR :: cdef temp dma address left offset
+#ifdef DBG_LPF_CDEF_NO_PIPELINE
+ cdef_data32 |= (1<<17); // cdef test no pipeline for very small picture
+#endif
WRITE_VREG(HEVC_DBLK_CDEF1, cdef_data32);
}
// Picture count
void config_next_ref_info_hw(struct AV1HW_s *hw)
{
- int j;
- AV1_COMMON *const cm = &hw->pbi->common;
- av1_set_next_ref_frame_map(hw->pbi);
- WRITE_VREG(HEVC_PARSER_MEM_WR_ADDR, 0x1000);
+ int j;
+ AV1_COMMON *const cm = &hw->pbi->common;
+
+ av1_set_next_ref_frame_map(hw->pbi);
+ if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SC2)
+ WRITE_VREG(HEVC_PARSER_MEM_WR_ADDR, 0x11a0);
+ else
+ WRITE_VREG(HEVC_PARSER_MEM_WR_ADDR, 0x1000);
for (j = 0; j < 12; j++) {
unsigned int info =
av1_get_next_used_ref_info(cm, j);
cm->cur_frame->segment_feature[i] = (0x80000000 | (i << 22));
}
}
- WRITE_VREG(HEVC_PARSER_MEM_WR_ADDR, 0x1010 + (cur_pic_config->index));
+ if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_SC2)
+ WRITE_VREG(HEVC_PARSER_MEM_WR_ADDR, 0x11b0 + (cur_pic_config->index));
+ else
+ WRITE_VREG(HEVC_PARSER_MEM_WR_ADDR, 0x1010 + (cur_pic_config->index));
if (hw->aom_param.p.segmentation_enabled & 1) // segmentation_enabled
WRITE_VREG(HEVC_PARSER_MEM_RW_DATA, READ_VREG(AV1_REF_SEG_INFO));
else
(DEFAULT_VIDEO_BUFFER_SIZE >> 20);
static int slow_input;
-extern int enable_stream_mode_multi_dec;
-
/* #define DATA_DEBUG */
static int use_bufferlevelx10000 = 10000;
static int reset_canuse_buferlevel(int level);
mutex_lock(&amstream_mutex);
- if (get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) {
+ if ((get_cpu_major_id() >= AM_MESON_CPU_MAJOR_ID_G12A) &&
+ (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SC2)) {
r = check_efuse_chip(port->vformat);
if (r) {
pr_info("No support video format %d.\n", port->vformat);
get_esparser_stbuf_ops();
/* def used stbuf with parser if the feature disable. */
- if (!enable_stream_mode_multi_dec)
+ if (!is_support_no_parser())
ops = get_esparser_stbuf_ops();
}
}
}
- if (!enable_stream_mode_multi_dec) {
+ if (!is_support_no_parser()) {
if ((port->flag & PORT_FLAG_IN_USE) &&
((port->type & PORT_TYPE_FRAME) == 0)) {
mutex_unlock(&amstream_mutex);
}
}
}
+
return 0;
}
*/
break;
}
+ case AMSTREAM_IOC_INIT_EX_STBUF: {
+ struct stream_buffer_metainfo parm;
+ struct stream_buf_s *vbuf = &priv->vdec->vbuf;
+
+ if (copy_from_user(&parm, (void __user *)arg,
+ sizeof(struct stream_buffer_metainfo))) {
+ return -EFAULT;
+ }
+ stream_buffer_set_ext_buf(vbuf, parm.stbuf_start,
+ parm.stbuf_size, parm.stbuf_flag);
+ break;
+ }
+ case AMSTREAM_IOC_WR_STBUF_META: {
+ struct stream_buffer_metainfo meta;
+ struct stream_buf_s *vbuf = &priv->vdec->vbuf;
+
+ if (copy_from_user(&meta, (void __user *)arg,
+ sizeof(struct stream_buffer_metainfo))) {
+ return -EFAULT;
+ }
+ if (!vbuf->ext_buf_addr)
+ return -ENODEV;
+
+ stream_buffer_meta_write(vbuf, &meta);
+ break;
+ }
+ case AMSTREAM_IOC_GET_STBUF_STATUS: {
+ struct stream_buffer_status st;
+ struct stream_buf_s *pbuf = &priv->vdec->vbuf;
+
+ st.stbuf_start = pbuf->ext_buf_addr;
+ st.stbuf_size = pbuf->buf_size;
+ st.stbuf_rp = pbuf->ops->get_rp(pbuf);
+ st.stbuf_wp = pbuf->ops->get_wp(pbuf);
+ if (copy_to_user((void __user *)arg, &st,
+ sizeof(struct stream_buffer_status))) {
+ return -EFAULT;
+ }
+ break;
+ }
default:
r = -ENOIOCTLCMD;
break;
width = vdec->sys_info->width;
height = vdec->sys_info->height;
- memcpy(stbuf, get_def_parms(format),
- sizeof(*stbuf));
+ if (!stbuf->ext_buf_addr) {
+ memcpy(stbuf, get_def_parms(format),
+ sizeof(*stbuf));
+ }
stbuf->id = vdec->id;
stbuf->is_hevc = ((format == VFORMAT_HEVC) ||
void stream_buffer_set_ext_buf(struct stream_buf_s *stbuf,
ulong addr,
- u32 size)
+ u32 size,
+ u32 flag)
{
stbuf->ext_buf_addr = addr;
stbuf->buf_size = size;
+ stbuf->is_secure = ((flag & STBUF_META_FLAG_SECURE) != 0);
+
+ /*
+ pr_debug("%s, addr %lx, size 0x%x, secure %d\n", __func__,
+ stbuf->ext_buf_addr, stbuf->buf_size, stbuf->is_secure);
+ */
}
EXPORT_SYMBOL(stream_buffer_set_ext_buf);
+void stream_buffer_meta_write(struct stream_buf_s *stbuf,
+ struct stream_buffer_metainfo *meta)
+{
+ u32 wp;
+
+ if (meta->stbuf_pktaddr + meta->stbuf_pktsize < stbuf->buf_start + stbuf->buf_size)
+ wp = meta->stbuf_pktaddr + meta->stbuf_pktsize;
+ else
+ wp = meta->stbuf_pktaddr + meta->stbuf_pktsize - stbuf->buf_size;
+
+ stbuf->ops->set_wp(stbuf, wp);
+ /*
+ pr_debug("%s, update wp 0x%x + sz 0x%x --> 0x%x\n",
+ __func__, meta->stbuf_pktaddr, meta->stbuf_pktsize, wp);
+ */
+}
+EXPORT_SYMBOL(stream_buffer_meta_write);
+
ssize_t stream_buffer_write_ex(struct file *file,
struct stream_buf_s *stbuf,
const char __user *buf,
struct parser_args *pars);
void stream_buffer_set_ext_buf(struct stream_buf_s *stbuf,
- ulong addr,
- u32 size);
+ ulong addr,
+ u32 size,
+ u32 flag);
int stream_buffer_write(struct file *file,
struct stream_buf_s *stbuf,
size_t count,
int flags);
+void stream_buffer_meta_write(struct stream_buf_s *stbuf,
+ struct stream_buffer_metainfo *meta);
+
#endif /* STREAM_BUFFER_INTERFACE_H */
#include <linux/amlogic/media/codec_mm/codec_mm.h>
#include <linux/amlogic/media/frame_sync/ptsserv.h>
#include "../../frame_provider/decoder/utils/vdec.h"
+#include "../../common/chips/decoder_cpu_ver_info.h"
#include "stream_buffer_base.h"
#include "amports_priv.h"
#include "thread_rw.h"
if (stbuf->ext_buf_addr) {
addr = stbuf->ext_buf_addr;
size = stbuf->buf_size;
+ is_secure = stbuf->is_secure;
+ pages = (size >> PAGE_SHIFT);
} else {
flags |= CODEC_MM_FLAGS_FOR_VDECODER;
if (vdec->port_flag & PORT_FLAG_DRM) {
ret = -ENOMEM;
goto err;
}
-
- ret = vdec_set_input_buffer(vdec, addr, size);
- if (ret) {
- pr_err("[%d]: set input buffer err.\n", stbuf->id);
- goto err;
- }
+ }
+ ret = vdec_set_input_buffer(vdec, addr, size);
+ if (ret) {
+ pr_err("[%d]: set input buffer err.\n", stbuf->id);
+ goto err;
}
atomic_set(&stbuf->payload, 0);
stbuf->buf_page_num = pages;
stbuf->canusebuf_size = size;
- /* init pts server. */
- ret = pts_start(type_to_pts(stbuf->type));
- if (ret < 0) {
- pr_err("[%d]: pts server failed\n", stbuf->id);
- //goto err;//fixme
+ if (get_cpu_major_id() < AM_MESON_CPU_MAJOR_ID_SC2) {
+ /* init pts server. parser register w/r inside */
+ ret = pts_start(type_to_pts(stbuf->type));
+ if (ret < 0) {
+ pr_err("[%d]: pts server failed\n", stbuf->id);
+ //goto err;//fixme
+ }
}
-
/* init thread write. */
if (!(vdec_get_debug_flags() & 1) &&
- !codec_mm_video_tvp_enabled()) {
+ !codec_mm_video_tvp_enabled() &&
+ (!stbuf->ext_buf_addr)) {
int block_size = PAGE_SIZE << 4;
int buf_num = (2 * SZ_1M) / (PAGE_SIZE << 4);
size = size - 6 * 1024;
}
- if ((buf->type == BUF_TYPE_VIDEO)
- || (has_hevc_vdec() && buf->type == BUF_TYPE_HEVC))
- size -= READ_PARSER_REG(PARSER_VIDEO_HOLE);
-
+ if (!buf->no_parser) {
+ if ((buf->type == BUF_TYPE_VIDEO)
+ || (has_hevc_vdec() && buf->type == BUF_TYPE_HEVC))
+ size -= READ_PARSER_REG(PARSER_VIDEO_HOLE);
+ }
return size > 0 ? size : 0;
}
int r;
buf->first_tstamp = INVALID_PTS;
-
- r = stbuf_init(buf, NULL);/* reinit buffer */
- if (r < 0)
- pr_err("stbuf_release %d, stbuf_init failed\n", __LINE__);
-
+ if (!buf->ext_buf_addr) {
+ r = stbuf_init(buf, NULL);/* reinit buffer */
+ if (r < 0)
+ pr_err("stbuf_release %d, stbuf_init failed\n", __LINE__);
+ }
if (buf->flag & BUF_FLAG_ALLOC && buf->buf_start) {
codec_mm_free_for_dma(MEM_NAME, buf->buf_start);
buf->flag &= ~BUF_FLAG_ALLOC;
#define FETCHBUF_SIZE (64*1024)
#define USER_DATA_SIZE (8*1024)
+/* stream_buffer_metainfo stbuf_flag */
+#define STBUF_META_FLAG_SECURE (1 << 0)
+#define STBUF_META_FLAG_XXX1 (1 << 1)
+
struct vdec_s;
struct stream_buf_s;
u32 extpad[7];
} /*drminfo_t */;
+struct stream_buffer_metainfo {
+ union {
+ u32 stbuf_start;
+ u32 stbuf_pktaddr; //stbuf_pktaddr + stbuf_pktsize = wp
+ };
+ union {
+ u32 stbuf_size;
+ u32 stbuf_pktsize;
+ };
+ u32 stbuf_flag;
+ u32 stbuf_private;
+ u32 reserved[16];
+};
+
+struct stream_buffer_status {
+ u32 stbuf_wp;
+ u32 stbuf_rp;
+ u32 stbuf_start;
+ u32 stbuf_size;
+ u32 reserved[16];
+};
+
+
#define TYPE_DRMINFO_V2 0x100
#define TYPE_DRMINFO 0x80
#define TYPE_PATTERN 0x40