drm/nouveau/fifo: convert to new-style nvkm_engine
authorBen Skeggs <bskeggs@redhat.com>
Thu, 20 Aug 2015 04:54:22 +0000 (14:54 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Fri, 28 Aug 2015 02:40:46 +0000 (12:40 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
56 files changed:
drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h
drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild
drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h
drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c
drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c
drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c
drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c
drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c

index d9e494ba50338f89d727a5fa921f2a31c09457ff..84cc3e9cfed724a21cd240ed1e0bd97d60774e1e 100644 (file)
@@ -1,7 +1,5 @@
 #ifndef __NVKM_FIFO_H__
 #define __NVKM_FIFO_H__
-#define nvkm_fifo_chan(p) container_of((p), struct nvkm_fifo_chan, object)
-#define nvkm_fifo(p) container_of((p), struct nvkm_fifo, engine)
 #include <core/engine.h>
 #include <core/event.h>
 
@@ -33,46 +31,21 @@ struct nvkm_fifo_chan {
 
 extern const struct nvkm_object_func nvkm_fifo_chan_func;
 
-#include <core/gpuobj.h>
-struct nvkm_fifo_base {
-       struct nvkm_gpuobj gpuobj;
-};
-
-#define nvkm_fifo_context_create(p,e,c,g,s,a,f,d)                           \
-       nvkm_gpuobj_create((p), (e), (c), NV_ENGCTX_CLASS, (g), (s), (a), (f), (d))
-#define nvkm_fifo_context_destroy(p)                                        \
-       nvkm_gpuobj_destroy(&(p)->gpuobj)
-#define nvkm_fifo_context_init(p)                                           \
-       nvkm_gpuobj_init(&(p)->gpuobj)
-#define nvkm_fifo_context_fini(p,s)                                         \
-       nvkm_gpuobj_fini(&(p)->gpuobj, (s))
-
-#define _nvkm_fifo_context_dtor _nvkm_gpuobj_dtor
-#define _nvkm_fifo_context_init _nvkm_gpuobj_init
-#define _nvkm_fifo_context_fini _nvkm_gpuobj_fini
-#define _nvkm_fifo_context_rd32 _nvkm_gpuobj_rd32
-#define _nvkm_fifo_context_wr32 _nvkm_gpuobj_wr32
-
 struct nvkm_fifo {
-       struct nvkm_engine engine;
        const struct nvkm_fifo_func *func;
-
-       struct nvkm_event cevent; /* channel creation event */
-       struct nvkm_event uevent; /* async user trigger */
+       struct nvkm_engine engine;
 
        DECLARE_BITMAP(mask, NVKM_FIFO_CHID_NR);
        int nr;
        struct list_head chan;
        spinlock_t lock;
 
-       void (*pause)(struct nvkm_fifo *, unsigned long *);
-       void (*start)(struct nvkm_fifo *, unsigned long *);
+       struct nvkm_event uevent; /* async user trigger */
+       struct nvkm_event cevent; /* channel creation event */
 };
 
-struct nvkm_fifo_func {
-       void *(*dtor)(struct nvkm_fifo *);
-       const struct nvkm_fifo_chan_oclass *chan[];
-};
+void nvkm_fifo_pause(struct nvkm_fifo *, unsigned long *);
+void nvkm_fifo_start(struct nvkm_fifo *, unsigned long *);
 
 void nvkm_fifo_chan_put(struct nvkm_fifo *, unsigned long flags,
                        struct nvkm_fifo_chan **);
@@ -81,38 +54,16 @@ nvkm_fifo_chan_inst(struct nvkm_fifo *, u64 inst, unsigned long *flags);
 struct nvkm_fifo_chan *
 nvkm_fifo_chan_chid(struct nvkm_fifo *, int chid, unsigned long *flags);
 
-#define nvkm_fifo_create(o,e,c,fc,lc,d)                                     \
-       nvkm_fifo_create_((o), (e), (c), (fc), (lc), sizeof(**d), (void **)d)
-#define nvkm_fifo_init(p)                                                   \
-       nvkm_engine_init_old(&(p)->engine)
-#define nvkm_fifo_fini(p,s)                                                 \
-       nvkm_engine_fini_old(&(p)->engine, (s))
-
-int nvkm_fifo_create_(struct nvkm_object *, struct nvkm_object *,
-                        struct nvkm_oclass *, int min, int max,
-                        int size, void **);
-void nvkm_fifo_destroy(struct nvkm_fifo *);
-
-#define _nvkm_fifo_init _nvkm_engine_init
-#define _nvkm_fifo_fini _nvkm_engine_fini
-
-extern struct nvkm_oclass *nv04_fifo_oclass;
-extern struct nvkm_oclass *nv10_fifo_oclass;
-extern struct nvkm_oclass *nv17_fifo_oclass;
-extern struct nvkm_oclass *nv40_fifo_oclass;
-extern struct nvkm_oclass *nv50_fifo_oclass;
-extern struct nvkm_oclass *g84_fifo_oclass;
-extern struct nvkm_oclass *gf100_fifo_oclass;
-extern struct nvkm_oclass *gk104_fifo_oclass;
-extern struct nvkm_oclass *gk20a_fifo_oclass;
-extern struct nvkm_oclass *gk208_fifo_oclass;
-extern struct nvkm_oclass *gm204_fifo_oclass;
-extern struct nvkm_oclass *gm20b_fifo_oclass;
-
-int  nvkm_fifo_uevent_ctor(struct nvkm_object *, void *, u32,
-                          struct nvkm_notify *);
-void nvkm_fifo_uevent(struct nvkm_fifo *);
-
-void nv04_fifo_intr(struct nvkm_subdev *);
-int  nv04_fifo_context_attach(struct nvkm_object *, struct nvkm_object *);
+int nv04_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
+int nv10_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
+int nv17_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
+int nv40_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
+int nv50_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
+int g84_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
+int gf100_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
+int gk104_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
+int gk208_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
+int gk20a_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
+int gm204_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
+int gm20b_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **);
 #endif
index e056f7afc35cf74382f88d05d8ee429d1ebfe677..b8fc539e0a9946a28c413614a7268047685f4716 100644 (file)
@@ -231,7 +231,7 @@ nvkm_gpuobj_destroy(struct nvkm_gpuobj *gpuobj)
        nvkm_object_destroy(&gpuobj->object);
 }
 
-#include <engine/fifo.h>
+#include <engine/fifo/chan.h>
 
 int
 nvkm_gpuobj_create_(struct nvkm_object *parent, struct nvkm_object *engine,
index 764b46751eb9036bbc67001ffe4b4f57884a02a4..03763268248f3e58d29f6794a558b57fccb8e848 100644 (file)
@@ -26,6 +26,7 @@
 
 #include <core/client.h>
 #include <core/enum.h>
+#include <core/gpuobj.h>
 #include <engine/fifo.h>
 
 #include <nvif/class.h>
index ea3e8902f458f125328a5829a94ee73434bdbd62..62395ab742c5f16abefc9d69352937a1dcd17930 100644 (file)
@@ -88,7 +88,7 @@ nv4_chipset = {
        .timer = nv04_timer_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv04_fifo_new,
+       .fifo = nv04_fifo_new,
 //     .gr = nv04_gr_new,
 //     .sw = nv04_sw_new,
 };
@@ -108,7 +108,7 @@ nv5_chipset = {
        .timer = nv04_timer_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv04_fifo_new,
+       .fifo = nv04_fifo_new,
 //     .gr = nv04_gr_new,
 //     .sw = nv04_sw_new,
 };
@@ -148,7 +148,7 @@ nv11_chipset = {
        .timer = nv04_timer_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv10_fifo_new,
+       .fifo = nv10_fifo_new,
 //     .gr = nv10_gr_new,
 //     .sw = nv10_sw_new,
 };
@@ -169,7 +169,7 @@ nv15_chipset = {
        .timer = nv04_timer_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv10_fifo_new,
+       .fifo = nv10_fifo_new,
 //     .gr = nv10_gr_new,
 //     .sw = nv10_sw_new,
 };
@@ -190,7 +190,7 @@ nv17_chipset = {
        .timer = nv04_timer_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv17_fifo_new,
+       .fifo = nv17_fifo_new,
 //     .gr = nv10_gr_new,
 //     .sw = nv10_sw_new,
 };
@@ -211,7 +211,7 @@ nv18_chipset = {
        .timer = nv04_timer_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv17_fifo_new,
+       .fifo = nv17_fifo_new,
 //     .gr = nv10_gr_new,
 //     .sw = nv10_sw_new,
 };
@@ -232,7 +232,7 @@ nv1a_chipset = {
        .timer = nv04_timer_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv10_fifo_new,
+       .fifo = nv10_fifo_new,
 //     .gr = nv10_gr_new,
 //     .sw = nv10_sw_new,
 };
@@ -253,7 +253,7 @@ nv1f_chipset = {
        .timer = nv04_timer_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv17_fifo_new,
+       .fifo = nv17_fifo_new,
 //     .gr = nv10_gr_new,
 //     .sw = nv10_sw_new,
 };
@@ -274,7 +274,7 @@ nv20_chipset = {
        .timer = nv04_timer_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv17_fifo_new,
+       .fifo = nv17_fifo_new,
 //     .gr = nv20_gr_new,
 //     .sw = nv10_sw_new,
 };
@@ -295,7 +295,7 @@ nv25_chipset = {
        .timer = nv04_timer_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv17_fifo_new,
+       .fifo = nv17_fifo_new,
 //     .gr = nv25_gr_new,
 //     .sw = nv10_sw_new,
 };
@@ -316,7 +316,7 @@ nv28_chipset = {
        .timer = nv04_timer_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv17_fifo_new,
+       .fifo = nv17_fifo_new,
 //     .gr = nv25_gr_new,
 //     .sw = nv10_sw_new,
 };
@@ -337,7 +337,7 @@ nv2a_chipset = {
        .timer = nv04_timer_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv17_fifo_new,
+       .fifo = nv17_fifo_new,
 //     .gr = nv2a_gr_new,
 //     .sw = nv10_sw_new,
 };
@@ -358,7 +358,7 @@ nv30_chipset = {
        .timer = nv04_timer_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv17_fifo_new,
+       .fifo = nv17_fifo_new,
 //     .gr = nv30_gr_new,
 //     .sw = nv10_sw_new,
 };
@@ -379,7 +379,7 @@ nv31_chipset = {
        .timer = nv04_timer_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv17_fifo_new,
+       .fifo = nv17_fifo_new,
 //     .gr = nv30_gr_new,
 //     .mpeg = nv31_mpeg_new,
 //     .sw = nv10_sw_new,
@@ -401,7 +401,7 @@ nv34_chipset = {
        .timer = nv04_timer_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv17_fifo_new,
+       .fifo = nv17_fifo_new,
 //     .gr = nv34_gr_new,
 //     .mpeg = nv31_mpeg_new,
 //     .sw = nv10_sw_new,
@@ -423,7 +423,7 @@ nv35_chipset = {
        .timer = nv04_timer_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv17_fifo_new,
+       .fifo = nv17_fifo_new,
 //     .gr = nv35_gr_new,
 //     .sw = nv10_sw_new,
 };
@@ -444,7 +444,7 @@ nv36_chipset = {
        .timer = nv04_timer_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv17_fifo_new,
+       .fifo = nv17_fifo_new,
 //     .gr = nv35_gr_new,
 //     .mpeg = nv31_mpeg_new,
 //     .sw = nv10_sw_new,
@@ -468,7 +468,7 @@ nv40_chipset = {
        .volt = nv40_volt_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv40_fifo_new,
+       .fifo = nv40_fifo_new,
 //     .gr = nv40_gr_new,
 //     .mpeg = nv40_mpeg_new,
 //     .pm = nv40_pm_new,
@@ -493,7 +493,7 @@ nv41_chipset = {
        .volt = nv40_volt_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv40_fifo_new,
+       .fifo = nv40_fifo_new,
 //     .gr = nv40_gr_new,
 //     .mpeg = nv40_mpeg_new,
 //     .pm = nv40_pm_new,
@@ -518,7 +518,7 @@ nv42_chipset = {
        .volt = nv40_volt_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv40_fifo_new,
+       .fifo = nv40_fifo_new,
 //     .gr = nv40_gr_new,
 //     .mpeg = nv40_mpeg_new,
 //     .pm = nv40_pm_new,
@@ -543,7 +543,7 @@ nv43_chipset = {
        .volt = nv40_volt_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv40_fifo_new,
+       .fifo = nv40_fifo_new,
 //     .gr = nv40_gr_new,
 //     .mpeg = nv40_mpeg_new,
 //     .pm = nv40_pm_new,
@@ -568,7 +568,7 @@ nv44_chipset = {
        .volt = nv40_volt_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv40_fifo_new,
+       .fifo = nv40_fifo_new,
 //     .gr = nv40_gr_new,
 //     .mpeg = nv44_mpeg_new,
 //     .pm = nv40_pm_new,
@@ -593,7 +593,7 @@ nv45_chipset = {
        .volt = nv40_volt_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv40_fifo_new,
+       .fifo = nv40_fifo_new,
 //     .gr = nv40_gr_new,
 //     .mpeg = nv44_mpeg_new,
 //     .pm = nv40_pm_new,
@@ -618,7 +618,7 @@ nv46_chipset = {
        .volt = nv40_volt_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv40_fifo_new,
+       .fifo = nv40_fifo_new,
 //     .gr = nv40_gr_new,
 //     .mpeg = nv44_mpeg_new,
 //     .pm = nv40_pm_new,
@@ -643,7 +643,7 @@ nv47_chipset = {
        .volt = nv40_volt_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv40_fifo_new,
+       .fifo = nv40_fifo_new,
 //     .gr = nv40_gr_new,
 //     .mpeg = nv44_mpeg_new,
 //     .pm = nv40_pm_new,
@@ -668,7 +668,7 @@ nv49_chipset = {
        .volt = nv40_volt_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv40_fifo_new,
+       .fifo = nv40_fifo_new,
 //     .gr = nv40_gr_new,
 //     .mpeg = nv44_mpeg_new,
 //     .pm = nv40_pm_new,
@@ -693,7 +693,7 @@ nv4a_chipset = {
        .volt = nv40_volt_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv40_fifo_new,
+       .fifo = nv40_fifo_new,
 //     .gr = nv40_gr_new,
 //     .mpeg = nv44_mpeg_new,
 //     .pm = nv40_pm_new,
@@ -718,7 +718,7 @@ nv4b_chipset = {
        .volt = nv40_volt_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv40_fifo_new,
+       .fifo = nv40_fifo_new,
 //     .gr = nv40_gr_new,
 //     .mpeg = nv44_mpeg_new,
 //     .pm = nv40_pm_new,
@@ -743,7 +743,7 @@ nv4c_chipset = {
        .volt = nv40_volt_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv40_fifo_new,
+       .fifo = nv40_fifo_new,
 //     .gr = nv40_gr_new,
 //     .mpeg = nv44_mpeg_new,
 //     .pm = nv40_pm_new,
@@ -768,7 +768,7 @@ nv4e_chipset = {
        .volt = nv40_volt_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv40_fifo_new,
+       .fifo = nv40_fifo_new,
 //     .gr = nv40_gr_new,
 //     .mpeg = nv44_mpeg_new,
 //     .pm = nv40_pm_new,
@@ -796,7 +796,7 @@ nv50_chipset = {
        .volt = nv40_volt_new,
        .disp = nv50_disp_new,
        .dma = nv50_dma_new,
-//     .fifo = nv50_fifo_new,
+       .fifo = nv50_fifo_new,
 //     .gr = nv50_gr_new,
 //     .mpeg = nv50_mpeg_new,
 //     .pm = nv50_pm_new,
@@ -821,7 +821,7 @@ nv63_chipset = {
        .volt = nv40_volt_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv40_fifo_new,
+       .fifo = nv40_fifo_new,
 //     .gr = nv40_gr_new,
 //     .mpeg = nv44_mpeg_new,
 //     .pm = nv40_pm_new,
@@ -846,7 +846,7 @@ nv67_chipset = {
        .volt = nv40_volt_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv40_fifo_new,
+       .fifo = nv40_fifo_new,
 //     .gr = nv40_gr_new,
 //     .mpeg = nv44_mpeg_new,
 //     .pm = nv40_pm_new,
@@ -871,7 +871,7 @@ nv68_chipset = {
        .volt = nv40_volt_new,
        .disp = nv04_disp_new,
        .dma = nv04_dma_new,
-//     .fifo = nv40_fifo_new,
+       .fifo = nv40_fifo_new,
 //     .gr = nv40_gr_new,
 //     .mpeg = nv44_mpeg_new,
 //     .pm = nv40_pm_new,
@@ -901,7 +901,7 @@ nv84_chipset = {
        .cipher = g84_cipher_new,
        .disp = g84_disp_new,
        .dma = nv50_dma_new,
-//     .fifo = g84_fifo_new,
+       .fifo = g84_fifo_new,
 //     .gr = nv50_gr_new,
 //     .mpeg = g84_mpeg_new,
 //     .pm = g84_pm_new,
@@ -932,7 +932,7 @@ nv86_chipset = {
        .cipher = g84_cipher_new,
        .disp = g84_disp_new,
        .dma = nv50_dma_new,
-//     .fifo = g84_fifo_new,
+       .fifo = g84_fifo_new,
 //     .gr = nv50_gr_new,
 //     .mpeg = g84_mpeg_new,
 //     .pm = g84_pm_new,
@@ -963,7 +963,7 @@ nv92_chipset = {
        .cipher = g84_cipher_new,
        .disp = g84_disp_new,
        .dma = nv50_dma_new,
-//     .fifo = g84_fifo_new,
+       .fifo = g84_fifo_new,
 //     .gr = nv50_gr_new,
 //     .mpeg = g84_mpeg_new,
 //     .pm = g84_pm_new,
@@ -994,7 +994,7 @@ nv94_chipset = {
        .cipher = g84_cipher_new,
        .disp = g94_disp_new,
        .dma = nv50_dma_new,
-//     .fifo = g84_fifo_new,
+       .fifo = g84_fifo_new,
 //     .gr = nv50_gr_new,
 //     .mpeg = g84_mpeg_new,
 //     .pm = g84_pm_new,
@@ -1022,7 +1022,7 @@ nv96_chipset = {
        .bar = g84_bar_new,
        .volt = nv40_volt_new,
        .dma = nv50_dma_new,
-//     .fifo = g84_fifo_new,
+       .fifo = g84_fifo_new,
 //     .sw = nv50_sw_new,
 //     .gr = nv50_gr_new,
 //     .mpeg = g84_mpeg_new,
@@ -1053,7 +1053,7 @@ nv98_chipset = {
        .bar = g84_bar_new,
        .volt = nv40_volt_new,
        .dma = nv50_dma_new,
-//     .fifo = g84_fifo_new,
+       .fifo = g84_fifo_new,
 //     .sw = nv50_sw_new,
 //     .gr = nv50_gr_new,
        .mspdec = g98_mspdec_new,
@@ -1087,7 +1087,7 @@ nva0_chipset = {
        .cipher = g84_cipher_new,
        .disp = gt200_disp_new,
        .dma = nv50_dma_new,
-//     .fifo = g84_fifo_new,
+       .fifo = g84_fifo_new,
 //     .gr = nv50_gr_new,
 //     .mpeg = g84_mpeg_new,
 //     .pm = gt200_pm_new,
@@ -1118,7 +1118,7 @@ nva3_chipset = {
        .ce[0] = gt215_ce_new,
        .disp = gt215_disp_new,
        .dma = nv50_dma_new,
-//     .fifo = g84_fifo_new,
+       .fifo = g84_fifo_new,
 //     .gr = nv50_gr_new,
 //     .mpeg = g84_mpeg_new,
        .mspdec = gt215_mspdec_new,
@@ -1151,7 +1151,7 @@ nva5_chipset = {
        .ce[0] = gt215_ce_new,
        .disp = gt215_disp_new,
        .dma = nv50_dma_new,
-//     .fifo = g84_fifo_new,
+       .fifo = g84_fifo_new,
 //     .gr = nv50_gr_new,
        .mspdec = gt215_mspdec_new,
        .msppp = gt215_msppp_new,
@@ -1183,7 +1183,7 @@ nva8_chipset = {
        .ce[0] = gt215_ce_new,
        .disp = gt215_disp_new,
        .dma = nv50_dma_new,
-//     .fifo = g84_fifo_new,
+       .fifo = g84_fifo_new,
 //     .gr = nv50_gr_new,
        .mspdec = gt215_mspdec_new,
        .msppp = gt215_msppp_new,
@@ -1213,7 +1213,7 @@ nvaa_chipset = {
        .volt = nv40_volt_new,
        .disp = g94_disp_new,
        .dma = nv50_dma_new,
-//     .fifo = g84_fifo_new,
+       .fifo = g84_fifo_new,
 //     .gr = nv50_gr_new,
        .mspdec = g98_mspdec_new,
        .msppp = g98_msppp_new,
@@ -1244,7 +1244,7 @@ nvac_chipset = {
        .volt = nv40_volt_new,
        .disp = g94_disp_new,
        .dma = nv50_dma_new,
-//     .fifo = g84_fifo_new,
+       .fifo = g84_fifo_new,
 //     .gr = nv50_gr_new,
        .mspdec = g98_mspdec_new,
        .msppp = g98_msppp_new,
@@ -1277,7 +1277,7 @@ nvaf_chipset = {
        .ce[0] = gt215_ce_new,
        .disp = gt215_disp_new,
        .dma = nv50_dma_new,
-//     .fifo = g84_fifo_new,
+       .fifo = g84_fifo_new,
 //     .gr = nv50_gr_new,
        .mspdec = gt215_mspdec_new,
        .msppp = gt215_msppp_new,
@@ -1312,7 +1312,7 @@ nvc0_chipset = {
        .ce[1] = gf100_ce_new,
        .disp = gt215_disp_new,
        .dma = gf100_dma_new,
-//     .fifo = gf100_fifo_new,
+       .fifo = gf100_fifo_new,
 //     .gr = gf100_gr_new,
        .mspdec = gf100_mspdec_new,
        .msppp = gf100_msppp_new,
@@ -1346,7 +1346,7 @@ nvc1_chipset = {
        .ce[0] = gf100_ce_new,
        .disp = gt215_disp_new,
        .dma = gf100_dma_new,
-//     .fifo = gf100_fifo_new,
+       .fifo = gf100_fifo_new,
 //     .gr = gf108_gr_new,
        .mspdec = gf100_mspdec_new,
        .msppp = gf100_msppp_new,
@@ -1380,7 +1380,7 @@ nvc3_chipset = {
        .ce[0] = gf100_ce_new,
        .disp = gt215_disp_new,
        .dma = gf100_dma_new,
-//     .fifo = gf100_fifo_new,
+       .fifo = gf100_fifo_new,
 //     .gr = gf104_gr_new,
        .mspdec = gf100_mspdec_new,
        .msppp = gf100_msppp_new,
@@ -1415,7 +1415,7 @@ nvc4_chipset = {
        .ce[1] = gf100_ce_new,
        .disp = gt215_disp_new,
        .dma = gf100_dma_new,
-//     .fifo = gf100_fifo_new,
+       .fifo = gf100_fifo_new,
 //     .gr = gf104_gr_new,
        .mspdec = gf100_mspdec_new,
        .msppp = gf100_msppp_new,
@@ -1450,7 +1450,7 @@ nvc8_chipset = {
        .ce[1] = gf100_ce_new,
        .disp = gt215_disp_new,
        .dma = gf100_dma_new,
-//     .fifo = gf100_fifo_new,
+       .fifo = gf100_fifo_new,
 //     .gr = gf110_gr_new,
        .mspdec = gf100_mspdec_new,
        .msppp = gf100_msppp_new,
@@ -1485,7 +1485,7 @@ nvce_chipset = {
        .ce[1] = gf100_ce_new,
        .disp = gt215_disp_new,
        .dma = gf100_dma_new,
-//     .fifo = gf100_fifo_new,
+       .fifo = gf100_fifo_new,
 //     .gr = gf104_gr_new,
        .mspdec = gf100_mspdec_new,
        .msppp = gf100_msppp_new,
@@ -1519,7 +1519,7 @@ nvcf_chipset = {
        .ce[0] = gf100_ce_new,
        .disp = gt215_disp_new,
        .dma = gf100_dma_new,
-//     .fifo = gf100_fifo_new,
+       .fifo = gf100_fifo_new,
 //     .gr = gf104_gr_new,
        .mspdec = gf100_mspdec_new,
        .msppp = gf100_msppp_new,
@@ -1551,7 +1551,7 @@ nvd7_chipset = {
        .ce[0] = gf100_ce_new,
        .disp = gf119_disp_new,
        .dma = gf119_dma_new,
-//     .fifo = gf100_fifo_new,
+       .fifo = gf100_fifo_new,
 //     .gr = gf117_gr_new,
        .mspdec = gf100_mspdec_new,
        .msppp = gf100_msppp_new,
@@ -1585,7 +1585,7 @@ nvd9_chipset = {
        .ce[0] = gf100_ce_new,
        .disp = gf119_disp_new,
        .dma = gf119_dma_new,
-//     .fifo = gf100_fifo_new,
+       .fifo = gf100_fifo_new,
 //     .gr = gf119_gr_new,
        .mspdec = gf100_mspdec_new,
        .msppp = gf100_msppp_new,
@@ -1621,7 +1621,7 @@ nve4_chipset = {
        .ce[2] = gk104_ce_new,
        .disp = gk104_disp_new,
        .dma = gf119_dma_new,
-//     .fifo = gk104_fifo_new,
+       .fifo = gk104_fifo_new,
 //     .gr = gk104_gr_new,
        .mspdec = gk104_mspdec_new,
        .msppp = gf100_msppp_new,
@@ -1657,7 +1657,7 @@ nve6_chipset = {
        .ce[2] = gk104_ce_new,
        .disp = gk104_disp_new,
        .dma = gf119_dma_new,
-//     .fifo = gk104_fifo_new,
+       .fifo = gk104_fifo_new,
 //     .gr = gk104_gr_new,
        .mspdec = gk104_mspdec_new,
        .msppp = gf100_msppp_new,
@@ -1693,7 +1693,7 @@ nve7_chipset = {
        .ce[2] = gk104_ce_new,
        .disp = gk104_disp_new,
        .dma = gf119_dma_new,
-//     .fifo = gk104_fifo_new,
+       .fifo = gk104_fifo_new,
 //     .gr = gk104_gr_new,
        .mspdec = gk104_mspdec_new,
        .msppp = gf100_msppp_new,
@@ -1720,7 +1720,7 @@ nvea_chipset = {
        .volt = gk20a_volt_new,
        .ce[2] = gk104_ce_new,
        .dma = gf119_dma_new,
-//     .fifo = gk20a_fifo_new,
+       .fifo = gk20a_fifo_new,
 //     .gr = gk20a_gr_new,
 //     .pm = gk104_pm_new,
 //     .sw = gf100_sw_new,
@@ -1753,7 +1753,7 @@ nvf0_chipset = {
        .ce[2] = gk104_ce_new,
        .disp = gk110_disp_new,
        .dma = gf119_dma_new,
-//     .fifo = gk104_fifo_new,
+       .fifo = gk104_fifo_new,
 //     .gr = gk110_gr_new,
        .mspdec = gk104_mspdec_new,
        .msppp = gf100_msppp_new,
@@ -1789,7 +1789,7 @@ nvf1_chipset = {
        .ce[2] = gk104_ce_new,
        .disp = gk110_disp_new,
        .dma = gf119_dma_new,
-//     .fifo = gk104_fifo_new,
+       .fifo = gk104_fifo_new,
 //     .gr = gk110b_gr_new,
        .mspdec = gk104_mspdec_new,
        .msppp = gf100_msppp_new,
@@ -1825,7 +1825,7 @@ nv106_chipset = {
        .ce[2] = gk104_ce_new,
        .disp = gk110_disp_new,
        .dma = gf119_dma_new,
-//     .fifo = gk208_fifo_new,
+       .fifo = gk208_fifo_new,
 //     .gr = gk208_gr_new,
        .mspdec = gk104_mspdec_new,
        .msppp = gf100_msppp_new,
@@ -1860,7 +1860,7 @@ nv108_chipset = {
        .ce[2] = gk104_ce_new,
        .disp = gk110_disp_new,
        .dma = gf119_dma_new,
-//     .fifo = gk208_fifo_new,
+       .fifo = gk208_fifo_new,
 //     .gr = gk208_gr_new,
        .mspdec = gk104_mspdec_new,
        .msppp = gf100_msppp_new,
@@ -1893,7 +1893,7 @@ nv117_chipset = {
        .ce[2] = gk104_ce_new,
        .disp = gm107_disp_new,
        .dma = gf119_dma_new,
-//     .fifo = gk208_fifo_new,
+       .fifo = gk208_fifo_new,
 //     .gr = gm107_gr_new,
 //     .sw = gf100_sw_new,
 };
@@ -1922,7 +1922,7 @@ nv124_chipset = {
        .ce[2] = gm204_ce_new,
        .disp = gm204_disp_new,
        .dma = gf119_dma_new,
-//     .fifo = gm204_fifo_new,
+       .fifo = gm204_fifo_new,
 //     .gr = gm204_gr_new,
 //     .sw = gf100_sw_new,
 };
@@ -1951,7 +1951,7 @@ nv126_chipset = {
        .ce[2] = gm204_ce_new,
        .disp = gm204_disp_new,
        .dma = gf119_dma_new,
-//     .fifo = gm204_fifo_new,
+       .fifo = gm204_fifo_new,
 //     .gr = gm206_gr_new,
 //     .sw = gf100_sw_new,
 };
@@ -1972,7 +1972,7 @@ nv12b_chipset = {
        .timer = gk20a_timer_new,
        .ce[2] = gm204_ce_new,
        .dma = gf119_dma_new,
-//     .fifo = gm20b_fifo_new,
+       .fifo = gm20b_fifo_new,
 //     .gr = gm20b_gr_new,
 //     .sw = gf100_sw_new,
 };
index 09a1fe1604a2ef8076222778fe50aab80003bee8..d319f5680f440d4041d260241100151080b82d2d 100644 (file)
@@ -28,55 +28,46 @@ gf100_identify(struct nvkm_device *device)
 {
        switch (device->chipset) {
        case 0xc0:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] =  gf100_gr_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;
                break;
        case 0xc4:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;
                break;
        case 0xc3:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;
                break;
        case 0xce:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;
                break;
        case 0xcf:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] =  gf104_gr_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;
                break;
        case 0xc1:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] =  gf108_gr_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = gf108_pm_oclass;
                break;
        case 0xc8:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] =  gf110_gr_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;
                break;
        case 0xd9:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] =  gf119_gr_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = gf117_pm_oclass;
                break;
        case 0xd7:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] =  gf117_gr_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = gf117_pm_oclass;
index b3d25aad22f7146cac294c0a59e4c4c6c9f2148a..fe8298e02e9f3c3c723974a9e3fa652cb770a8ca 100644 (file)
@@ -28,48 +28,40 @@ gk104_identify(struct nvkm_device *device)
 {
        switch (device->chipset) {
        case 0xe4:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  gk104_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] =  gk104_gr_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = gk104_pm_oclass;
                break;
        case 0xe7:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  gk104_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] =  gk104_gr_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = gk104_pm_oclass;
                break;
        case 0xe6:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  gk104_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] =  gk104_gr_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = gk104_pm_oclass;
                break;
        case 0xea:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  gk20a_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] =  gk20a_gr_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = gk104_pm_oclass;
                break;
        case 0xf0:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  gk104_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] =  gk110_gr_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = &gk110_pm_oclass;
                break;
        case 0xf1:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  gk104_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] =  gk110b_gr_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = &gk110_pm_oclass;
                break;
        case 0x106:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  gk208_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] =  gk208_gr_oclass;
                break;
        case 0x108:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  gk208_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] =  gk208_gr_oclass;
                break;
index c0c1bd3989d603122f0596883e8aa50fa82d55f5..2362a634462c30c593d3a61adff0c3861853a072 100644 (file)
@@ -31,7 +31,6 @@ gm100_identify(struct nvkm_device *device)
 
 #if 0
 #endif
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  gk208_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] =  gm107_gr_oclass;
 #if 0
@@ -46,7 +45,6 @@ gm100_identify(struct nvkm_device *device)
 #endif
 #if 0
 #endif
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  gm204_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] =  gm204_gr_oclass;
 #if 0
@@ -59,7 +57,6 @@ gm100_identify(struct nvkm_device *device)
 #endif
 #if 0
 #endif
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  gm204_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] =  gm206_gr_oclass;
 #if 0
@@ -67,7 +64,6 @@ gm100_identify(struct nvkm_device *device)
                break;
        case 0x12b:
 
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  gm20b_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] =  gm20b_gr_oclass;
                break;
index 7a71d0c1d22f84d8398d20ada2c72098ff2cc4fb..edddbaa41b43ddeebfc9b1274dbf6bc259baf6db 100644 (file)
@@ -28,12 +28,10 @@ nv04_identify(struct nvkm_device *device)
 {
        switch (device->chipset) {
        case 0x04:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv04_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv04_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv04_gr_oclass;
                break;
        case 0x05:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv04_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv04_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv04_gr_oclass;
                break;
index 2b59c02fe7348c9f222027b774de2164bf7a7d94..f1ebb9bcda3b6e4b0aebc73aa27baf802cec1d5f 100644 (file)
@@ -31,37 +31,30 @@ nv10_identify(struct nvkm_device *device)
                device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
                break;
        case 0x15:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
                break;
        case 0x16:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
                break;
        case 0x1a:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
                break;
        case 0x11:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
                break;
        case 0x17:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
                break;
        case 0x1f:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
                break;
        case 0x18:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
                break;
index b4f8c479f3d7ab233467aa8cc001e1721ec069ae..f9c4dad1f8ff09762324101d6779cd43b5a1a416 100644 (file)
@@ -28,22 +28,18 @@ nv20_identify(struct nvkm_device *device)
 {
        switch (device->chipset) {
        case 0x20:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv20_gr_oclass;
                break;
        case 0x25:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv25_gr_oclass;
                break;
        case 0x28:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv25_gr_oclass;
                break;
        case 0x2a:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv2a_gr_oclass;
                break;
index fec9e3f38a5cdedb32d90eb0fa799a027483419f..b8e1e43723a3fb5494d11a616af604401d3713fc 100644 (file)
@@ -28,29 +28,24 @@ nv30_identify(struct nvkm_device *device)
 {
        switch (device->chipset) {
        case 0x30:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv30_gr_oclass;
                break;
        case 0x35:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv35_gr_oclass;
                break;
        case 0x31:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv30_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
                break;
        case 0x36:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv35_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
                break;
        case 0x34:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv34_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv31_mpeg_oclass;
index 553923ab0376db544dbbbcc660550a575c4d22a4..158ed5e395df490226bebdeed3f4cc2de3dcc8fa 100644 (file)
@@ -28,112 +28,96 @@ nv40_identify(struct nvkm_device *device)
 {
        switch (device->chipset) {
        case 0x40:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
                break;
        case 0x41:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
                break;
        case 0x42:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
                break;
        case 0x43:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv40_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
                break;
        case 0x45:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
                break;
        case 0x47:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
                break;
        case 0x49:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
                break;
        case 0x4b:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
                break;
        case 0x44:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
                break;
        case 0x46:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
                break;
        case 0x4a:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
                break;
        case 0x4c:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
                break;
        case 0x4e:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
                break;
        case 0x63:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
                break;
        case 0x67:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
                break;
        case 0x68:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv40_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv40_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv44_mpeg_oclass;
index f4c4ded9193fe46287e02c9f2b507652cbd72281..688b3e2d61ff92d7758da075d11f476783139fbe 100644 (file)
@@ -28,93 +28,79 @@ nv50_identify(struct nvkm_device *device)
 {
        switch (device->chipset) {
        case 0x50:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  nv50_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv50_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  nv50_pm_oclass;
                break;
        case 0x84:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
                break;
        case 0x86:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
                break;
        case 0x92:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
                break;
        case 0x94:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
                break;
        case 0x96:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
                break;
        case 0x98:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
                break;
        case 0xa0:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  gt200_pm_oclass;
                break;
        case 0xaa:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
                break;
        case 0xac:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
                break;
        case 0xa3:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
                device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
                break;
        case 0xa5:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
                break;
        case 0xa8:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
                break;
        case 0xaf:
-               device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
                device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
index e51372bdbf540e97d6a60026e02c3a562f2df5ac..2d11b328bee11a01087123c108137a2ac262c7b7 100644 (file)
  * OTHER DEALINGS IN THE SOFTWARE.
  */
 #include <engine/falcon.h>
-#include <engine/fifo.h>
 
+#include <core/gpuobj.h>
 #include <subdev/timer.h>
+#include <engine/fifo.h>
 
 static int
 nvkm_falcon_oclass_get(struct nvkm_oclass *oclass, int index)
index 4525b01598a9e669da442f88bca40739ec488e29..74993c144a84642411c8afac69836e2d3aad644a 100644 (file)
@@ -7,8 +7,8 @@ nvkm-y += nvkm/engine/fifo/nv50.o
 nvkm-y += nvkm/engine/fifo/g84.o
 nvkm-y += nvkm/engine/fifo/gf100.o
 nvkm-y += nvkm/engine/fifo/gk104.o
-nvkm-y += nvkm/engine/fifo/gk20a.o
 nvkm-y += nvkm/engine/fifo/gk208.o
+nvkm-y += nvkm/engine/fifo/gk20a.o
 nvkm-y += nvkm/engine/fifo/gm204.o
 nvkm-y += nvkm/engine/fifo/gm20b.o
 
index b693127d80e107daf57297f3644550500a692d82..1fbbfbe6ca9cf477c68dbc00c5ca94ba166a6705 100644 (file)
 #include "chan.h"
 
 #include <core/client.h>
+#include <core/gpuobj.h>
 #include <core/notify.h>
 
 #include <nvif/event.h>
 #include <nvif/unpack.h>
 
+void
+nvkm_fifo_pause(struct nvkm_fifo *fifo, unsigned long *flags)
+{
+       return fifo->func->pause(fifo, flags);
+}
+
+void
+nvkm_fifo_start(struct nvkm_fifo *fifo, unsigned long *flags)
+{
+       return fifo->func->start(fifo, flags);
+}
+
 void
 nvkm_fifo_chan_put(struct nvkm_fifo *fifo, unsigned long flags,
                   struct nvkm_fifo_chan **pchan)
@@ -95,7 +108,21 @@ nvkm_fifo_event_func = {
        .ctor = nvkm_fifo_event_ctor,
 };
 
-int
+static void
+nvkm_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
+{
+       struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
+       fifo->func->uevent_fini(fifo);
+}
+
+static void
+nvkm_fifo_uevent_init(struct nvkm_event *event, int type, int index)
+{
+       struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
+       fifo->func->uevent_init(fifo);
+}
+
+static int
 nvkm_fifo_uevent_ctor(struct nvkm_object *object, void *data, u32 size,
                      struct nvkm_notify *notify)
 {
@@ -113,6 +140,13 @@ nvkm_fifo_uevent_ctor(struct nvkm_object *object, void *data, u32 size,
        return ret;
 }
 
+static const struct nvkm_event_func
+nvkm_fifo_uevent_func = {
+       .ctor = nvkm_fifo_uevent_ctor,
+       .init = nvkm_fifo_uevent_init,
+       .fini = nvkm_fifo_uevent_fini,
+};
+
 void
 nvkm_fifo_uevent(struct nvkm_fifo *fifo)
 {
@@ -156,50 +190,88 @@ nvkm_fifo_class_get(struct nvkm_oclass *oclass, int index,
        return c;
 }
 
-void
-nvkm_fifo_destroy(struct nvkm_fifo *fifo)
+static void
+nvkm_fifo_intr(struct nvkm_engine *engine)
 {
-       nvkm_event_fini(&fifo->uevent);
+       struct nvkm_fifo *fifo = nvkm_fifo(engine);
+       fifo->func->intr(fifo);
+}
+
+static int
+nvkm_fifo_fini(struct nvkm_engine *engine, bool suspend)
+{
+       struct nvkm_fifo *fifo = nvkm_fifo(engine);
+       if (fifo->func->fini)
+               fifo->func->fini(fifo);
+       return 0;
+}
+
+static int
+nvkm_fifo_oneinit(struct nvkm_engine *engine)
+{
+       struct nvkm_fifo *fifo = nvkm_fifo(engine);
+       if (fifo->func->oneinit)
+               return fifo->func->oneinit(fifo);
+       return 0;
+}
+
+static int
+nvkm_fifo_init(struct nvkm_engine *engine)
+{
+       struct nvkm_fifo *fifo = nvkm_fifo(engine);
+       fifo->func->init(fifo);
+       return 0;
+}
+
+static void *
+nvkm_fifo_dtor(struct nvkm_engine *engine)
+{
+       struct nvkm_fifo *fifo = nvkm_fifo(engine);
+       void *data = fifo;
+       if (fifo->func->dtor)
+               data = fifo->func->dtor(fifo);
        nvkm_event_fini(&fifo->cevent);
-       nvkm_engine_destroy(&fifo->engine);
+       nvkm_event_fini(&fifo->uevent);
+       return data;
 }
 
 static const struct nvkm_engine_func
-nvkm_fifo_func = {
+nvkm_fifo = {
+       .dtor = nvkm_fifo_dtor,
+       .oneinit = nvkm_fifo_oneinit,
+       .init = nvkm_fifo_init,
+       .fini = nvkm_fifo_fini,
+       .intr = nvkm_fifo_intr,
        .base.sclass = nvkm_fifo_class_get,
 };
 
 int
-nvkm_fifo_create_(struct nvkm_object *parent, struct nvkm_object *engine,
-                 struct nvkm_oclass *oclass,
-                 int min, int max, int length, void **pobject)
+nvkm_fifo_ctor(const struct nvkm_fifo_func *func, struct nvkm_device *device,
+              int index, int nr, struct nvkm_fifo *fifo)
 {
-       struct nvkm_fifo *fifo;
-       int  nr = max + 1;
-       int cnt = nr - min;
        int ret;
 
-       ret = nvkm_engine_create_(parent, engine, oclass, true, "PFIFO",
-                                 "fifo", length, pobject);
-       fifo = *pobject;
-       if (ret)
-               return ret;
-
-       fifo->engine.func = &nvkm_fifo_func;
+       fifo->func = func;
        INIT_LIST_HEAD(&fifo->chan);
+       spin_lock_init(&fifo->lock);
 
-       fifo->nr = nr;
-       if (WARN_ON(fifo->nr > NVKM_FIFO_CHID_NR)) {
+       if (WARN_ON(fifo->nr > NVKM_FIFO_CHID_NR))
                fifo->nr = NVKM_FIFO_CHID_NR;
-               cnt = fifo->nr - min;
-       }
-       bitmap_fill(fifo->mask, NVKM_FIFO_CHID_NR);
-       bitmap_clear(fifo->mask, min, cnt);
+       else
+               fifo->nr = nr;
+       bitmap_clear(fifo->mask, 0, fifo->nr);
 
-       ret = nvkm_event_init(&nvkm_fifo_event_func, 1, 1, &fifo->cevent);
+       ret = nvkm_engine_ctor(&nvkm_fifo, device, index, 0x00000100,
+                              true, &fifo->engine);
        if (ret)
                return ret;
 
-       spin_lock_init(&fifo->lock);
-       return 0;
+       if (func->uevent_init) {
+               ret = nvkm_event_init(&nvkm_fifo_uevent_func, 1, 1,
+                                     &fifo->uevent);
+               if (ret)
+                       return ret;
+       }
+
+       return nvkm_event_init(&nvkm_fifo_event_func, 1, 1, &fifo->cevent);
 }
index a02c60f340c0a0abaccc8549de21e6cb167da8a2..4ed06abdc91766c05c281892e1d2b5af2dfcad16 100644 (file)
@@ -24,6 +24,7 @@
 #include "chan.h"
 
 #include <core/client.h>
+#include <core/gpuobj.h>
 #include <core/oproxy.h>
 #include <subdev/mmu.h>
 #include <engine/dma.h>
index bfec12dbf49293b8e3837b3687fe856650b72140..55dc415c5c08b2373ab566b8caec1b218a2476bf 100644 (file)
@@ -1,5 +1,6 @@
 #ifndef __NVKM_FIFO_CHAN_H__
 #define __NVKM_FIFO_CHAN_H__
+#define nvkm_fifo_chan(p) container_of((p), struct nvkm_fifo_chan, object)
 #include "priv.h"
 
 struct nvkm_fifo_chan_func {
index eafa87886643e0b6aab2bc62c1233bd5cd8e126f..52cbc4b47b2c63a2f33a2a9c3db7e746fd206f3c 100644 (file)
@@ -73,7 +73,7 @@ nv04_fifo_dma_fini(struct nvkm_fifo_chan *base)
        struct nv04_fifo *fifo = chan->fifo;
        struct nvkm_device *device = fifo->base.engine.subdev.device;
        struct nvkm_memory *fctx = device->imem->ramfc;
-       struct ramfc_desc *c;
+       const struct nv04_fifo_ramfc *c;
        unsigned long flags;
        u32 mask = fifo->base.nr - 1;
        u32 data = chan->ramfc;
@@ -90,7 +90,7 @@ nv04_fifo_dma_fini(struct nvkm_fifo_chan *base)
                nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 0);
                nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0);
 
-               c = fifo->ramfc_desc;
+               c = fifo->ramfc;
                do {
                        u32 rm = ((1ULL << c->bits) - 1) << c->regs;
                        u32 cm = ((1ULL << c->bits) - 1) << c->ctxs;
@@ -99,7 +99,7 @@ nv04_fifo_dma_fini(struct nvkm_fifo_chan *base)
                        nvkm_wo32(fctx, c->ctxp + data, cv | (rv << c->ctxs));
                } while ((++c)->bits);
 
-               c = fifo->ramfc_desc;
+               c = fifo->ramfc;
                do {
                        nvkm_wr32(device, c->regp, 0x00000000);
                } while ((++c)->bits);
@@ -136,7 +136,7 @@ nv04_fifo_dma_dtor(struct nvkm_fifo_chan *base)
        struct nv04_fifo_chan *chan = nv04_fifo_chan(base);
        struct nv04_fifo *fifo = chan->fifo;
        struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem;
-       struct ramfc_desc *c = fifo->ramfc_desc;
+       const struct nv04_fifo_ramfc *c = fifo->ramfc;
 
        nvkm_kmap(imem->ramfc);
        do {
index 1ad16205305f8b9e2a3fbc4d934461a534814df7..d8e4d55704d1dea98cbac8bb6eb65dac518cbc7e 100644 (file)
@@ -25,6 +25,7 @@
 #include "regsnv04.h"
 
 #include <core/client.h>
+#include <core/gpuobj.h>
 #include <subdev/instmem.h>
 
 #include <nvif/class.h>
index 2fbb9d4f0900e5765b70284fb2c5ed40aee9db12..1424dd9b62998692fc7425c10041a7ba87866dad 100644 (file)
@@ -25,6 +25,7 @@
 #include "regsnv04.h"
 
 #include <core/client.h>
+#include <core/gpuobj.h>
 #include <subdev/instmem.h>
 
 #include <nvif/class.h>
index 00fa9d3eff7ad3b9adbda3c223a1ec36088b5b9e..ff7b529764fe03935a50f7d66b30e25d4497999b 100644 (file)
 #include "channv50.h"
 
 static void
-g84_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
+g84_fifo_uevent_fini(struct nvkm_fifo *fifo)
 {
-       struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
        struct nvkm_device *device = fifo->engine.subdev.device;
        nvkm_mask(device, 0x002140, 0x40000000, 0x00000000);
 }
 
 static void
-g84_fifo_uevent_init(struct nvkm_event *event, int type, int index)
+g84_fifo_uevent_init(struct nvkm_fifo *fifo)
 {
-       struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
        struct nvkm_device *device = fifo->engine.subdev.device;
        nvkm_mask(device, 0x002140, 0x40000000, 0x40000000);
 }
 
-static const struct nvkm_event_func
-g84_fifo_uevent_func = {
-       .ctor = nvkm_fifo_uevent_ctor,
-       .init = g84_fifo_uevent_init,
-       .fini = g84_fifo_uevent_fini,
-};
-
 static const struct nvkm_fifo_func
-g84_fifo_func = {
+g84_fifo = {
+       .dtor = nv50_fifo_dtor,
+       .oneinit = nv50_fifo_oneinit,
+       .init = nv50_fifo_init,
+       .intr = nv04_fifo_intr,
+       .pause = nv04_fifo_pause,
+       .start = nv04_fifo_start,
+       .uevent_init = g84_fifo_uevent_init,
+       .uevent_fini = g84_fifo_uevent_fini,
        .chan = {
                &g84_fifo_dma_oclass,
                &g84_fifo_gpfifo_oclass,
@@ -56,50 +55,8 @@ g84_fifo_func = {
        },
 };
 
-static int
-g84_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
-             struct nvkm_oclass *oclass, void *data, u32 size,
-             struct nvkm_object **pobject)
+int
+g84_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
 {
-       struct nvkm_device *device = (void *)parent;
-       struct nv50_fifo *fifo;
-       int ret;
-
-       ret = nvkm_fifo_create(parent, engine, oclass, 1, 127, &fifo);
-       *pobject = nv_object(fifo);
-       if (ret)
-               return ret;
-
-       fifo->base.func = &g84_fifo_func;
-
-       ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000,
-                             false, &fifo->runlist[0]);
-       if (ret)
-               return ret;
-
-       ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000,
-                             false, &fifo->runlist[1]);
-       if (ret)
-               return ret;
-
-       ret = nvkm_event_init(&g84_fifo_uevent_func, 1, 1, &fifo->base.uevent);
-       if (ret)
-               return ret;
-
-       nv_subdev(fifo)->unit = 0x00000100;
-       nv_subdev(fifo)->intr = nv04_fifo_intr;
-       fifo->base.pause = nv04_fifo_pause;
-       fifo->base.start = nv04_fifo_start;
-       return 0;
+       return nv50_fifo_new_(&g84_fifo, device, index, pfifo);
 }
-
-struct nvkm_oclass *
-g84_fifo_oclass = &(struct nvkm_oclass) {
-       .handle = NV_ENGINE(FIFO, 0x84),
-       .ofuncs = &(struct nvkm_ofuncs) {
-               .ctor = g84_fifo_ctor,
-               .dtor = nv50_fifo_dtor,
-               .init = nv50_fifo_init,
-               .fini = _nvkm_fifo_fini,
-       },
-};
index e8598fc447962275de80e18f60e2e4480967a1e4..bc094223f6877744200934677170fb446cd450ca 100644 (file)
@@ -26,6 +26,7 @@
 
 #include <core/client.h>
 #include <core/enum.h>
+#include <core/gpuobj.h>
 #include <core/handle.h>
 #include <subdev/bar.h>
 #include <engine/sw.h>
 #include <nvif/class.h>
 
 static void
-gf100_fifo_uevent_init(struct nvkm_event *event, int type, int index)
+gf100_fifo_uevent_init(struct nvkm_fifo *fifo)
 {
-       struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
        struct nvkm_device *device = fifo->engine.subdev.device;
        nvkm_mask(device, 0x002140, 0x80000000, 0x80000000);
 }
 
 static void
-gf100_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
+gf100_fifo_uevent_fini(struct nvkm_fifo *fifo)
 {
-       struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
        struct nvkm_device *device = fifo->engine.subdev.device;
        nvkm_mask(device, 0x002140, 0x80000000, 0x00000000);
 }
 
-static const struct nvkm_event_func
-gf100_fifo_uevent_func = {
-       .ctor = nvkm_fifo_uevent_ctor,
-       .init = gf100_fifo_uevent_init,
-       .fini = gf100_fifo_uevent_fini,
-};
-
 void
 gf100_fifo_runlist_update(struct gf100_fifo *fifo)
 {
@@ -64,7 +56,7 @@ gf100_fifo_runlist_update(struct gf100_fifo *fifo)
        struct nvkm_memory *cur;
        int nr = 0;
 
-       mutex_lock(&nv_subdev(fifo)->mutex);
+       mutex_lock(&subdev->mutex);
        cur = fifo->runlist.mem[fifo->runlist.active];
        fifo->runlist.active = !fifo->runlist.active;
 
@@ -83,7 +75,7 @@ gf100_fifo_runlist_update(struct gf100_fifo *fifo)
                               !(nvkm_rd32(device, 0x00227c) & 0x00100000),
                               msecs_to_jiffies(2000)) == 0)
                nvkm_error(subdev, "runlist update timeout\n");
-       mutex_unlock(&nv_subdev(fifo)->mutex);
+       mutex_unlock(&subdev->mutex);
 }
 
 static inline int
@@ -106,6 +98,8 @@ gf100_fifo_engidx(struct gf100_fifo *fifo, u32 engn)
 static inline struct nvkm_engine *
 gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn)
 {
+       struct nvkm_device *device = fifo->base.engine.subdev.device;
+
        switch (engn) {
        case 0: engn = NVDEV_ENGINE_GR; break;
        case 1: engn = NVDEV_ENGINE_MSVLD; break;
@@ -117,7 +111,7 @@ gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn)
                return NULL;
        }
 
-       return nvkm_engine(fifo, engn);
+       return nvkm_device_engine(device, engn);
 }
 
 static void
@@ -167,7 +161,7 @@ gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine,
        list_del_init(&chan->head);
        chan->killed = true;
 
-       fifo->mask |= 1ULL << nv_engidx(engine);
+       fifo->mask |= 1ULL << engine->subdev.index;
        schedule_work(&fifo->fault);
 }
 
@@ -333,7 +327,7 @@ gf100_fifo_intr_fault(struct gf100_fifo *fifo, int unit)
                        nvkm_mask(device, 0x001718, 0x00000000, 0x00000000);
                        break;
                default:
-                       engine = nvkm_engine(fifo, eu->data2);
+                       engine = nvkm_device_engine(device, eu->data2);
                        break;
                }
        }
@@ -457,10 +451,11 @@ gf100_fifo_intr_engine(struct gf100_fifo *fifo)
 }
 
 static void
-gf100_fifo_intr(struct nvkm_subdev *subdev)
+gf100_fifo_intr(struct nvkm_fifo *base)
 {
-       struct gf100_fifo *fifo = (void *)subdev;
-       struct nvkm_device *device = fifo->base.engine.subdev.device;
+       struct gf100_fifo *fifo = gf100_fifo(base);
+       struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
+       struct nvkm_device *device = subdev->device;
        u32 mask = nvkm_rd32(device, 0x002140);
        u32 stat = nvkm_rd32(device, 0x002100) & mask;
 
@@ -531,17 +526,52 @@ gf100_fifo_intr(struct nvkm_subdev *subdev)
 }
 
 static int
-gf100_fifo_init(struct nvkm_object *object)
+gf100_fifo_oneinit(struct nvkm_fifo *base)
 {
-       struct gf100_fifo *fifo = (void *)object;
-       struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
-       struct nvkm_device *device = subdev->device;
-       int ret, i;
+       struct gf100_fifo *fifo = gf100_fifo(base);
+       struct nvkm_device *device = fifo->base.engine.subdev.device;
+       int ret;
 
-       ret = nvkm_fifo_init(&fifo->base);
+       ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000,
+                             false, &fifo->runlist.mem[0]);
+       if (ret)
+               return ret;
+
+       ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000,
+                             false, &fifo->runlist.mem[1]);
        if (ret)
                return ret;
 
+       init_waitqueue_head(&fifo->runlist.wait);
+
+       ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 0x1000,
+                             0x1000, false, &fifo->user.mem);
+       if (ret)
+               return ret;
+
+       ret = nvkm_bar_umap(device->bar, 128 * 0x1000, 12, &fifo->user.bar);
+       if (ret)
+               return ret;
+
+       nvkm_memory_map(fifo->user.mem, &fifo->user.bar, 0);
+       return 0;
+}
+
+static void
+gf100_fifo_fini(struct nvkm_fifo *base)
+{
+       struct gf100_fifo *fifo = gf100_fifo(base);
+       flush_work(&fifo->fault);
+}
+
+static void
+gf100_fifo_init(struct nvkm_fifo *base)
+{
+       struct gf100_fifo *fifo = gf100_fifo(base);
+       struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
+       struct nvkm_device *device = subdev->device;
+       int i;
+
        nvkm_wr32(device, 0x000204, 0xffffffff);
        nvkm_wr32(device, 0x002204, 0xffffffff);
 
@@ -571,90 +601,44 @@ gf100_fifo_init(struct nvkm_object *object)
        nvkm_wr32(device, 0x002100, 0xffffffff);
        nvkm_wr32(device, 0x002140, 0x7fffffff);
        nvkm_wr32(device, 0x002628, 0x00000001); /* ENGINE_INTR_EN */
-       return 0;
 }
 
-static void
-gf100_fifo_dtor(struct nvkm_object *object)
+static void *
+gf100_fifo_dtor(struct nvkm_fifo *base)
 {
-       struct gf100_fifo *fifo = (void *)object;
-
+       struct gf100_fifo *fifo = gf100_fifo(base);
        nvkm_vm_put(&fifo->user.bar);
        nvkm_memory_del(&fifo->user.mem);
        nvkm_memory_del(&fifo->runlist.mem[0]);
        nvkm_memory_del(&fifo->runlist.mem[1]);
-
-       nvkm_fifo_destroy(&fifo->base);
+       return fifo;
 }
 
 static const struct nvkm_fifo_func
-gf100_fifo_func = {
+gf100_fifo = {
+       .dtor = gf100_fifo_dtor,
+       .oneinit = gf100_fifo_oneinit,
+       .init = gf100_fifo_init,
+       .fini = gf100_fifo_fini,
+       .intr = gf100_fifo_intr,
+       .uevent_init = gf100_fifo_uevent_init,
+       .uevent_fini = gf100_fifo_uevent_fini,
        .chan = {
                &gf100_fifo_gpfifo_oclass,
                NULL
        },
 };
 
-static int
-gf100_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
-               struct nvkm_oclass *oclass, void *data, u32 size,
-               struct nvkm_object **pobject)
+int
+gf100_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
 {
-       struct nvkm_device *device = (void *)parent;
-       struct nvkm_bar *bar = device->bar;
        struct gf100_fifo *fifo;
-       int ret;
-
-       ret = nvkm_fifo_create(parent, engine, oclass, 0, 127, &fifo);
-       *pobject = nv_object(fifo);
-       if (ret)
-               return ret;
-
-       fifo->base.func = &gf100_fifo_func;
 
+       if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL)))
+               return -ENOMEM;
        INIT_LIST_HEAD(&fifo->chan);
        INIT_WORK(&fifo->fault, gf100_fifo_recover_work);
+       *pfifo = &fifo->base;
 
-       ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000,
-                             false, &fifo->runlist.mem[0]);
-       if (ret)
-               return ret;
-
-       ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000,
-                             false, &fifo->runlist.mem[1]);
-       if (ret)
-               return ret;
-
-       init_waitqueue_head(&fifo->runlist.wait);
-
-       ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 0x1000,
-                             0x1000, false, &fifo->user.mem);
-       if (ret)
-               return ret;
-
-       ret = nvkm_bar_umap(bar, 128 * 0x1000, 12, &fifo->user.bar);
-       if (ret)
-               return ret;
-
-       nvkm_memory_map(fifo->user.mem, &fifo->user.bar, 0);
-
-       ret = nvkm_event_init(&gf100_fifo_uevent_func, 1, 1, &fifo->base.uevent);
-       if (ret)
-               return ret;
-
-       nv_subdev(fifo)->unit = 0x00000100;
-       nv_subdev(fifo)->intr = gf100_fifo_intr;
-       return 0;
+       return nvkm_fifo_ctor(&gf100_fifo, device, index, 128, &fifo->base);
 }
-
-
-struct nvkm_oclass *
-gf100_fifo_oclass = &(struct nvkm_oclass) {
-       .handle = NV_ENGINE(FIFO, 0xc0),
-       .ofuncs = &(struct nvkm_ofuncs) {
-               .ctor = gf100_fifo_ctor,
-               .dtor = gf100_fifo_dtor,
-               .init = gf100_fifo_init,
-               .fini = _nvkm_fifo_fini,
-       },
-};
index a69f61f3ecac18c20fda69706ca46eb023c07f33..465b52dee27777d47721837dbb0d13a1d80c6094 100644 (file)
 
 #include <core/client.h>
 #include <core/enum.h>
+#include <core/gpuobj.h>
 #include <core/handle.h>
 #include <subdev/bar.h>
 #include <engine/sw.h>
 
 #include <nvif/class.h>
 
-static void
-gk104_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
+void
+gk104_fifo_uevent_fini(struct nvkm_fifo *fifo)
 {
-       struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
        struct nvkm_device *device = fifo->engine.subdev.device;
        nvkm_mask(device, 0x002140, 0x80000000, 0x00000000);
 }
 
-static void
-gk104_fifo_uevent_init(struct nvkm_event *event, int type, int index)
+void
+gk104_fifo_uevent_init(struct nvkm_fifo *fifo)
 {
-       struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
        struct nvkm_device *device = fifo->engine.subdev.device;
        nvkm_mask(device, 0x002140, 0x80000000, 0x80000000);
 }
 
-static const struct nvkm_event_func
-gk104_fifo_uevent_func = {
-       .ctor = nvkm_fifo_uevent_ctor,
-       .init = gk104_fifo_uevent_init,
-       .fini = gk104_fifo_uevent_fini,
-};
-
 void
 gk104_fifo_runlist_update(struct gk104_fifo *fifo, u32 engine)
 {
@@ -65,7 +57,7 @@ gk104_fifo_runlist_update(struct gk104_fifo *fifo, u32 engine)
        struct nvkm_memory *cur;
        int nr = 0;
 
-       mutex_lock(&nv_subdev(fifo)->mutex);
+       mutex_lock(&subdev->mutex);
        cur = engn->runlist[engn->cur_runlist];
        engn->cur_runlist = !engn->cur_runlist;
 
@@ -84,15 +76,16 @@ gk104_fifo_runlist_update(struct gk104_fifo *fifo, u32 engine)
                               (engine * 0x08)) & 0x00100000),
                                msecs_to_jiffies(2000)) == 0)
                nvkm_error(subdev, "runlist %d update timeout\n", engine);
-       mutex_unlock(&nv_subdev(fifo)->mutex);
+       mutex_unlock(&subdev->mutex);
 }
 
 static inline struct nvkm_engine *
 gk104_fifo_engine(struct gk104_fifo *fifo, u32 engn)
 {
+       struct nvkm_device *device = fifo->base.engine.subdev.device;
        u64 subdevs = gk104_fifo_engine_subdev(engn);
        if (subdevs)
-               return nvkm_engine(fifo, __ffs(subdevs));
+               return nvkm_device_engine(device, __ffs(subdevs));
        return NULL;
 }
 
@@ -136,14 +129,14 @@ gk104_fifo_recover(struct gk104_fifo *fifo, struct nvkm_engine *engine,
        u32 chid = chan->base.chid;
 
        nvkm_error(subdev, "%s engine fault on channel %d, recovering...\n",
-                  nvkm_subdev_name[nv_subdev(engine)->index], chid);
+                  nvkm_subdev_name[engine->subdev.index], chid);
        assert_spin_locked(&fifo->base.lock);
 
        nvkm_mask(device, 0x800004 + (chid * 0x08), 0x00000800, 0x00000800);
        list_del_init(&chan->head);
        chan->killed = true;
 
-       fifo->mask |= 1ULL << nv_engidx(engine);
+       fifo->mask |= 1ULL << engine->subdev.index;
        schedule_work(&fifo->fault);
 }
 
@@ -399,7 +392,7 @@ gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit)
                        nvkm_mask(device, 0x001718, 0x00000000, 0x00000000);
                        break;
                default:
-                       engine = nvkm_engine(fifo, eu->data2);
+                       engine = nvkm_device_engine(device, eu->data2);
                        break;
                }
        }
@@ -542,11 +535,12 @@ gk104_fifo_intr_engine(struct gk104_fifo *fifo)
        nvkm_fifo_uevent(&fifo->base);
 }
 
-static void
-gk104_fifo_intr(struct nvkm_subdev *subdev)
+void
+gk104_fifo_intr(struct nvkm_fifo *base)
 {
-       struct gk104_fifo *fifo = (void *)subdev;
-       struct nvkm_device *device = fifo->base.engine.subdev.device;
+       struct gk104_fifo *fifo = gk104_fifo(base);
+       struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
+       struct nvkm_device *device = subdev->device;
        u32 mask = nvkm_rd32(device, 0x002140);
        u32 stat = nvkm_rd32(device, 0x002100) & mask;
 
@@ -633,33 +627,62 @@ gk104_fifo_intr(struct nvkm_subdev *subdev)
        }
 }
 
+void
+gk104_fifo_fini(struct nvkm_fifo *base)
+{
+       struct gk104_fifo *fifo = gk104_fifo(base);
+       struct nvkm_device *device = fifo->base.engine.subdev.device;
+       flush_work(&fifo->fault);
+       /* allow mmu fault interrupts, even when we're not using fifo */
+       nvkm_mask(device, 0x002140, 0x10000000, 0x10000000);
+}
+
 int
-gk104_fifo_fini(struct nvkm_object *object, bool suspend)
+gk104_fifo_oneinit(struct nvkm_fifo *base)
 {
-       struct gk104_fifo *fifo = (void *)object;
+       struct gk104_fifo *fifo = gk104_fifo(base);
        struct nvkm_device *device = fifo->base.engine.subdev.device;
-       int ret;
+       int ret, i;
 
-       ret = nvkm_fifo_fini(&fifo->base, suspend);
+       for (i = 0; i < ARRAY_SIZE(fifo->engine); i++) {
+               ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
+                                     0x8000, 0x1000, false,
+                                     &fifo->engine[i].runlist[0]);
+               if (ret)
+                       return ret;
+
+               ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
+                                     0x8000, 0x1000, false,
+                                     &fifo->engine[i].runlist[1]);
+               if (ret)
+                       return ret;
+
+               init_waitqueue_head(&fifo->engine[i].wait);
+               INIT_LIST_HEAD(&fifo->engine[i].chan);
+       }
+
+       ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
+                             fifo->base.nr * 0x200, 0x1000, true,
+                             &fifo->user.mem);
        if (ret)
                return ret;
 
-       /* allow mmu fault interrupts, even when we're not using fifo */
-       nvkm_mask(device, 0x002140, 0x10000000, 0x10000000);
+       ret = nvkm_bar_umap(device->bar, fifo->base.nr * 0x200, 12,
+                           &fifo->user.bar);
+       if (ret)
+               return ret;
+
+       nvkm_memory_map(fifo->user.mem, &fifo->user.bar, 0);
        return 0;
 }
 
-int
-gk104_fifo_init(struct nvkm_object *object)
+void
+gk104_fifo_init(struct nvkm_fifo *base)
 {
-       struct gk104_fifo *fifo = (void *)object;
+       struct gk104_fifo *fifo = gk104_fifo(base);
        struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
        struct nvkm_device *device = subdev->device;
-       int ret, i;
-
-       ret = nvkm_fifo_init(&fifo->base);
-       if (ret)
-               return ret;
+       int i;
 
        /* enable all available PBDMA units */
        nvkm_wr32(device, 0x000204, 0xffffffff);
@@ -683,13 +706,12 @@ gk104_fifo_init(struct nvkm_object *object)
 
        nvkm_wr32(device, 0x002100, 0xffffffff);
        nvkm_wr32(device, 0x002140, 0x7fffffff);
-       return 0;
 }
 
-void
-gk104_fifo_dtor(struct nvkm_object *object)
+void *
+gk104_fifo_dtor(struct nvkm_fifo *base)
 {
-       struct gk104_fifo *fifo = (void *)object;
+       struct gk104_fifo *fifo = gk104_fifo(base);
        int i;
 
        nvkm_vm_put(&fifo->user.bar);
@@ -700,11 +722,32 @@ gk104_fifo_dtor(struct nvkm_object *object)
                nvkm_memory_del(&fifo->engine[i].runlist[0]);
        }
 
-       nvkm_fifo_destroy(&fifo->base);
+       return fifo;
+}
+
+int
+gk104_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device,
+               int index, int nr, struct nvkm_fifo **pfifo)
+{
+       struct gk104_fifo *fifo;
+
+       if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL)))
+               return -ENOMEM;
+       INIT_WORK(&fifo->fault, gk104_fifo_recover_work);
+       *pfifo = &fifo->base;
+
+       return nvkm_fifo_ctor(func, device, index, nr, &fifo->base);
 }
 
 static const struct nvkm_fifo_func
-gk104_fifo_func = {
+gk104_fifo = {
+       .dtor = gk104_fifo_dtor,
+       .oneinit = gk104_fifo_oneinit,
+       .init = gk104_fifo_init,
+       .fini = gk104_fifo_fini,
+       .intr = gk104_fifo_intr,
+       .uevent_init = gk104_fifo_uevent_init,
+       .uevent_fini = gk104_fifo_uevent_fini,
        .chan = {
                &gk104_fifo_gpfifo_oclass,
                NULL
@@ -712,72 +755,7 @@ gk104_fifo_func = {
 };
 
 int
-gk104_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
-               struct nvkm_oclass *oclass, void *data, u32 size,
-               struct nvkm_object **pobject)
+gk104_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
 {
-       struct nvkm_device *device = (void *)parent;
-       struct nvkm_bar *bar = device->bar;
-       struct gk104_fifo_impl *impl = (void *)oclass;
-       struct gk104_fifo *fifo;
-       int ret, i;
-
-       ret = nvkm_fifo_create(parent, engine, oclass, 0,
-                              impl->channels - 1, &fifo);
-       *pobject = nv_object(fifo);
-       if (ret)
-               return ret;
-
-       fifo->base.func = &gk104_fifo_func;
-
-       INIT_WORK(&fifo->fault, gk104_fifo_recover_work);
-
-       for (i = 0; i < ARRAY_SIZE(fifo->engine); i++) {
-               ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
-                                     0x8000, 0x1000, false,
-                                     &fifo->engine[i].runlist[0]);
-               if (ret)
-                       return ret;
-
-               ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
-                                     0x8000, 0x1000, false,
-                                     &fifo->engine[i].runlist[1]);
-               if (ret)
-                       return ret;
-
-               init_waitqueue_head(&fifo->engine[i].wait);
-               INIT_LIST_HEAD(&fifo->engine[i].chan);
-       }
-
-       ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
-                             impl->channels * 0x200, 0x1000,
-                             true, &fifo->user.mem);
-       if (ret)
-               return ret;
-
-       ret = nvkm_bar_umap(bar, impl->channels * 0x200, 12, &fifo->user.bar);
-       if (ret)
-               return ret;
-
-       nvkm_memory_map(fifo->user.mem, &fifo->user.bar, 0);
-
-       ret = nvkm_event_init(&gk104_fifo_uevent_func, 1, 1, &fifo->base.uevent);
-       if (ret)
-               return ret;
-
-       nv_subdev(fifo)->unit = 0x00000100;
-       nv_subdev(fifo)->intr = gk104_fifo_intr;
-       return 0;
+       return gk104_fifo_new_(&gk104_fifo, device, index, 4096, pfifo);
 }
-
-struct nvkm_oclass *
-gk104_fifo_oclass = &(struct gk104_fifo_impl) {
-       .base.handle = NV_ENGINE(FIFO, 0xe0),
-       .base.ofuncs = &(struct nvkm_ofuncs) {
-               .ctor = gk104_fifo_ctor,
-               .dtor = gk104_fifo_dtor,
-               .init = gk104_fifo_init,
-               .fini = gk104_fifo_fini,
-       },
-       .channels = 4096,
-}.base;
index 1103e6b1ee5a62878ad38d0a212b6403767533d2..7a5c544a5ffbb743f8617f3201800b4fbca5bbf4 100644 (file)
@@ -26,23 +26,17 @@ struct gk104_fifo {
        int spoon_nr;
 };
 
-struct gk104_fifo_impl {
-       struct nvkm_oclass base;
-       u32 channels;
-};
-
-int  gk104_fifo_ctor(struct nvkm_object *, struct nvkm_object *,
-                   struct nvkm_oclass *, void *, u32,
-                   struct nvkm_object **);
-void gk104_fifo_dtor(struct nvkm_object *);
-int  gk104_fifo_init(struct nvkm_object *);
-int  gk104_fifo_fini(struct nvkm_object *, bool);
+int gk104_fifo_new_(const struct nvkm_fifo_func *, struct nvkm_device *,
+                   int index, int nr, struct nvkm_fifo **);
+void *gk104_fifo_dtor(struct nvkm_fifo *);
+int gk104_fifo_oneinit(struct nvkm_fifo *);
+void gk104_fifo_init(struct nvkm_fifo *);
+void gk104_fifo_fini(struct nvkm_fifo *);
+void gk104_fifo_intr(struct nvkm_fifo *);
+void gk104_fifo_uevent_init(struct nvkm_fifo *);
+void gk104_fifo_uevent_fini(struct nvkm_fifo *);
 void gk104_fifo_runlist_update(struct gk104_fifo *, u32 engine);
 
-int  gm204_fifo_ctor(struct nvkm_object *, struct nvkm_object *,
-                   struct nvkm_oclass *, void *, u32,
-                   struct nvkm_object **);
-
 static inline u64
 gk104_fifo_engine_subdev(int engine)
 {
index 927092217a06f6b227caa791e440cffd0d144722..ce01c1a7d41cb3a7b396498495da39b986c298ec 100644 (file)
  * Authors: Ben Skeggs
  */
 #include "gk104.h"
+#include "changk104.h"
 
-struct nvkm_oclass *
-gk208_fifo_oclass = &(struct gk104_fifo_impl) {
-       .base.handle = NV_ENGINE(FIFO, 0x08),
-       .base.ofuncs = &(struct nvkm_ofuncs) {
-               .ctor = gk104_fifo_ctor,
-               .dtor = gk104_fifo_dtor,
-               .init = gk104_fifo_init,
-               .fini = _nvkm_fifo_fini,
+static const struct nvkm_fifo_func
+gk208_fifo = {
+       .dtor = gk104_fifo_dtor,
+       .oneinit = gk104_fifo_oneinit,
+       .init = gk104_fifo_init,
+       .fini = gk104_fifo_fini,
+       .intr = gk104_fifo_intr,
+       .uevent_init = gk104_fifo_uevent_init,
+       .uevent_fini = gk104_fifo_uevent_fini,
+       .chan = {
+               &gk104_fifo_gpfifo_oclass,
+               NULL
        },
-       .channels = 1024,
-}.base;
+};
+
+int
+gk208_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
+{
+       return gk104_fifo_new_(&gk208_fifo, device, index, 1024, pfifo);
+}
index b30dc87a1357c6bda79ba3a4b98c3bb5405197b0..b47fe98f41818ab7105abbb237577f1665932268 100644 (file)
  * DEALINGS IN THE SOFTWARE.
  */
 #include "gk104.h"
+#include "changk104.h"
 
-struct nvkm_oclass *
-gk20a_fifo_oclass = &(struct gk104_fifo_impl) {
-       .base.handle = NV_ENGINE(FIFO, 0xea),
-       .base.ofuncs = &(struct nvkm_ofuncs) {
-               .ctor = gk104_fifo_ctor,
-               .dtor = gk104_fifo_dtor,
-               .init = gk104_fifo_init,
-               .fini = gk104_fifo_fini,
+static const struct nvkm_fifo_func
+gk20a_fifo = {
+       .dtor = gk104_fifo_dtor,
+       .oneinit = gk104_fifo_oneinit,
+       .init = gk104_fifo_init,
+       .fini = gk104_fifo_fini,
+       .intr = gk104_fifo_intr,
+       .uevent_init = gk104_fifo_uevent_init,
+       .uevent_fini = gk104_fifo_uevent_fini,
+       .chan = {
+               &gk104_fifo_gpfifo_oclass,
+               NULL
        },
-       .channels = 128,
-}.base;
+};
+
+int
+gk20a_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
+{
+       return gk104_fifo_new_(&gk20a_fifo, device, index, 128, pfifo);
+}
index 18c68ac741a0a40bb2d60ebe99b5b9f907df6556..2db629f1bf7e80a6fc051bcbe6a8e1b89caac191 100644 (file)
 #include "changk104.h"
 
 static const struct nvkm_fifo_func
-gm204_fifo_func = {
+gm204_fifo = {
+       .dtor = gk104_fifo_dtor,
+       .oneinit = gk104_fifo_oneinit,
+       .init = gk104_fifo_init,
+       .fini = gk104_fifo_fini,
+       .intr = gk104_fifo_intr,
+       .uevent_init = gk104_fifo_uevent_init,
+       .uevent_fini = gk104_fifo_uevent_fini,
        .chan = {
                &gm204_fifo_gpfifo_oclass,
                NULL
@@ -33,26 +40,7 @@ gm204_fifo_func = {
 };
 
 int
-gm204_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
-               struct nvkm_oclass *oclass, void *data, u32 size,
-               struct nvkm_object **pobject)
+gm204_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
 {
-       int ret = gk104_fifo_ctor(parent, engine, oclass, data, size, pobject);
-       if (ret == 0) {
-               struct gk104_fifo *fifo = (void *)*pobject;
-               fifo->base.func = &gm204_fifo_func;
-       }
-       return ret;
+       return gk104_fifo_new_(&gm204_fifo, device, index, 4096, pfifo);
 }
-
-struct nvkm_oclass *
-gm204_fifo_oclass = &(struct gk104_fifo_impl) {
-       .base.handle = NV_ENGINE(FIFO, 0x24),
-       .base.ofuncs = &(struct nvkm_ofuncs) {
-               .ctor = gm204_fifo_ctor,
-               .dtor = gk104_fifo_dtor,
-               .init = gk104_fifo_init,
-               .fini = _nvkm_fifo_fini,
-       },
-       .channels = 4096,
-}.base;
index 4abf547c34e64048e93328e04b1b2eaa240bfe54..ae6375d9760f8d962017648ed1293e3d1f15a5e2 100644 (file)
  * DEALINGS IN THE SOFTWARE.
  */
 #include "gk104.h"
+#include "changk104.h"
 
-struct nvkm_oclass *
-gm20b_fifo_oclass = &(struct gk104_fifo_impl) {
-       .base.handle = NV_ENGINE(FIFO, 0x2b),
-       .base.ofuncs = &(struct nvkm_ofuncs) {
-               .ctor = gm204_fifo_ctor,
-               .dtor = gk104_fifo_dtor,
-               .init = gk104_fifo_init,
-               .fini = gk104_fifo_fini,
+static const struct nvkm_fifo_func
+gm20b_fifo = {
+       .dtor = gk104_fifo_dtor,
+       .oneinit = gk104_fifo_oneinit,
+       .init = gk104_fifo_init,
+       .fini = gk104_fifo_fini,
+       .intr = gk104_fifo_intr,
+       .uevent_init = gk104_fifo_uevent_init,
+       .uevent_fini = gk104_fifo_uevent_fini,
+       .chan = {
+               &gm204_fifo_gpfifo_oclass,
+               NULL
        },
-       .channels = 512,
-}.base;
+};
+
+int
+gm20b_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
+{
+       return gk104_fifo_new_(&gm20b_fifo, device, index, 512, pfifo);
+}
index eb9195a6f375f054472937307f0db137493f04b6..5d76c3013a80765f22406236894a882f545cec00 100644 (file)
@@ -24,6 +24,7 @@
 #include "changf100.h"
 
 #include <core/client.h>
+#include <core/gpuobj.h>
 #include <subdev/fb.h>
 #include <subdev/timer.h>
 
index 2595cf92ff8048cb2e447c6c6f27e1c677e83323..fe39981915b6442b75ba1661f7ad91ad03140c50 100644 (file)
@@ -24,6 +24,7 @@
 #include "changk104.h"
 
 #include <core/client.h>
+#include <core/gpuobj.h>
 #include <subdev/fb.h>
 #include <subdev/mmu.h>
 #include <subdev/timer.h>
index d1ad3fa72c343933f105fc3ce16593293854d66c..e6f04e87139a2866e8eed66c836b55c94548f1b4 100644 (file)
@@ -32,8 +32,8 @@
 #include <subdev/timer.h>
 #include <engine/sw.h>
 
-static struct ramfc_desc
-nv04_ramfc[] = {
+static const struct nv04_fifo_ramfc
+nv04_fifo_ramfc[] = {
        { 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
        { 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
        { 16,  0, 0x08,  0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
@@ -46,10 +46,10 @@ nv04_ramfc[] = {
 };
 
 void
-nv04_fifo_pause(struct nvkm_fifo *obj, unsigned long *pflags)
+nv04_fifo_pause(struct nvkm_fifo *base, unsigned long *pflags)
 __acquires(fifo->base.lock)
 {
-       struct nv04_fifo *fifo = container_of(obj, typeof(*fifo), base);
+       struct nv04_fifo *fifo = nv04_fifo(base);
        struct nvkm_device *device = fifo->base.engine.subdev.device;
        unsigned long flags;
 
@@ -82,10 +82,10 @@ __acquires(fifo->base.lock)
 }
 
 void
-nv04_fifo_start(struct nvkm_fifo *obj, unsigned long *pflags)
+nv04_fifo_start(struct nvkm_fifo *base, unsigned long *pflags)
 __releases(fifo->base.lock)
 {
-       struct nv04_fifo *fifo = container_of(obj, typeof(*fifo), base);
+       struct nv04_fifo *fifo = nv04_fifo(base);
        struct nvkm_device *device = fifo->base.engine.subdev.device;
        unsigned long flags = *pflags;
 
@@ -236,10 +236,11 @@ nv04_fifo_dma_pusher(struct nv04_fifo *fifo, u32 chid)
 }
 
 void
-nv04_fifo_intr(struct nvkm_subdev *subdev)
+nv04_fifo_intr(struct nvkm_fifo *base)
 {
+       struct nv04_fifo *fifo = nv04_fifo(base);
+       struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
        struct nvkm_device *device = subdev->device;
-       struct nv04_fifo *fifo = (void *)subdev;
        u32 mask = nvkm_rd32(device, NV03_PFIFO_INTR_EN_0);
        u32 stat = nvkm_rd32(device, NV03_PFIFO_INTR_0) & mask;
        u32 reassign, chid, get, sem;
@@ -293,20 +294,15 @@ nv04_fifo_intr(struct nvkm_subdev *subdev)
        nvkm_wr32(device, NV03_PFIFO_CACHES, reassign);
 }
 
-int
-nv04_fifo_init(struct nvkm_object *object)
+void
+nv04_fifo_init(struct nvkm_fifo *base)
 {
-       struct nv04_fifo *fifo = (void *)object;
+       struct nv04_fifo *fifo = nv04_fifo(base);
        struct nvkm_device *device = fifo->base.engine.subdev.device;
        struct nvkm_instmem *imem = device->imem;
        struct nvkm_ramht *ramht = imem->ramht;
        struct nvkm_memory *ramro = imem->ramro;
        struct nvkm_memory *ramfc = imem->ramfc;
-       int ret;
-
-       ret = nvkm_fifo_init(&fifo->base);
-       if (ret)
-               return ret;
 
        nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff);
        nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff);
@@ -325,54 +321,44 @@ nv04_fifo_init(struct nvkm_object *object)
        nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);
        nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
        nvkm_wr32(device, NV03_PFIFO_CACHES, 1);
-       return 0;
 }
 
-void
-nv04_fifo_dtor(struct nvkm_object *object)
-{
-       struct nv04_fifo *fifo = (void *)object;
-       nvkm_fifo_destroy(&fifo->base);
-}
-
-static const struct nvkm_fifo_func
-nv04_fifo_func = {
-       .chan = {
-               &nv04_fifo_dma_oclass,
-               NULL
-       },
-};
-
-static int
-nv04_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
-              struct nvkm_oclass *oclass, void *data, u32 size,
-              struct nvkm_object **pobject)
+int
+nv04_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device,
+              int index, int nr, const struct nv04_fifo_ramfc *ramfc,
+              struct nvkm_fifo **pfifo)
 {
        struct nv04_fifo *fifo;
        int ret;
 
-       ret = nvkm_fifo_create(parent, engine, oclass, 0, 15, &fifo);
-       *pobject = nv_object(fifo);
+       if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL)))
+               return -ENOMEM;
+       fifo->ramfc = ramfc;
+       *pfifo = &fifo->base;
+
+       ret = nvkm_fifo_ctor(func, device, index, nr, &fifo->base);
        if (ret)
                return ret;
 
-       fifo->base.func = &nv04_fifo_func;
-
-       nv_subdev(fifo)->unit = 0x00000100;
-       nv_subdev(fifo)->intr = nv04_fifo_intr;
-       fifo->base.pause = nv04_fifo_pause;
-       fifo->base.start = nv04_fifo_start;
-       fifo->ramfc_desc = nv04_ramfc;
+       set_bit(nr - 1, fifo->base.mask); /* inactive channel */
        return 0;
 }
 
-struct nvkm_oclass *
-nv04_fifo_oclass = &(struct nvkm_oclass) {
-       .handle = NV_ENGINE(FIFO, 0x04),
-       .ofuncs = &(struct nvkm_ofuncs) {
-               .ctor = nv04_fifo_ctor,
-               .dtor = nv04_fifo_dtor,
-               .init = nv04_fifo_init,
-               .fini = _nvkm_fifo_fini,
+static const struct nvkm_fifo_func
+nv04_fifo = {
+       .init = nv04_fifo_init,
+       .intr = nv04_fifo_intr,
+       .pause = nv04_fifo_pause,
+       .start = nv04_fifo_start,
+       .chan = {
+               &nv04_fifo_dma_oclass,
+               NULL
        },
 };
+
+int
+nv04_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
+{
+       return nv04_fifo_new_(&nv04_fifo, device, index, 16,
+                             nv04_fifo_ramfc, pfifo);
+}
index c33dc56f8e022a27035b8c88a9dabd82623d3913..03f60004bf7ca3ce4dcd01380dc7bfbf34a5a65f 100644 (file)
@@ -3,7 +3,7 @@
 #define nv04_fifo(p) container_of((p), struct nv04_fifo, base)
 #include "priv.h"
 
-struct ramfc_desc {
+struct nv04_fifo_ramfc {
        unsigned bits:6;
        unsigned ctxs:5;
        unsigned ctxp:8;
@@ -13,9 +13,11 @@ struct ramfc_desc {
 
 struct nv04_fifo {
        struct nvkm_fifo base;
-       struct ramfc_desc *ramfc_desc;
+       const struct nv04_fifo_ramfc *ramfc;
 };
 
-void nv04_fifo_dtor(struct nvkm_object *);
-int  nv04_fifo_init(struct nvkm_object *);
+int nv04_fifo_new_(const struct nvkm_fifo_func *, struct nvkm_device *,
+                  int index, int nr, const struct nv04_fifo_ramfc *,
+                  struct nvkm_fifo **);
+void nv04_fifo_init(struct nvkm_fifo *);
 #endif
index d7fab9598fb0e9a841ef34ef56e291efc289027c..f9a87deb2b3dc3fd1f11e926bdb1bec17cf56b2b 100644 (file)
@@ -25,8 +25,8 @@
 #include "channv04.h"
 #include "regsnv04.h"
 
-static struct ramfc_desc
-nv10_ramfc[] = {
+static const struct nv04_fifo_ramfc
+nv10_fifo_ramfc[] = {
        { 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
        { 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
        { 32,  0, 0x08,  0, NV10_PFIFO_CACHE1_REF_CNT },
@@ -40,43 +40,20 @@ nv10_ramfc[] = {
 };
 
 static const struct nvkm_fifo_func
-nv10_fifo_func = {
+nv10_fifo = {
+       .init = nv04_fifo_init,
+       .intr = nv04_fifo_intr,
+       .pause = nv04_fifo_pause,
+       .start = nv04_fifo_start,
        .chan = {
                &nv10_fifo_dma_oclass,
                NULL
        },
 };
 
-static int
-nv10_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
-              struct nvkm_oclass *oclass, void *data, u32 size,
-              struct nvkm_object **pobject)
+int
+nv10_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
 {
-       struct nv04_fifo *fifo;
-       int ret;
-
-       ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &fifo);
-       *pobject = nv_object(fifo);
-       if (ret)
-               return ret;
-
-       fifo->base.func = &nv10_fifo_func;
-
-       nv_subdev(fifo)->unit = 0x00000100;
-       nv_subdev(fifo)->intr = nv04_fifo_intr;
-       fifo->base.pause = nv04_fifo_pause;
-       fifo->base.start = nv04_fifo_start;
-       fifo->ramfc_desc = nv10_ramfc;
-       return 0;
+       return nv04_fifo_new_(&nv10_fifo, device, index, 32,
+                             nv10_fifo_ramfc, pfifo);
 }
-
-struct nvkm_oclass *
-nv10_fifo_oclass = &(struct nvkm_oclass) {
-       .handle = NV_ENGINE(FIFO, 0x10),
-       .ofuncs = &(struct nvkm_ofuncs) {
-               .ctor = nv10_fifo_ctor,
-               .dtor = nv04_fifo_dtor,
-               .init = nv04_fifo_init,
-               .fini = _nvkm_fifo_fini,
-       },
-};
index a8e28fc24e756c390fe1adb493919cc80da5cde7..f6d383a21222e07b48ea569801ae227ba734c6b4 100644 (file)
@@ -28,8 +28,8 @@
 #include <core/ramht.h>
 #include <subdev/instmem.h>
 
-static struct ramfc_desc
-nv17_ramfc[] = {
+static const struct nv04_fifo_ramfc
+nv17_fifo_ramfc[] = {
        { 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
        { 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
        { 32,  0, 0x08,  0, NV10_PFIFO_CACHE1_REF_CNT },
@@ -47,20 +47,15 @@ nv17_ramfc[] = {
        {}
 };
 
-static int
-nv17_fifo_init(struct nvkm_object *object)
+static void
+nv17_fifo_init(struct nvkm_fifo *base)
 {
-       struct nv04_fifo *fifo = (void *)object;
+       struct nv04_fifo *fifo = nv04_fifo(base);
        struct nvkm_device *device = fifo->base.engine.subdev.device;
        struct nvkm_instmem *imem = device->imem;
        struct nvkm_ramht *ramht = imem->ramht;
        struct nvkm_memory *ramro = imem->ramro;
        struct nvkm_memory *ramfc = imem->ramfc;
-       int ret;
-
-       ret = nvkm_fifo_init(&fifo->base);
-       if (ret)
-               return ret;
 
        nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff);
        nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff);
@@ -80,47 +75,23 @@ nv17_fifo_init(struct nvkm_object *object)
        nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);
        nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
        nvkm_wr32(device, NV03_PFIFO_CACHES, 1);
-       return 0;
 }
 
 static const struct nvkm_fifo_func
-nv17_fifo_func = {
+nv17_fifo = {
+       .init = nv17_fifo_init,
+       .intr = nv04_fifo_intr,
+       .pause = nv04_fifo_pause,
+       .start = nv04_fifo_start,
        .chan = {
                &nv17_fifo_dma_oclass,
                NULL
        },
 };
 
-static int
-nv17_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
-              struct nvkm_oclass *oclass, void *data, u32 size,
-              struct nvkm_object **pobject)
+int
+nv17_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
 {
-       struct nv04_fifo *fifo;
-       int ret;
-
-       ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &fifo);
-       *pobject = nv_object(fifo);
-       if (ret)
-               return ret;
-
-       fifo->base.func = &nv17_fifo_func;
-
-       nv_subdev(fifo)->unit = 0x00000100;
-       nv_subdev(fifo)->intr = nv04_fifo_intr;
-       fifo->base.pause = nv04_fifo_pause;
-       fifo->base.start = nv04_fifo_start;
-       fifo->ramfc_desc = nv17_ramfc;
-       return 0;
+       return nv04_fifo_new_(&nv17_fifo, device, index, 32,
+                             nv17_fifo_ramfc, pfifo);
 }
-
-struct nvkm_oclass *
-nv17_fifo_oclass = &(struct nvkm_oclass) {
-       .handle = NV_ENGINE(FIFO, 0x17),
-       .ofuncs = &(struct nvkm_ofuncs) {
-               .ctor = nv17_fifo_ctor,
-               .dtor = nv04_fifo_dtor,
-               .init = nv17_fifo_init,
-               .fini = _nvkm_fifo_fini,
-       },
-};
index aca146377d36de4898adf3efabfefd268bd0299d..8c7ba32763c42e702d8e9d753851dd37b087755a 100644 (file)
@@ -29,8 +29,8 @@
 #include <subdev/fb.h>
 #include <subdev/instmem.h>
 
-static struct ramfc_desc
-nv40_ramfc[] = {
+static const struct nv04_fifo_ramfc
+nv40_fifo_ramfc[] = {
        { 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
        { 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
        { 32,  0, 0x08,  0, NV10_PFIFO_CACHE1_REF_CNT },
@@ -56,21 +56,16 @@ nv40_ramfc[] = {
        {}
 };
 
-static int
-nv40_fifo_init(struct nvkm_object *object)
+static void
+nv40_fifo_init(struct nvkm_fifo *base)
 {
-       struct nv04_fifo *fifo = (void *)object;
+       struct nv04_fifo *fifo = nv04_fifo(base);
        struct nvkm_device *device = fifo->base.engine.subdev.device;
        struct nvkm_fb *fb = device->fb;
        struct nvkm_instmem *imem = device->imem;
        struct nvkm_ramht *ramht = imem->ramht;
        struct nvkm_memory *ramro = imem->ramro;
        struct nvkm_memory *ramfc = imem->ramfc;
-       int ret;
-
-       ret = nvkm_fifo_init(&fifo->base);
-       if (ret)
-               return ret;
 
        nvkm_wr32(device, 0x002040, 0x000000ff);
        nvkm_wr32(device, 0x002044, 0x2101ffff);
@@ -81,7 +76,7 @@ nv40_fifo_init(struct nvkm_object *object)
                                            (ramht->gpuobj->addr >> 8));
        nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8);
 
-       switch (nv_device(fifo)->chipset) {
+       switch (device->chipset) {
        case 0x47:
        case 0x49:
        case 0x4b:
@@ -110,47 +105,23 @@ nv40_fifo_init(struct nvkm_object *object)
        nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);
        nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
        nvkm_wr32(device, NV03_PFIFO_CACHES, 1);
-       return 0;
 }
 
 static const struct nvkm_fifo_func
-nv40_fifo_func = {
+nv40_fifo = {
+       .init = nv40_fifo_init,
+       .intr = nv04_fifo_intr,
+       .pause = nv04_fifo_pause,
+       .start = nv04_fifo_start,
        .chan = {
                &nv40_fifo_dma_oclass,
                NULL
        },
 };
 
-static int
-nv40_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
-              struct nvkm_oclass *oclass, void *data, u32 size,
-              struct nvkm_object **pobject)
+int
+nv40_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
 {
-       struct nv04_fifo *fifo;
-       int ret;
-
-       ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &fifo);
-       *pobject = nv_object(fifo);
-       if (ret)
-               return ret;
-
-       fifo->base.func = &nv40_fifo_func;
-
-       nv_subdev(fifo)->unit = 0x00000100;
-       nv_subdev(fifo)->intr = nv04_fifo_intr;
-       fifo->base.pause = nv04_fifo_pause;
-       fifo->base.start = nv04_fifo_start;
-       fifo->ramfc_desc = nv40_ramfc;
-       return 0;
+       return nv04_fifo_new_(&nv40_fifo, device, index, 32,
+                             nv40_fifo_ramfc, pfifo);
 }
-
-struct nvkm_oclass *
-nv40_fifo_oclass = &(struct nvkm_oclass) {
-       .handle = NV_ENGINE(FIFO, 0x40),
-       .ofuncs = &(struct nvkm_ofuncs) {
-               .ctor = nv40_fifo_ctor,
-               .dtor = nv04_fifo_dtor,
-               .init = nv40_fifo_init,
-               .fini = _nvkm_fifo_fini,
-       },
-};
index ad653e9c461a39a0b1c71f05af3ca020d21dc764..66eb12c2b5ba75f959ffc7d49c485edd121d2375 100644 (file)
@@ -24,6 +24,8 @@
 #include "nv50.h"
 #include "channv50.h"
 
+#include <core/gpuobj.h>
+
 static void
 nv50_fifo_runlist_update_locked(struct nv50_fifo *fifo)
 {
@@ -49,22 +51,34 @@ nv50_fifo_runlist_update_locked(struct nv50_fifo *fifo)
 void
 nv50_fifo_runlist_update(struct nv50_fifo *fifo)
 {
-       mutex_lock(&nv_subdev(fifo)->mutex);
+       mutex_lock(&fifo->base.engine.subdev.mutex);
        nv50_fifo_runlist_update_locked(fifo);
-       mutex_unlock(&nv_subdev(fifo)->mutex);
+       mutex_unlock(&fifo->base.engine.subdev.mutex);
 }
 
 int
-nv50_fifo_init(struct nvkm_object *object)
+nv50_fifo_oneinit(struct nvkm_fifo *base)
 {
-       struct nv50_fifo *fifo = (void *)object;
+       struct nv50_fifo *fifo = nv50_fifo(base);
        struct nvkm_device *device = fifo->base.engine.subdev.device;
-       int ret, i;
+       int ret;
 
-       ret = nvkm_fifo_init(&fifo->base);
+       ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000,
+                             false, &fifo->runlist[0]);
        if (ret)
                return ret;
 
+       return nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000,
+                              false, &fifo->runlist[1]);
+}
+
+void
+nv50_fifo_init(struct nvkm_fifo *base)
+{
+       struct nv50_fifo *fifo = nv50_fifo(base);
+       struct nvkm_device *device = fifo->base.engine.subdev.device;
+       int i;
+
        nvkm_mask(device, 0x000200, 0x00000100, 0x00000000);
        nvkm_mask(device, 0x000200, 0x00000100, 0x00000100);
        nvkm_wr32(device, 0x00250c, 0x6f3cfc34);
@@ -80,69 +94,54 @@ nv50_fifo_init(struct nvkm_object *object)
        nvkm_wr32(device, 0x003200, 0x00000001);
        nvkm_wr32(device, 0x003250, 0x00000001);
        nvkm_wr32(device, 0x002500, 0x00000001);
-       return 0;
 }
 
-void
-nv50_fifo_dtor(struct nvkm_object *object)
+void *
+nv50_fifo_dtor(struct nvkm_fifo *base)
 {
-       struct nv50_fifo *fifo = (void *)object;
-
+       struct nv50_fifo *fifo = nv50_fifo(base);
        nvkm_memory_del(&fifo->runlist[1]);
        nvkm_memory_del(&fifo->runlist[0]);
-
-       nvkm_fifo_destroy(&fifo->base);
+       return fifo;
 }
 
-static const struct nvkm_fifo_func
-nv50_fifo_func = {
-       .chan = {
-               &nv50_fifo_dma_oclass,
-               &nv50_fifo_gpfifo_oclass,
-               NULL
-       },
-};
-
-static int
-nv50_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
-              struct nvkm_oclass *oclass, void *data, u32 size,
-              struct nvkm_object **pobject)
+int
+nv50_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device,
+              int index, struct nvkm_fifo **pfifo)
 {
-       struct nvkm_device *device = (void *)parent;
        struct nv50_fifo *fifo;
        int ret;
 
-       ret = nvkm_fifo_create(parent, engine, oclass, 1, 127, &fifo);
-       *pobject = nv_object(fifo);
-       if (ret)
-               return ret;
-
-       fifo->base.func = &nv50_fifo_func;
-
-       ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000,
-                             false, &fifo->runlist[0]);
-       if (ret)
-               return ret;
+       if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL)))
+               return -ENOMEM;
+       *pfifo = &fifo->base;
 
-       ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000,
-                             false, &fifo->runlist[1]);
+       ret = nvkm_fifo_ctor(func, device, index, 128, &fifo->base);
        if (ret)
                return ret;
 
-       nv_subdev(fifo)->unit = 0x00000100;
-       nv_subdev(fifo)->intr = nv04_fifo_intr;
-       fifo->base.pause = nv04_fifo_pause;
-       fifo->base.start = nv04_fifo_start;
+       set_bit(0, fifo->base.mask); /* PIO channel */
+       set_bit(127, fifo->base.mask); /* inactive channel */
        return 0;
 }
 
-struct nvkm_oclass *
-nv50_fifo_oclass = &(struct nvkm_oclass) {
-       .handle = NV_ENGINE(FIFO, 0x50),
-       .ofuncs = &(struct nvkm_ofuncs) {
-               .ctor = nv50_fifo_ctor,
-               .dtor = nv50_fifo_dtor,
-               .init = nv50_fifo_init,
-               .fini = _nvkm_fifo_fini,
+static const struct nvkm_fifo_func
+nv50_fifo = {
+       .dtor = nv50_fifo_dtor,
+       .oneinit = nv50_fifo_oneinit,
+       .init = nv50_fifo_init,
+       .intr = nv04_fifo_intr,
+       .pause = nv04_fifo_pause,
+       .start = nv04_fifo_start,
+       .chan = {
+               &nv50_fifo_dma_oclass,
+               &nv50_fifo_gpfifo_oclass,
+               NULL
        },
 };
+
+int
+nv50_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
+{
+       return nv50_fifo_new_(&nv50_fifo, device, index, pfifo);
+}
index a7d5dba12fb8e302ddd24bc1948711b0be843434..8ab53948cbb405bd5bc82adbe9fa7b4b5de570dc 100644 (file)
@@ -9,7 +9,11 @@ struct nv50_fifo {
        int cur_runlist;
 };
 
-void nv50_fifo_dtor(struct nvkm_object *);
-int  nv50_fifo_init(struct nvkm_object *);
+int nv50_fifo_new_(const struct nvkm_fifo_func *, struct nvkm_device *,
+                  int index, struct nvkm_fifo **);
+
+void *nv50_fifo_dtor(struct nvkm_fifo *);
+int nv50_fifo_oneinit(struct nvkm_fifo *);
+void nv50_fifo_init(struct nvkm_fifo *);
 void nv50_fifo_runlist_update(struct nv50_fifo *);
 #endif
index a30d160f30db637b02575d42721775b363cff8ae..cb1432e9be08ca6bbb618bccf584759a10b1bb1c 100644 (file)
@@ -1,7 +1,26 @@
 #ifndef __NVKM_FIFO_PRIV_H__
 #define __NVKM_FIFO_PRIV_H__
+#define nvkm_fifo(p) container_of((p), struct nvkm_fifo, engine)
 #include <engine/fifo.h>
 
+int nvkm_fifo_ctor(const struct nvkm_fifo_func *, struct nvkm_device *,
+                  int index, int nr, struct nvkm_fifo *);
+void nvkm_fifo_uevent(struct nvkm_fifo *);
+
+struct nvkm_fifo_func {
+       void *(*dtor)(struct nvkm_fifo *);
+       int (*oneinit)(struct nvkm_fifo *);
+       void (*init)(struct nvkm_fifo *);
+       void (*fini)(struct nvkm_fifo *);
+       void (*intr)(struct nvkm_fifo *);
+       void (*pause)(struct nvkm_fifo *, unsigned long *);
+       void (*start)(struct nvkm_fifo *, unsigned long *);
+       void (*uevent_init)(struct nvkm_fifo *);
+       void (*uevent_fini)(struct nvkm_fifo *);
+       const struct nvkm_fifo_chan_oclass *chan[];
+};
+
+void nv04_fifo_intr(struct nvkm_fifo *);
 void nv04_fifo_pause(struct nvkm_fifo *, unsigned long *);
 void nv04_fifo_start(struct nvkm_fifo *, unsigned long *);
 #endif
index f06c16f61a9812b7562ca6f8ddaaebe0c4d8f9b8..a5a4bdd9863e7a0c48694e4c801175887053b673 100644 (file)
@@ -25,6 +25,7 @@
 #include "regs.h"
 
 #include <core/client.h>
+#include <core/gpuobj.h>
 #include <engine/fifo.h>
 #include <engine/fifo/chan.h>
 #include <subdev/instmem.h>
index 98fb9e6efb9755535c42ed1d9b58571352daa90c..d5e44a7332ebb79caaca04e81d0d8f978fc831b6 100644 (file)
@@ -25,6 +25,7 @@
 #include "regs.h"
 
 #include <core/client.h>
+#include <core/gpuobj.h>
 #include <engine/fifo.h>
 #include <engine/fifo/chan.h>
 #include <subdev/fb.h>
@@ -1055,14 +1056,14 @@ nv10_gr_tile_prog(struct nvkm_engine *engine, int i)
        struct nvkm_fb_tile *tile = &device->fb->tile.region[i];
        unsigned long flags;
 
-       fifo->pause(fifo, &flags);
+       nvkm_fifo_pause(fifo, &flags);
        nv04_gr_idle(&gr->base);
 
        nvkm_wr32(device, NV10_PGRAPH_TLIMIT(i), tile->limit);
        nvkm_wr32(device, NV10_PGRAPH_TSIZE(i), tile->pitch);
        nvkm_wr32(device, NV10_PGRAPH_TILE(i), tile->addr);
 
-       fifo->start(fifo, &flags);
+       nvkm_fifo_start(fifo, &flags);
 }
 
 const struct nvkm_bitfield nv10_gr_intr_name[] = {
index 554f2e3f7e5b72c96972f71826fe44ddc95cf275..ce4f9925ea9b8c110e95400d9427f3ac74f84ade 100644 (file)
@@ -2,6 +2,7 @@
 #include "regs.h"
 
 #include <core/client.h>
+#include <core/gpuobj.h>
 #include <engine/fifo.h>
 #include <engine/fifo/chan.h>
 #include <subdev/fb.h>
@@ -152,7 +153,7 @@ nv20_gr_tile_prog(struct nvkm_engine *engine, int i)
        struct nvkm_fb_tile *tile = &device->fb->tile.region[i];
        unsigned long flags;
 
-       fifo->pause(fifo, &flags);
+       nvkm_fifo_pause(fifo, &flags);
        nv04_gr_idle(&gr->base);
 
        nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
@@ -172,7 +173,7 @@ nv20_gr_tile_prog(struct nvkm_engine *engine, int i)
                nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp);
        }
 
-       fifo->start(fifo, &flags);
+       nvkm_fifo_start(fifo, &flags);
 }
 
 void
index 7fb53d53426cd1f38d27b55ce23ae6b9e3259fe8..cc56ca9505f4a60f2d66637fc9e6a82056c7e9fe 100644 (file)
@@ -1,6 +1,7 @@
 #include "nv20.h"
 #include "regs.h"
 
+#include <core/gpuobj.h>
 #include <engine/fifo.h>
 #include <engine/fifo/chan.h>
 
index 2fabdc58665176de8d12cff1764a8cd59848f857..4e4cd93d686d3fc0ba0d8cf48b8c465bfdcaa5cc 100644 (file)
@@ -1,6 +1,7 @@
 #include "nv20.h"
 #include "regs.h"
 
+#include <core/gpuobj.h>
 #include <engine/fifo.h>
 #include <engine/fifo/chan.h>
 
index 8f5bfe3aa487d39862193f3e560478b7d348b79d..ea46b16c31e69c8811eb5b8852b6933cfccf92d8 100644 (file)
@@ -1,6 +1,7 @@
 #include "nv20.h"
 #include "regs.h"
 
+#include <core/gpuobj.h>
 #include <engine/fifo.h>
 #include <engine/fifo/chan.h>
 #include <subdev/fb.h>
index 3781a5b311fbcdc28e7a4acd63b483c723936464..0667e9d14b42ffdff96b40c167eaf44089bf6611 100644 (file)
@@ -1,6 +1,7 @@
 #include "nv20.h"
 #include "regs.h"
 
+#include <core/gpuobj.h>
 #include <engine/fifo.h>
 #include <engine/fifo/chan.h>
 
index 285c4eff2e5bcb58e02fde3c51e2acbd49bf6738..745d0e133d9a0c199786fa78799a153c0031fcbb 100644 (file)
@@ -1,6 +1,7 @@
 #include "nv20.h"
 #include "regs.h"
 
+#include <core/gpuobj.h>
 #include <engine/fifo.h>
 #include <engine/fifo/chan.h>
 
index 0e4e1152eeeca8da52c5a43f9d85f529e38f6f4b..be954500b4d8dfb21b68dd385281d92a31580b9b 100644 (file)
@@ -25,6 +25,7 @@
 #include "regs.h"
 
 #include <core/client.h>
+#include <core/gpuobj.h>
 #include <subdev/fb.h>
 #include <subdev/timer.h>
 #include <engine/fifo.h>
@@ -176,7 +177,7 @@ nv40_gr_tile_prog(struct nvkm_engine *engine, int i)
        struct nvkm_fb_tile *tile = &device->fb->tile.region[i];
        unsigned long flags;
 
-       fifo->pause(fifo, &flags);
+       nvkm_fifo_pause(fifo, &flags);
        nv04_gr_idle(&gr->base);
 
        switch (nv_device(gr)->chipset) {
@@ -243,7 +244,7 @@ nv40_gr_tile_prog(struct nvkm_engine *engine, int i)
                break;
        }
 
-       fifo->start(fifo, &flags);
+       nvkm_fifo_start(fifo, &flags);
 }
 
 static void
index 2a5bc9270fb9c3b4e9d4dc090dbcde46d9423787..11c4c88389378636b7d7d128d443ce61794c8ff9 100644 (file)
@@ -24,6 +24,7 @@
 #include "nv50.h"
 
 #include <core/client.h>
+#include <core/gpuobj.h>
 #include <subdev/timer.h>
 #include <engine/fifo.h>
 
index 417cc31a12ef78122a65361c1e79b8006399cfa6..f79749946b72cd9c71e2409fee2aa16fc3648b97 100644 (file)
@@ -24,6 +24,7 @@
 #include "nv31.h"
 
 #include <core/client.h>
+#include <core/gpuobj.h>
 #include <subdev/fb.h>
 #include <subdev/timer.h>
 #include <engine/fifo.h>
index 0f9ef18bf18d0955ffc1d9aa165ea8b6579d85e8..d1b914b43cee4c00e662eb752c2abbae21543dba 100644 (file)
@@ -25,6 +25,7 @@
 #include "priv.h"
 
 #include <core/client.h>
+#include <core/gpuobj.h>
 #include <engine/fifo.h>
 
 #include <nvif/class.h>
index 1ec4f4fde1c2daac2801a02f744e584c45883946..995c2c5ec15038f815640f00d52b7fdecc26c63a 100644 (file)
@@ -27,6 +27,7 @@
 
 #include <core/client.h>
 #include <core/enum.h>
+#include <core/gpuobj.h>
 
 #include <nvif/class.h>
 
index 4ca6b88e9a7f3917a593ac80cf0eef350ff0bca3..5cd7844f1d5fa49acdb25ff097fe95653a0a9e73 100644 (file)
@@ -23,6 +23,7 @@
  */
 #include "nv50.h"
 
+#include <core/gpuobj.h>
 #include <subdev/bar.h>
 #include <engine/disp.h>
 #include <engine/fifo.h>
index 6c93a20295a43c2cc51ac9aff86261f9194ebb8a..a00d9a55e53b8686b433aea4e9063d24a6d705af 100644 (file)
@@ -23,6 +23,7 @@
  */
 #include "nv50.h"
 
+#include <core/gpuobj.h>
 #include <core/handle.h>
 #include <engine/disp.h>
 #include <engine/fifo/chan.h>
index fa36233a71ddfdc3a40ff374329ab4faba8fbd89..d6a2b9593538c8ca2eb434aee51a4640f23dc2ac 100644 (file)
@@ -20,6 +20,8 @@
  * OTHER DEALINGS IN THE SOFTWARE.
  */
 #include <engine/xtensa.h>
+
+#include <core/gpuobj.h>
 #include <engine/fifo.h>
 
 static int
index e5258ba19834eceb2b69fa59fb6714cf9eddee74..07feae620c8d9f301e103a030d5ffb23c8e2120a 100644 (file)
@@ -317,7 +317,7 @@ gt215_clk_pre(struct nvkm_clk *clk, unsigned long *flags)
                return -EBUSY;
 
        if (fifo)
-               fifo->pause(fifo, flags);
+               nvkm_fifo_pause(fifo, flags);
 
        if (nvkm_msec(device, 2000,
                if (nvkm_rd32(device, 0x002504) & 0x00000010)
@@ -342,7 +342,7 @@ gt215_clk_post(struct nvkm_clk *clk, unsigned long *flags)
        struct nvkm_fifo *fifo = device->fifo;
 
        if (fifo && flags)
-               fifo->start(fifo, flags);
+               nvkm_fifo_start(fifo, flags);
 
        nvkm_mask(device, 0x002504, 0x00000001, 0x00000000);
        nvkm_mask(device, 0x020060, 0x00070000, 0x00040000);