drm/i915/chv: Freq(opcode) request for CHV.

On CHV, All the freq request should be even. So, we need to make sure we
request the opcode accordingly.

v2: Avoid vairable for freq request (ville)

Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index cf288a95347c02c81d195e86f9e8bd8469660314..218ef085cf7339f24197b73024901fa3e109e351 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1252,8 +1252,10 @@ static void gen6_pm_rps_work(struct work_struct *work)
        if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
                if (adj > 0)
                        adj *= 2;
-               else
-                       adj = 1;
+               else {
+                       /* CHV needs even encode values */
+                       adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1;
+               }
                new_delay = dev_priv->rps.cur_freq + adj;
 
                /*
@@ -1271,8 +1273,10 @@ static void gen6_pm_rps_work(struct work_struct *work)
        } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
                if (adj < 0)
                        adj *= 2;
-               else
-                       adj = -1;
+               else {
+                       /* CHV needs even encode values */
+                       adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1;
+               }
                new_delay = dev_priv->rps.cur_freq + adj;
        } else { /* unknown event */
                new_delay = dev_priv->rps.cur_freq;