#define MWAIT_SUBSTATE_MASK 0xf
#define MWAIT_CSTATE_MASK 0xf
#define MWAIT_SUBSTATE_SIZE 4
-#define MWAIT_MAX_NUM_CSTATES 8
#define CPUID_MWAIT_LEAF 5
#define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1
.en_core_tk_irqen = 1,
};
/* intel_idle.max_cstate=0 disables driver */
-static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;
+static int max_cstate = CPUIDLE_STATE_MAX - 1;
static unsigned int mwait_substates;
* which is also the index into the MWAIT hint array.
* Thus C0 is a dummy.
*/
-static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
+static struct cpuidle_state nehalem_cstates[CPUIDLE_STATE_MAX] = {
{ /* MWAIT C0 */ },
{ /* MWAIT C1 */
.name = "C1-NHM",
.enter = &intel_idle },
};
-static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
+static struct cpuidle_state snb_cstates[CPUIDLE_STATE_MAX] = {
{ /* MWAIT C0 */ },
{ /* MWAIT C1 */
.name = "C1-SNB",
.enter = &intel_idle },
};
-static struct cpuidle_state ivb_cstates[MWAIT_MAX_NUM_CSTATES] = {
+static struct cpuidle_state ivb_cstates[CPUIDLE_STATE_MAX] = {
{ /* MWAIT C0 */ },
{ /* MWAIT C1 */
.name = "C1-IVB",
.enter = &intel_idle },
};
-static struct cpuidle_state hsw_cstates[MWAIT_MAX_NUM_CSTATES] = {
+static struct cpuidle_state hsw_cstates[CPUIDLE_STATE_MAX] = {
{ /* MWAIT C0 */ },
{ /* MWAIT C1 */
.name = "C1-HSW",
.enter = &intel_idle },
};
-static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
+static struct cpuidle_state atom_cstates[CPUIDLE_STATE_MAX] = {
{ /* MWAIT C0 */ },
{ /* MWAIT C1 */
.name = "C1-ATM",
drv->state_count = 1;
- for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
+ for (cstate = 1; cstate < CPUIDLE_STATE_MAX; ++cstate) {
int num_substates;
if (cstate > max_cstate) {
dev->state_count = 1;
- for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
+ for (cstate = 1; cstate < CPUIDLE_STATE_MAX; ++cstate) {
int num_substates;
if (cstate > max_cstate) {