int ret;
for (i = 0; i < map->num_reg_defaults; i++) {
- ret = regmap_write(map, map->reg_defaults[i].reg,
- map->reg_defaults[i].def);
+ ret = _regmap_write(map, map->reg_defaults[i].reg,
+ map->reg_defaults[i].def);
if (ret < 0)
return ret;
dev_dbg(map->dev, "Synced register %#x, value %#x\n",
if (ret)
return ret;
map->cache_bypass = 1;
- ret = regmap_write(map, i, val);
+ ret = _regmap_write(map, i, val);
map->cache_bypass = 0;
if (ret)
return ret;
if (val == def)
continue;
map->cache_bypass = 1;
- ret = regmap_write(map, regtmp, val);
+ ret = _regmap_write(map, regtmp, val);
map->cache_bypass = 0;
if (ret)
return ret;
BUG_ON(!map->cache_ops);
+ mutex_lock(&map->lock);
dev_dbg(map->dev, "Syncing %s cache\n",
map->cache_ops->name);
name = map->cache_ops->name;
if (ret < 0)
goto out;
map->cache_bypass = 1;
- ret = regmap_write(map, i, val);
+ ret = _regmap_write(map, i, val);
map->cache_bypass = 0;
if (ret < 0)
goto out;
}
out:
trace_regcache_sync(map->dev, name, "stop");
+ mutex_unlock(&map->lock);
return ret;
}