clk: meson: remove CLK_SET_RATE_PARENT for spicc

PD#164751: clk: meson: remove CLK_SET_RATE_PARENT for spicc

If add CLK_SET_RATE_PARENT, set rate for spicc clock will
change clk81 rate.

Change-Id: If653169e26363e8015ae0547e899a9ea2b362a48
Signed-off-by: Jian Hu <jian.hu@amlogic.com>

diff --git a/drivers/amlogic/clk/axg/axg.c b/drivers/amlogic/clk/axg/axg.c
index d267eb63ee6ba60f2ce2eae0fe3668762c2925b8..0afb4ceb32a6bcd90dc7d01510ab8f24dc25c164 100644 (file)
--- a/drivers/amlogic/clk/axg/axg.c
+++ b/drivers/amlogic/clk/axg/axg.c
@@ -619,6 +619,31 @@ static struct clk_gate axg_clk81 = {
        },
 };
 
+static struct clk_gate axg_spicc_0 = {
+       .reg = (void *)HHI_GCLK_MPEG0,
+       .bit_idx = 8,
+       .lock = &clk_lock,
+       .hw.init = &(struct clk_init_data){
+               .name = "axg_spicc_0",
+               .ops = &clk_gate_ops,
+               .parent_names = (const char *[]){ "clk81" },
+               .num_parents = 1,
+               .flags = 0,
+       },
+};
+
+static struct clk_gate axg_spicc_1 = {
+       .reg = (void *)HHI_GCLK_MPEG0,
+       .bit_idx = 15,
+       .lock = &clk_lock,
+       .hw.init = &(struct clk_init_data){
+               .name = "axg_spicc_1",
+               .ops = &clk_gate_ops,
+               .parent_names = (const char *[]){ "clk81" },
+               .num_parents = 1,
+               .flags = 0,
+       },
+};
 /* Everything Else (EE) domain gates */
 static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
 static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
@@ -626,12 +651,12 @@ static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
 static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5);
 static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6);
 static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7);
-static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8);
+//static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8);
 static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9);
 static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12);
 static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13);
 static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14);
-static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15);
+//static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15);
 static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16);
 static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17);
 static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19);

diff --git a/drivers/amlogic/clk/g12a/g12a.c b/drivers/amlogic/clk/g12a/g12a.c
index e2c7afd9caf9caf35ab0392cfa27fb4d34220b82..ab3a65d4c4539c6a97e17e9363b760eb996e634d 100644 (file)
--- a/drivers/amlogic/clk/g12a/g12a.c
+++ b/drivers/amlogic/clk/g12a/g12a.c
@@ -562,6 +562,31 @@ static struct clk_gate g12a_12m_gate = {
 
 
 /* Everything Else (EE) domain gates */
+static struct clk_gate g12a_spicc_0 = {
+       .reg = (void *)HHI_GCLK_MPEG0,
+       .bit_idx = 8,
+       .lock = &clk_lock,
+       .hw.init = &(struct clk_init_data){
+               .name = "g12a_spicc_0",
+               .ops = &clk_gate_ops,
+               .parent_names = (const char *[]){ "clk81" },
+               .num_parents = 1,
+               .flags = 0,
+       },
+};
+
+static struct clk_gate g12a_spicc_1 = {
+       .reg = (void *)HHI_GCLK_MPEG0,
+       .bit_idx = 14,
+       .lock = &clk_lock,
+       .hw.init = &(struct clk_init_data){
+               .name = "g12a_spicc_1",
+               .ops = &clk_gate_ops,
+               .parent_names = (const char *[]){ "clk81" },
+               .num_parents = 1,
+               .flags = 0,
+       },
+};
 static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0);
 static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1);
 static MESON_GATE(g12a_alocker, HHI_GCLK_MPEG0, 2);
@@ -570,13 +595,13 @@ static MESON_GATE(g12a_eth_phy, HHI_GCLK_MPEG0, 4);
 static MESON_GATE(g12a_isa, HHI_GCLK_MPEG0, 5);
 static MESON_GATE(g12a_pl301, HHI_GCLK_MPEG0, 6);
 static MESON_GATE(g12a_periphs, HHI_GCLK_MPEG0, 7);
-static MESON_GATE(g12a_spicc_0, HHI_GCLK_MPEG0, 8);
+//static MESON_GATE(g12a_spicc_0, HHI_GCLK_MPEG0, 8);
 static MESON_GATE(g12a_i2c, HHI_GCLK_MPEG0, 9);
 static MESON_GATE(g12a_sana, HHI_GCLK_MPEG0, 10);
 static MESON_GATE(g12a_sd, HHI_GCLK_MPEG0, 11);
 static MESON_GATE(g12a_rng0, HHI_GCLK_MPEG0, 12);
 static MESON_GATE(g12a_uart0, HHI_GCLK_MPEG0, 13);
-static MESON_GATE(g12a_spicc_1, HHI_GCLK_MPEG0, 14);
+//static MESON_GATE(g12a_spicc_1, HHI_GCLK_MPEG0, 14);
 static MESON_GATE(g12a_hiu_reg, HHI_GCLK_MPEG0, 19);
 static MESON_GATE(g12a_mipi_dsi_phy, HHI_GCLK_MPEG0, 20);
 static MESON_GATE(g12a_assist_misc, HHI_GCLK_MPEG0, 23);

diff --git a/drivers/amlogic/clk/gxl/gxl.c b/drivers/amlogic/clk/gxl/gxl.c
index 8831de5cc14e01769ee736b2bdd58b0717153514..3545db67c06aa416977838d210dfde1b74a4b32d 100644 (file)
--- a/drivers/amlogic/clk/gxl/gxl.c
+++ b/drivers/amlogic/clk/gxl/gxl.c
@@ -686,13 +686,26 @@ static struct clk_gate gxl_clk81 = {
        },
 };
 
+static struct clk_gate gxl_spicc = {
+       .reg = (void *)HHI_GCLK_MPEG0,
+       .bit_idx = 8,
+       .lock = &clk_lock,
+       .hw.init = &(struct clk_init_data){
+               .name = "gxl_spicc",
+               .ops = &clk_gate_ops,
+               .parent_names = (const char *[]){ "clk81" },
+               .num_parents = 1,
+               .flags = 0,
+       },
+};
+
 /* Everything Else (EE) domain gates */
 static MESON_GATE(gxl_ddr, HHI_GCLK_MPEG0, 0);
 static MESON_GATE(gxl_dos, HHI_GCLK_MPEG0, 1);
 static MESON_GATE(gxl_isa, HHI_GCLK_MPEG0, 5);
 static MESON_GATE(gxl_pl301, HHI_GCLK_MPEG0, 6);
 static MESON_GATE(gxl_periphs, HHI_GCLK_MPEG0, 7);
-static MESON_GATE(gxl_spicc, HHI_GCLK_MPEG0, 8);
+//static MESON_GATE(gxl_spicc, HHI_GCLK_MPEG0, 8);
 static MESON_GATE(gxl_i2c, HHI_GCLK_MPEG0, 9);
 static MESON_GATE(gxl_sana, HHI_GCLK_MPEG0, 10);
 static MESON_GATE(gxl_smart_card, HHI_GCLK_MPEG0, 11);

diff --git a/drivers/amlogic/clk/m8b/meson8b.c b/drivers/amlogic/clk/m8b/meson8b.c
index a93043881bb3958ac32a2dfcec96ab411681d222..2c3c74e58c78795696d690f84d657db26cd55d4c 100644 (file)
--- a/drivers/amlogic/clk/m8b/meson8b.c
+++ b/drivers/amlogic/clk/m8b/meson8b.c
@@ -404,6 +404,19 @@ struct clk_gate meson8b_clk81 = {
        },
 };
 
+static struct clk_gate meson8b_spicc = {
+       .reg = (void *)HHI_GCLK_MPEG0,
+       .bit_idx = 8,
+       .lock = &clk_lock,
+       .hw.init = &(struct clk_init_data){
+               .name = "meson8b_spicc",
+               .ops = &clk_gate_ops,
+               .parent_names = (const char *[]){ "clk81" },
+               .num_parents = 1,
+               .flags = 0,
+       },
+};
+
 /* Everything Else (EE) domain gates */
 
 static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
@@ -411,7 +424,7 @@ static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1);
 static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5);
 static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6);
 static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7);
-static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8);
+//static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8);
 static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9);
 static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10);
 static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11);

diff --git a/drivers/amlogic/clk/txlx/txlx.c b/drivers/amlogic/clk/txlx/txlx.c
index 227ec77c465498051e5f68736f5227f87332245c..dd9fd01f903a285ddc12bf98108036d225a17b88 100644 (file)
--- a/drivers/amlogic/clk/txlx/txlx.c
+++ b/drivers/amlogic/clk/txlx/txlx.c
@@ -541,13 +541,13 @@ static MESON_GATE(txlx_audio_locker, HHI_GCLK_MPEG0, 2);
 static MESON_GATE(txlx_isa, HHI_GCLK_MPEG0, 5);
 static MESON_GATE(txlx_pl301, HHI_GCLK_MPEG0, 6);
 static MESON_GATE(txlx_periphs, HHI_GCLK_MPEG0, 7);
-static MESON_GATE(txlx_spicc_0, HHI_GCLK_MPEG0, 8);
+//static MESON_GATE(txlx_spicc_0, HHI_GCLK_MPEG0, 8);
 static MESON_GATE(txlx_i2c, HHI_GCLK_MPEG0, 9);
 static MESON_GATE(txlx_sana, HHI_GCLK_MPEG0, 10);
 static MESON_GATE(txlx_smart_card, HHI_GCLK_MPEG0, 11);
 static MESON_GATE(txlx_rng0, HHI_GCLK_MPEG0, 12);
 static MESON_GATE(txlx_uart0, HHI_GCLK_MPEG0, 13);
-static MESON_GATE(txlx_spicc_1, HHI_GCLK_MPEG0, 14);
+//static MESON_GATE(txlx_spicc_1, HHI_GCLK_MPEG0, 14);
 static MESON_GATE(txlx_stream, HHI_GCLK_MPEG0, 15);
 static MESON_GATE(txlx_async_fifo, HHI_GCLK_MPEG0, 16);
 static MESON_GATE(txlx_hiu_reg, HHI_GCLK_MPEG0, 19);
@@ -629,6 +629,32 @@ static MESON_GATE(txlx_ao_ahb_bus, HHI_GCLK_AO, 2);
 static MESON_GATE(txlx_ao_iface, HHI_GCLK_AO, 3);
 static MESON_GATE(txlx_ao_i2c, HHI_GCLK_AO, 4);
 
+static struct clk_gate txlx_spicc_0 = {
+       .reg = (void *)HHI_GCLK_MPEG0,
+       .bit_idx = 8,
+       .lock = &clk_lock,
+       .hw.init = &(struct clk_init_data){
+               .name = "txlx_spicc_0",
+               .ops = &clk_gate_ops,
+               .parent_names = (const char *[]){ "clk81" },
+               .num_parents = 1,
+               .flags = 0,
+       },
+};
+
+static struct clk_gate txlx_spicc_1 = {
+       .reg = (void *)HHI_GCLK_MPEG0,
+       .bit_idx = 14,
+       .lock = &clk_lock,
+       .hw.init = &(struct clk_init_data){
+               .name = "txlx_spicc_1",
+               .ops = &clk_gate_ops,
+               .parent_names = (const char *[]){ "clk81" },
+               .num_parents = 1,
+               .flags = 0,
+       },
+};
+
 /* Array of all clocks provided by this provider */
 
 static struct clk_hw *txlx_clk_hws[] = {