};
cvbsout {
- compatible = "amlogic, cvbsout-g12a";
+ compatible = "amlogic, cvbsout-g12b";
dev_name = "cvbsout";
- status = "disabled";
+ status = "okay";
clocks = <&clkc CLKID_VCLK2_ENCI
&clkc CLKID_VCLK2_VENCI0
&clkc CLKID_VCLK2_VENCI1
"vdac_clk_gate";
/* performance: reg_address, reg_value */
- /* s905x */
+ /* g12b */
performance = <0x1bf0 0x9
- 0x1b56 0x343
+ 0x1b56 0x333
0x1b12 0x8080
0x1b05 0xfd
- 0x1c59 0xf752
+ 0x1c59 0xf850
+ 0xffff 0x0>; /* ending flag */
+ performance_sarft = <0x1bf0 0x9
+ 0x1b56 0x333
+ 0x1b12 0x0
+ 0x1b05 0x9
+ 0x1c59 0xfc48
0xffff 0x0>; /* ending flag */
};
};
cvbsout {
- compatible = "amlogic, cvbsout-g12a";
+ compatible = "amlogic, cvbsout-g12b";
dev_name = "cvbsout";
- status = "disabled";
+ status = "okay";
clocks = <&clkc CLKID_VCLK2_ENCI
&clkc CLKID_VCLK2_VENCI0
&clkc CLKID_VCLK2_VENCI1
"vdac_clk_gate";
/* performance: reg_address, reg_value */
- /* s905x */
+ /* g12b */
performance = <0x1bf0 0x9
- 0x1b56 0x343
+ 0x1b56 0x333
0x1b12 0x8080
0x1b05 0xfd
- 0x1c59 0xf752
+ 0x1c59 0xf850
+ 0xffff 0x0>; /* ending flag */
+ performance_sarft = <0x1bf0 0x9
+ 0x1b56 0x333
+ 0x1b12 0x0
+ 0x1b05 0x9
+ 0x1c59 0xfc48
0xffff 0x0>; /* ending flag */
};
};
cvbsout {
- compatible = "amlogic, cvbsout-g12a";
+ compatible = "amlogic, cvbsout-g12b";
dev_name = "cvbsout";
- status = "disabled";
+ status = "okay";
clocks = <&clkc CLKID_VCLK2_ENCI
&clkc CLKID_VCLK2_VENCI0
&clkc CLKID_VCLK2_VENCI1
"vdac_clk_gate";
/* performance: reg_address, reg_value */
- /* s905x */
+ /* g12b */
performance = <0x1bf0 0x9
- 0x1b56 0x343
+ 0x1b56 0x333
0x1b12 0x8080
0x1b05 0xfd
- 0x1c59 0xf752
+ 0x1c59 0xf850
+ 0xffff 0x0>; /* ending flag */
+ performance_sarft = <0x1bf0 0x9
+ 0x1b56 0x333
+ 0x1b12 0x0
+ 0x1b05 0x9
+ 0x1c59 0xfc48
0xffff 0x0>; /* ending flag */
};
pr_info("vcbus [0x%x] = 0x%x\n", performance_regs_enci[i],
cvbs_out_reg_read(performance_regs_enci[i]));
}
- if (cvbs_cpu_type() == CVBS_CPU_TYPE_G12A)
+ if (cvbs_cpu_type() == CVBS_CPU_TYPE_G12A ||
+ cvbs_cpu_type() == CVBS_CPU_TYPE_G12B)
size = sizeof(performance_regs_vdac_g12a)/sizeof(unsigned int);
else
size = sizeof(performance_regs_vdac)/sizeof(unsigned int);
pr_info("------------------------\n");
for (i = 0; i < size; i++) {
- if (cvbs_cpu_type() == CVBS_CPU_TYPE_G12A)
+ if (cvbs_cpu_type() == CVBS_CPU_TYPE_G12A ||
+ cvbs_cpu_type() == CVBS_CPU_TYPE_G12B)
pr_info("hiu [0x%x] = 0x%x\n",
performance_regs_vdac_g12a[i],
cvbs_out_hiu_read(performance_regs_vdac_g12a[i]));
cvbs_performance_config_dump();
break;
case CMD_VP_SET_PLLPATH:
- if (cvbs_cpu_type() != CVBS_CPU_TYPE_G12A) {
- print_info("ERR:Only g12a chip supported\n");
+ if (cvbs_cpu_type() != CVBS_CPU_TYPE_G12A &&
+ cvbs_cpu_type() != CVBS_CPU_TYPE_G12B) {
+ print_info("ERR:Only g12a/b chip supported\n");
break;
}
if (argc != 2) {
.name = "meson-g12a-cvbsout",
};
+struct meson_cvbsout_data meson_g12b_cvbsout_data = {
+ .cntl0_val = 0x906001,
+ .cpu_id = CVBS_CPU_TYPE_G12B,
+ .name = "meson-g12b-cvbsout",
+};
+
static const struct of_device_id meson_cvbsout_dt_match[] = {
{
.compatible = "amlogic, cvbsout-gxl",
}, {
.compatible = "amlogic, cvbsout-g12a",
.data = &meson_g12a_cvbsout_data,
+ }, {
+ .compatible = "amlogic, cvbsout-g12b",
+ .data = &meson_g12b_cvbsout_data,
},
{},
};
CVBS_CPU_TYPE_GXM = 2,
CVBS_CPU_TYPE_TXLX = 3,
CVBS_CPU_TYPE_G12A = 4,
+ CVBS_CPU_TYPE_G12B = 5,
};
struct meson_cvbsout_data {
pr_info("[error]: hdmi_pll lock failed\n");
cvbs_out_hiu_setb(HHI_VIID_CLK_CNTL, 0, VCLK2_EN, 1);
udelay(5);
- } else if (cvbs_cpu_type() == CVBS_CPU_TYPE_G12A) {
+ } else if (cvbs_cpu_type() == CVBS_CPU_TYPE_G12A ||
+ cvbs_cpu_type() == CVBS_CPU_TYPE_G12B) {
if (cvbs_clk_path & 0x1) {
pr_info("config g12a gp0_pll\n");
cvbs_out_hiu_write(HHI_GP0_PLL_CNTL0, 0x180204f7);
pr_info("[error]: hdmi_pll lock failed\n");
}
- if (cvbs_cpu_type() == CVBS_CPU_TYPE_G12A) {
+ if (cvbs_cpu_type() == CVBS_CPU_TYPE_G12A ||
+ cvbs_cpu_type() == CVBS_CPU_TYPE_G12B) {
if (cvbs_clk_path & 0x2)
cvbs_set_vid1_clk(cvbs_clk_path & 0x1);
else
void disable_vmode_clk(void)
{
- if (cvbs_cpu_type() == CVBS_CPU_TYPE_G12A) {
+ if (cvbs_cpu_type() == CVBS_CPU_TYPE_G12A ||
+ cvbs_cpu_type() == CVBS_CPU_TYPE_G12B) {
if (cvbs_clk_path & 0x2)
disable_vid1_clk_out();
else
if (is_meson_txlx_cpu())
vdac_hiu_reg_setb(HHI_VDAC_CNTL0, enable, 9, 1);
- else if (is_meson_g12a_cpu())
+ else if (is_meson_g12a_cpu() ||
+ is_meson_g12b_cpu())
vdac_hiu_reg_setb(HHI_VDAC_CNTL0_G12A, ~enable, 9, 1);
else
vdac_hiu_reg_setb(HHI_VDAC_CNTL0, ~enable, 9, 1);
bool enable = 0;
/*bit10 is for bandgap startup setting in g12a*/
- if (is_meson_g12a_cpu())
+ if (is_meson_g12a_cpu() || is_meson_g12b_cpu())
return;
switch (module_sel & 0xf) {
else
enable = 1;
- if (is_meson_g12a_cpu())
+ if (is_meson_g12a_cpu() || is_meson_g12b_cpu())
vdac_hiu_reg_setb(HHI_VDAC_CNTL0_G12A, enable, 0, 1);
else
vdac_hiu_reg_setb(HHI_VDAC_CNTL0, enable, 0, 1);
void vdac_set_ctrl0_ctrl1(unsigned int ctrl0, unsigned int ctrl1)
{
- if (is_meson_g12a_cpu()) {
+ if (is_meson_g12a_cpu() || is_meson_g12b_cpu()) {
vdac_hiu_reg_write(HHI_VDAC_CNTL0_G12A, ctrl0);
vdac_hiu_reg_write(HHI_VDAC_CNTL1_G12A, ctrl1);
} else {
/*Cdac pwd*/
vdac_out_cntl1_bit3(1, VDAC_MODULE_ATV_DEMOD);
/* enable AFE output buffer */
- if (!is_meson_g12a_cpu())
+ if (!is_meson_g12a_cpu() && !is_meson_g12b_cpu())
vdac_hiu_reg_setb(HHI_VDAC_CNTL0, 0, 10, 1);
vdac_out_cntl0_bit0(1, VDAC_MODULE_ATV_DEMOD);
} else {
break;
vdac_out_cntl0_bit0(0, VDAC_MODULE_ATV_DEMOD);
/* Disable AFE output buffer */
- if (!is_meson_g12a_cpu())
+ if (!is_meson_g12a_cpu() && !is_meson_g12b_cpu())
vdac_hiu_reg_setb(HHI_VDAC_CNTL0, 0, 10, 1);
/* enable dac output */
vdac_out_cntl1_bit3(0, 0x4);
pri_flag &= ~VDAC_MODULE_CVBS_OUT;
if (pri_flag & VDAC_MODULE_ATV_DEMOD) {
vdac_out_cntl1_bit3(1, VDAC_MODULE_ATV_DEMOD);
- if (!is_meson_g12a_cpu())
+ if (!is_meson_g12a_cpu() &&
+ !is_meson_g12b_cpu())
vdac_hiu_reg_setb(HHI_VDAC_CNTL0,
0, 10, 1);
vdac_out_cntl0_bit0(1, VDAC_MODULE_ATV_DEMOD);