cvbs: add cvbs support for g12b
authorNian Jing <nian.jing@amlogic.com>
Mon, 28 May 2018 09:15:24 +0000 (17:15 +0800)
committerYixun Lan <yixun.lan@amlogic.com>
Fri, 29 Jun 2018 07:28:48 +0000 (00:28 -0700)
PD#165090: g12b cvbs

Change-Id: I04c26993d96af570a9d3a3bbabd4211d706081b1
Signed-off-by: Nian Jing <nian.jing@amlogic.com>
arch/arm64/boot/dts/amlogic/g12b_a311d_skt.dts
arch/arm64/boot/dts/amlogic/g12b_a311d_w400.dts
arch/arm64/boot/dts/amlogic/g12b_pxp.dts
drivers/amlogic/media/vout/cvbs/cvbs_out.c
drivers/amlogic/media/vout/cvbs/cvbs_out.h
drivers/amlogic/media/vout/cvbs/enc_clk_config.c
drivers/amlogic/media/vout/vdac/vdac_dev.c

index d6f173982bfa34ff3db6e0cdb08504eecd62a061..73f704ba2f2c5f83355bc064b9d8e6866a5adbd5 100644 (file)
        };
 
        cvbsout {
-               compatible = "amlogic, cvbsout-g12a";
+               compatible = "amlogic, cvbsout-g12b";
                dev_name = "cvbsout";
-               status = "disabled";
+               status = "okay";
                clocks = <&clkc CLKID_VCLK2_ENCI
                        &clkc CLKID_VCLK2_VENCI0
                        &clkc CLKID_VCLK2_VENCI1
                        "vdac_clk_gate";
 
                /* performance: reg_address, reg_value */
-               /* s905x */
+               /* g12b */
                performance = <0x1bf0  0x9
-                       0x1b56  0x343
+                       0x1b56  0x333
                        0x1b12  0x8080
                        0x1b05  0xfd
-                       0x1c59  0xf752
+                       0x1c59  0xf850
+                       0xffff  0x0>; /* ending flag */
+               performance_sarft = <0x1bf0  0x9
+                       0x1b56  0x333
+                       0x1b12  0x0
+                       0x1b05  0x9
+                       0x1c59  0xfc48
                        0xffff  0x0>; /* ending flag */
        };
 
index d1d61c9d05df0b3d912628e5fdc333c564a728c5..795ec043b59bf7d8d67a37cbf47f45c3f034359e 100644 (file)
        };
 
        cvbsout {
-               compatible = "amlogic, cvbsout-g12a";
+               compatible = "amlogic, cvbsout-g12b";
                dev_name = "cvbsout";
-               status = "disabled";
+               status = "okay";
                clocks = <&clkc CLKID_VCLK2_ENCI
                        &clkc CLKID_VCLK2_VENCI0
                        &clkc CLKID_VCLK2_VENCI1
                        "vdac_clk_gate";
 
                /* performance: reg_address, reg_value */
-               /* s905x */
+               /* g12b */
                performance = <0x1bf0  0x9
-                       0x1b56  0x343
+                       0x1b56  0x333
                        0x1b12  0x8080
                        0x1b05  0xfd
-                       0x1c59  0xf752
+                       0x1c59  0xf850
+                       0xffff  0x0>; /* ending flag */
+               performance_sarft = <0x1bf0  0x9
+                       0x1b56  0x333
+                       0x1b12  0x0
+                       0x1b05  0x9
+                       0x1c59  0xfc48
                        0xffff  0x0>; /* ending flag */
        };
 
index 08d58500c7e9f5ae855f23f73933cbbb5e287675..b511c302dc7c6c31034e2a816bdb75312936037f 100644 (file)
        };
 
        cvbsout {
-               compatible = "amlogic, cvbsout-g12a";
+               compatible = "amlogic, cvbsout-g12b";
                dev_name = "cvbsout";
-               status = "disabled";
+               status = "okay";
                clocks = <&clkc CLKID_VCLK2_ENCI
                        &clkc CLKID_VCLK2_VENCI0
                        &clkc CLKID_VCLK2_VENCI1
                        "vdac_clk_gate";
 
                /* performance: reg_address, reg_value */
-               /* s905x */
+               /* g12b */
                performance = <0x1bf0  0x9
-                       0x1b56  0x343
+                       0x1b56  0x333
                        0x1b12  0x8080
                        0x1b05  0xfd
-                       0x1c59  0xf752
+                       0x1c59  0xf850
+                       0xffff  0x0>; /* ending flag */
+               performance_sarft = <0x1bf0  0x9
+                       0x1b56  0x333
+                       0x1b12  0x0
+                       0x1b05  0x9
+                       0x1c59  0xfc48
                        0xffff  0x0>; /* ending flag */
        };
 
index 3cc0fe748f395ff2cb8f43d93f66152b5e2b7878..afe13b9e647b87fd9c7cc120a03d92408db0068d 100644 (file)
@@ -818,13 +818,15 @@ static void cvbs_performance_regs_dump(void)
                pr_info("vcbus [0x%x] = 0x%x\n", performance_regs_enci[i],
                        cvbs_out_reg_read(performance_regs_enci[i]));
        }
-       if (cvbs_cpu_type() == CVBS_CPU_TYPE_G12A)
+       if (cvbs_cpu_type() == CVBS_CPU_TYPE_G12A ||
+               cvbs_cpu_type() == CVBS_CPU_TYPE_G12B)
                size = sizeof(performance_regs_vdac_g12a)/sizeof(unsigned int);
        else
                size = sizeof(performance_regs_vdac)/sizeof(unsigned int);
        pr_info("------------------------\n");
        for (i = 0; i < size; i++) {
-               if (cvbs_cpu_type() == CVBS_CPU_TYPE_G12A)
+               if (cvbs_cpu_type() == CVBS_CPU_TYPE_G12A ||
+                       cvbs_cpu_type() == CVBS_CPU_TYPE_G12B)
                        pr_info("hiu [0x%x] = 0x%x\n",
                        performance_regs_vdac_g12a[i],
                        cvbs_out_hiu_read(performance_regs_vdac_g12a[i]));
@@ -1113,8 +1115,9 @@ static void cvbs_debug_store(char *buf)
                cvbs_performance_config_dump();
                break;
        case CMD_VP_SET_PLLPATH:
-               if (cvbs_cpu_type() != CVBS_CPU_TYPE_G12A) {
-                       print_info("ERR:Only g12a chip supported\n");
+               if (cvbs_cpu_type() != CVBS_CPU_TYPE_G12A &&
+                       cvbs_cpu_type() != CVBS_CPU_TYPE_G12B) {
+                       print_info("ERR:Only g12a/b chip supported\n");
                        break;
                }
                if (argc != 2) {
@@ -1331,6 +1334,12 @@ struct meson_cvbsout_data meson_g12a_cvbsout_data = {
        .name = "meson-g12a-cvbsout",
 };
 
+struct meson_cvbsout_data meson_g12b_cvbsout_data = {
+       .cntl0_val = 0x906001,
+       .cpu_id = CVBS_CPU_TYPE_G12B,
+       .name = "meson-g12b-cvbsout",
+};
+
 static const struct of_device_id meson_cvbsout_dt_match[] = {
        {
                .compatible = "amlogic, cvbsout-gxl",
@@ -1344,6 +1353,9 @@ static const struct of_device_id meson_cvbsout_dt_match[] = {
        }, {
                .compatible = "amlogic, cvbsout-g12a",
                .data           = &meson_g12a_cvbsout_data,
+       }, {
+               .compatible = "amlogic, cvbsout-g12b",
+               .data           = &meson_g12b_cvbsout_data,
        },
        {},
 };
index 1d2dfefc289a581644b4ab8b750b52f7d2fed5cc..902f19d2bac5d0e8d139a4624da7db277f6928aa 100644 (file)
@@ -48,6 +48,7 @@ enum cvbs_cpu_type {
        CVBS_CPU_TYPE_GXM    = 2,
        CVBS_CPU_TYPE_TXLX   = 3,
        CVBS_CPU_TYPE_G12A   = 4,
+       CVBS_CPU_TYPE_G12B   = 5,
 };
 
 struct meson_cvbsout_data {
index 027845e57451ecd388e9d2fdb86808ac1e35747a..28b6fc871f5102d2f3de06333ad1cdb034e31560 100644 (file)
@@ -182,7 +182,8 @@ void set_vmode_clk(void)
                        pr_info("[error]: hdmi_pll lock failed\n");
                cvbs_out_hiu_setb(HHI_VIID_CLK_CNTL, 0, VCLK2_EN, 1);
                udelay(5);
-       } else if (cvbs_cpu_type() == CVBS_CPU_TYPE_G12A) {
+       } else if (cvbs_cpu_type() == CVBS_CPU_TYPE_G12A ||
+                       cvbs_cpu_type() == CVBS_CPU_TYPE_G12B) {
                if (cvbs_clk_path & 0x1) {
                        pr_info("config g12a gp0_pll\n");
                        cvbs_out_hiu_write(HHI_GP0_PLL_CNTL0, 0x180204f7);
@@ -227,7 +228,8 @@ void set_vmode_clk(void)
                        pr_info("[error]: hdmi_pll lock failed\n");
        }
 
-       if (cvbs_cpu_type() == CVBS_CPU_TYPE_G12A) {
+       if (cvbs_cpu_type() == CVBS_CPU_TYPE_G12A ||
+               cvbs_cpu_type() == CVBS_CPU_TYPE_G12B) {
                if (cvbs_clk_path & 0x2)
                        cvbs_set_vid1_clk(cvbs_clk_path & 0x1);
                else
@@ -245,7 +247,8 @@ void set_vmode_clk(void)
 
 void disable_vmode_clk(void)
 {
-       if (cvbs_cpu_type() == CVBS_CPU_TYPE_G12A) {
+       if (cvbs_cpu_type() == CVBS_CPU_TYPE_G12A ||
+               cvbs_cpu_type() == CVBS_CPU_TYPE_G12B) {
                if (cvbs_clk_path & 0x2)
                        disable_vid1_clk_out();
                else
index f1c8e19cca97fd26153dbd97d8c41b2f4656a3da..fbb202decff55f64438372b749606341e7c6e691 100644 (file)
@@ -172,7 +172,8 @@ void ana_ref_cntl0_bit9(bool on, unsigned int module_sel)
 
        if (is_meson_txlx_cpu())
                vdac_hiu_reg_setb(HHI_VDAC_CNTL0, enable, 9, 1);
-       else if (is_meson_g12a_cpu())
+       else if (is_meson_g12a_cpu() ||
+                       is_meson_g12b_cpu())
                vdac_hiu_reg_setb(HHI_VDAC_CNTL0_G12A, ~enable, 9, 1);
        else
                vdac_hiu_reg_setb(HHI_VDAC_CNTL0, ~enable, 9, 1);
@@ -187,7 +188,7 @@ void vdac_out_cntl0_bit10(bool on, unsigned int module_sel)
        bool enable = 0;
 
        /*bit10 is for bandgap startup setting in g12a*/
-       if (is_meson_g12a_cpu())
+       if (is_meson_g12a_cpu() || is_meson_g12b_cpu())
                return;
 
        switch (module_sel & 0xf) {
@@ -273,7 +274,7 @@ void vdac_out_cntl0_bit0(bool on, unsigned int module_sel)
        else
                enable = 1;
 
-       if (is_meson_g12a_cpu())
+       if (is_meson_g12a_cpu() || is_meson_g12b_cpu())
                vdac_hiu_reg_setb(HHI_VDAC_CNTL0_G12A, enable, 0, 1);
        else
                vdac_hiu_reg_setb(HHI_VDAC_CNTL0, enable, 0, 1);
@@ -332,7 +333,7 @@ EXPORT_SYMBOL(vdac_out_cntl1_bit3);
 
 void vdac_set_ctrl0_ctrl1(unsigned int ctrl0, unsigned int ctrl1)
 {
-       if (is_meson_g12a_cpu()) {
+       if (is_meson_g12a_cpu() || is_meson_g12b_cpu()) {
                vdac_hiu_reg_write(HHI_VDAC_CNTL0_G12A, ctrl0);
                vdac_hiu_reg_write(HHI_VDAC_CNTL1_G12A, ctrl1);
        } else {
@@ -368,7 +369,7 @@ void vdac_enable(bool on, unsigned int module_sel)
                        /*Cdac pwd*/
                        vdac_out_cntl1_bit3(1, VDAC_MODULE_ATV_DEMOD);
                        /* enable AFE output buffer */
-                       if (!is_meson_g12a_cpu())
+                       if (!is_meson_g12a_cpu() && !is_meson_g12b_cpu())
                                vdac_hiu_reg_setb(HHI_VDAC_CNTL0, 0, 10, 1);
                        vdac_out_cntl0_bit0(1, VDAC_MODULE_ATV_DEMOD);
                } else {
@@ -378,7 +379,7 @@ void vdac_enable(bool on, unsigned int module_sel)
                                break;
                        vdac_out_cntl0_bit0(0, VDAC_MODULE_ATV_DEMOD);
                        /* Disable AFE output buffer */
-                       if (!is_meson_g12a_cpu())
+                       if (!is_meson_g12a_cpu() && !is_meson_g12b_cpu())
                                vdac_hiu_reg_setb(HHI_VDAC_CNTL0, 0, 10, 1);
                        /* enable dac output */
                        vdac_out_cntl1_bit3(0, 0x4);
@@ -448,7 +449,8 @@ void vdac_enable(bool on, unsigned int module_sel)
                        pri_flag &= ~VDAC_MODULE_CVBS_OUT;
                        if (pri_flag & VDAC_MODULE_ATV_DEMOD) {
                                vdac_out_cntl1_bit3(1, VDAC_MODULE_ATV_DEMOD);
-                               if (!is_meson_g12a_cpu())
+                               if (!is_meson_g12a_cpu() &&
+                                       !is_meson_g12b_cpu())
                                        vdac_hiu_reg_setb(HHI_VDAC_CNTL0,
                                                0, 10, 1);
                                vdac_out_cntl0_bit0(1, VDAC_MODULE_ATV_DEMOD);