}
MFC_WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID);
+
+ if (sfr_dump & MFC_DUMP_DEC_INIT_BUFS)
+ call_dop(dev, dump_regs, dev);
+
s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_INIT_BUFFERS);
return ret;
}
MFC_WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID);
+
+ if (sfr_dump & MFC_DUMP_ENC_INIT_BUFS)
+ call_dop(dev, dump_regs, dev);
+
s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_INIT_BUFFERS);
return ret;
int num_entities;
};
+enum mfc_sfr_dump_type {
+ MFC_DUMP_NONE = 0,
+ MFC_DUMP_DEC_SEQ_START = (1 << 0),
+ MFC_DUMP_DEC_INIT_BUFS = (1 << 1),
+ MFC_DUMP_DEC_NAL_START = (1 << 2),
+ MFC_DUMP_ENC_SEQ_START = (1 << 3),
+ MFC_DUMP_ENC_INIT_BUFS = (1 << 4),
+ MFC_DUMP_ENC_NAL_START = (1 << 5),
+ MFC_DUMP_ERR_INT = (1 << 6),
+ MFC_DUMP_WARN_INT = (1 << 7),
+};
+
struct s5p_mfc_debugfs {
struct dentry *root;
struct dentry *mfc_info;
struct dentry *nal_q_parallel_disable;
struct dentry *otf_dump;
struct dentry *perf_measure_option;
+ struct dentry *sfr_dump;
};
/**
extern struct s5p_mfc_dump_ops mfc_dump_ops;
struct s5p_mfc_dump_ops {
+ void (*dump_regs)(struct s5p_mfc_dev *dev);
void (*dump_and_stop_always)(struct s5p_mfc_dev *dev);
};
struct _otf_handle *otf_handle;
int batch_mode;
+ bool check_dump;
};
#endif /* __S5P_MFC_DATA_STRUCT_H */
extern unsigned int nal_q_disable;
extern unsigned int nal_q_parallel_disable;
extern unsigned int otf_dump;
+extern unsigned int sfr_dump;
#define mfc_debug(level, fmt, args...) \
do { \
unsigned int nal_q_parallel_disable;
unsigned int otf_dump;
unsigned int perf_measure_option;
+unsigned int sfr_dump;
static int mfc_info_show(struct seq_file *s, void *unused)
{
static int mfc_debug_info_show(struct seq_file *s, void *unused)
{
seq_puts(s, ">> MFC debug information\n");
+
+ seq_puts(s, "-----SFR dump options (bit setting)\n");
+ seq_puts(s, "ex) echo 0xff > /d/mfc/sfr_dump (all dump mode)\n");
+ seq_puts(s, "1 (1 << 0): dec SEQ_START\n");
+ seq_puts(s, "2 (1 << 1): dec INIT_BUFS\n");
+ seq_puts(s, "4 (1 << 2): dec NAL_START\n");
+ seq_puts(s, "8 (1 << 3): enc SEQ_START\n");
+ seq_puts(s, "16 (1 << 4): enc INIT_BUFS\n");
+ seq_puts(s, "32 (1 << 5): enc NAL_START\n");
+ seq_puts(s, "64 (1 << 6): ERR interrupt\n");
+ seq_puts(s, "128 (1 << 7): WARN interrupt\n");
+
return 0;
}
0644, debugfs->root, &otf_dump);
debugfs->perf_measure_option = debugfs_create_u32("perf_measure_option",
0644, debugfs->root, &perf_measure_option);
+ debugfs->sfr_dump = debugfs_create_u32("sfr_dump",
+ 0644, debugfs->root, &sfr_dump);
}
dec->consumed = 0;
dec->remained_size = 0;
+ ctx->check_dump = 0;
s5p_mfc_init_queue(&ctx->src_buf_queue);
s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->src_buf_queue),
s5p_mfc_get_queue_count(&ctx->buf_queue_lock, &ctx->dst_buf_queue),
ctx->state, ctx->dpb_count);
- mfc_debug(2, "ctx->state=%d\n", ctx->state);
+ mfc_debug(2, "ctx->state = %d\n", ctx->state);
/* Last frame has already been sent to MFC
* Now obtaining frames from MFC buffer */
mfc_debug(2, "SEI enable was set, 0x%x\n", MFC_READL(S5P_FIMV_D_SEI_ENABLE));
MFC_WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID);
+
+ if (sfr_dump & MFC_DUMP_DEC_SEQ_START)
+ call_dop(dev, dump_regs, dev);
+
s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_SEQ_HEADER);
mfc_debug_leave();
MFC_WRITEL(MFC_TIMEOUT_VALUE, S5P_FIMV_DEC_TIMEOUT_VALUE);
MFC_WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID);
+
+ if ((sfr_dump & MFC_DUMP_DEC_NAL_START) && !ctx->check_dump) {
+ call_dop(dev, dump_regs, dev);
+ ctx->check_dump = 1;
+ }
+
/* Issue different commands to instance basing on whether it
* is the last frame or not. */
switch (last_frame) {
MFC_READL(S5P_FIMV_E_RC_MODE));
MFC_WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID);
+
+ if (sfr_dump & MFC_DUMP_ENC_SEQ_START)
+ call_dop(dev, dump_regs, dev);
+
s5p_mfc_cmd_host2risc(dev, S5P_FIMV_H2R_CMD_SEQ_HEADER);
mfc_debug(2, "--\n");
}
MFC_WRITEL(ctx->inst_no, S5P_FIMV_INSTANCE_ID);
+
+ if ((sfr_dump & MFC_DUMP_ENC_NAL_START) && !ctx->check_dump) {
+ call_dop(dev, dump_regs, dev);
+ ctx->check_dump = 1;
+ }
+
/* Issue different commands to instance basing on whether it
* is the last frame or not. */
switch (last_frame) {
#include "s5p_mfc_qos.h"
#include "s5p_mfc_queue.h"
-#include "s5p_mfc_utils.h"
#include "s5p_mfc_buf.h"
#include "s5p_mfc_mem.h"
if (dbg_enable && (reason != S5P_FIMV_R2H_CMD_QUEUE_DONE_RET))
s5p_mfc_dbg_disable(dev);
+ if ((sfr_dump & MFC_DUMP_ERR_INT) && (reason == S5P_FIMV_R2H_CMD_ERR_RET))
+ call_dop(dev, dump_regs, dev);
+
+ if ((sfr_dump & MFC_DUMP_WARN_INT) &&
+ (err && (reason != S5P_FIMV_R2H_CMD_ERR_RET)))
+ call_dop(dev, dump_regs, dev);
+
#ifdef NAL_Q_ENABLE
if (dev->nal_q_handle) {
ret = mfc_nal_q_irq(dev, reason, err);
#include <linux/interrupt.h>
#include "s5p_mfc_common.h"
-#include "s5p_mfc_reg.h"
+
+#include "s5p_mfc_utils.h"
irqreturn_t s5p_mfc_top_half_irq(int irq, void *priv);
irqreturn_t s5p_mfc_irq(int irq, void *priv);
-static inline int s5p_mfc_dec_status_decoding(unsigned int dst_frame_status)
-{
- if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY ||
- dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_ONLY)
- return 1;
- return 0;
-}
-
-static inline int s5p_mfc_dec_status_display(unsigned int dst_frame_status)
-{
- if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
- dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
- return 1;
-
- return 0;
-}
-
static inline void s5p_mfc_handle_force_change_status(struct s5p_mfc_ctx *ctx)
{
if (ctx->state != MFCINST_ABORT && ctx->state != MFCINST_HEAD_PARSED &&
ctx->state != MFCINST_RES_CHANGE_FLUSH)
s5p_mfc_change_state(ctx, MFCINST_RUNNING);
}
+
#endif /* __S5P_MFC_IRQ_H */
#include "s5p_mfc_utils.h"
#include "s5p_mfc_buf.h"
#include "s5p_mfc_mem.h"
-#include "s5p_mfc_irq.h"
#ifdef NAL_Q_ENABLE
#define CBR_I_LIMIT_MAX 5
dec->assigned_dpb[i] = NULL;
}
+static inline int s5p_mfc_dec_status_decoding(unsigned int dst_frame_status)
+{
+ if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY ||
+ dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_ONLY)
+ return 1;
+ return 0;
+}
+
+static inline int s5p_mfc_dec_status_display(unsigned int dst_frame_status)
+{
+ if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
+ dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
+ return 1;
+
+ return 0;
+}
+
void s5p_mfc_cleanup_assigned_dpb(struct s5p_mfc_ctx *ctx);
void s5p_mfc_unprotect_released_dpb(struct s5p_mfc_ctx *ctx, unsigned int released_flag);
void s5p_mfc_protect_dpb(struct s5p_mfc_ctx *ctx, struct s5p_mfc_buf *dst_mb);
}
struct s5p_mfc_dump_ops mfc_dump_ops = {
+ .dump_regs = mfc_dump_regs,
.dump_and_stop_always = mfc_dump_info_and_stop_hw,
};