ixgbe: Implement firmware interface to access some PHYs

Implement new interface for firmware commands to access some PHYs.

Signed-off-by: Mark Rustad <mark.d.rustad@intel.com>
Tested-by: Krishneil Singh <krishneil.k.singh@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.h
index 671a0cdf69357beb1bf5b799dd19c3e92b34d331..e083732adf649106ee8ae56d665e77649dba6456 100644 (file)
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.h
@@ -116,6 +116,8 @@ u8 ixgbe_calculate_checksum(u8 *buffer, u32 length);
 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *, u32 length,
                                 u32 timeout, bool return_data);
 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 len, u32 timeout);
+s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
+                         u32 (*data)[FW_PHY_ACT_DATA_COUNT]);
 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw);
 bool ixgbe_mng_present(struct ixgbe_hw *hw);
 bool ixgbe_mng_enabled(struct ixgbe_hw *hw);

diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
index 5c59b3c440ec5559e7d2a35b23fd8ff62ffc273b..a8f2d70352414d8031d02a6b14fcb746b22dcef1 100644 (file)
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
@@ -2645,6 +2645,59 @@ enum ixgbe_fdir_pballoc_type {
 #define FW_INT_PHY_REQ_LEN             10
 #define FW_INT_PHY_REQ_READ            0
 #define FW_INT_PHY_REQ_WRITE           1
+#define FW_PHY_ACT_REQ_CMD             5
+#define FW_PHY_ACT_DATA_COUNT          4
+#define FW_PHY_ACT_REQ_LEN             (4 + 4 * FW_PHY_ACT_DATA_COUNT)
+#define FW_PHY_ACT_INIT_PHY            1
+#define FW_PHY_ACT_SETUP_LINK          2
+#define FW_PHY_ACT_LINK_SPEED_10       BIT(0)
+#define FW_PHY_ACT_LINK_SPEED_100      BIT(1)
+#define FW_PHY_ACT_LINK_SPEED_1G       BIT(2)
+#define FW_PHY_ACT_LINK_SPEED_2_5G     BIT(3)
+#define FW_PHY_ACT_LINK_SPEED_5G       BIT(4)
+#define FW_PHY_ACT_LINK_SPEED_10G      BIT(5)
+#define FW_PHY_ACT_LINK_SPEED_20G      BIT(6)
+#define FW_PHY_ACT_LINK_SPEED_25G      BIT(7)
+#define FW_PHY_ACT_LINK_SPEED_40G      BIT(8)
+#define FW_PHY_ACT_LINK_SPEED_50G      BIT(9)
+#define FW_PHY_ACT_LINK_SPEED_100G     BIT(10)
+#define FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT 16
+#define FW_PHY_ACT_SETUP_LINK_PAUSE_MASK (3 << \
+                                         HW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT)
+#define FW_PHY_ACT_SETUP_LINK_PAUSE_NONE 0u
+#define FW_PHY_ACT_SETUP_LINK_PAUSE_TX 1u
+#define FW_PHY_ACT_SETUP_LINK_PAUSE_RX 2u
+#define FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX 3u
+#define FW_PHY_ACT_SETUP_LINK_LP       BIT(18)
+#define FW_PHY_ACT_SETUP_LINK_HP       BIT(19)
+#define FW_PHY_ACT_SETUP_LINK_EEE      BIT(20)
+#define FW_PHY_ACT_SETUP_LINK_AN       BIT(22)
+#define FW_PHY_ACT_SETUP_LINK_RSP_DOWN BIT(0)
+#define FW_PHY_ACT_GET_LINK_INFO       3
+#define FW_PHY_ACT_GET_LINK_INFO_EEE   BIT(19)
+#define FW_PHY_ACT_GET_LINK_INFO_FC_TX BIT(20)
+#define FW_PHY_ACT_GET_LINK_INFO_FC_RX BIT(21)
+#define FW_PHY_ACT_GET_LINK_INFO_POWER BIT(22)
+#define FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE   BIT(24)
+#define FW_PHY_ACT_GET_LINK_INFO_TEMP  BIT(25)
+#define FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX      BIT(28)
+#define FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX      BIT(29)
+#define FW_PHY_ACT_FORCE_LINK_DOWN     4
+#define FW_PHY_ACT_FORCE_LINK_DOWN_OFF BIT(0)
+#define FW_PHY_ACT_PHY_SW_RESET                5
+#define FW_PHY_ACT_PHY_HW_RESET                6
+#define FW_PHY_ACT_GET_PHY_INFO                7
+#define FW_PHY_ACT_UD_2                        0x1002
+#define FW_PHY_ACT_UD_2_10G_KR_EEE     BIT(6)
+#define FW_PHY_ACT_UD_2_10G_KX4_EEE    BIT(5)
+#define FW_PHY_ACT_UD_2_1G_KX_EEE      BIT(4)
+#define FW_PHY_ACT_UD_2_10G_T_EEE      BIT(3)
+#define FW_PHY_ACT_UD_2_1G_T_EEE       BIT(2)
+#define FW_PHY_ACT_UD_2_100M_TX_EEE    BIT(1)
+#define FW_PHY_ACT_RETRIES             50
+#define FW_PHY_INFO_SPEED_MASK         0xFFFu
+#define FW_PHY_INFO_ID_HI_MASK         0xFFFF0000u
+#define FW_PHY_INFO_ID_LO_MASK         0x0000FFFFu
 
 /* Host Interface Command Structures */
 struct ixgbe_hic_hdr {
@@ -2745,6 +2798,19 @@ struct ixgbe_hic_internal_phy_resp {
        __be32 read_data;
 };
 
+struct ixgbe_hic_phy_activity_req {
+       struct ixgbe_hic_hdr hdr;
+       u8 port_number;
+       u8 pad;
+       __le16 activity_id;
+       __be32 data[FW_PHY_ACT_DATA_COUNT];
+};
+
+struct ixgbe_hic_phy_activity_resp {
+       struct ixgbe_hic_hdr hdr;
+       __be32 data[FW_PHY_ACT_DATA_COUNT];
+};
+
 /* Transmit Descriptor - Advanced */
 union ixgbe_adv_tx_desc {
        struct {

diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
index 5a6c4b7f7e33dc9079353780a5cc4462dd65ae21..9dc6079f2ac4b24e6fa4e7f316208d4f03813e08 100644 (file)
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c
@@ -402,6 +402,51 @@ ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
        return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
 }
 
+/**
+ * ixgbe_fw_phy_activity - Perform an activity on a PHY
+ * @hw: pointer to hardware structure
+ * @activity: activity to perform
+ * @data: Pointer to 4 32-bit words of data
+ */
+s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
+                         u32 (*data)[FW_PHY_ACT_DATA_COUNT])
+{
+       union {
+               struct ixgbe_hic_phy_activity_req cmd;
+               struct ixgbe_hic_phy_activity_resp rsp;
+       } hic;
+       u16 retries = FW_PHY_ACT_RETRIES;
+       s32 rc;
+       u32 i;
+
+       do {
+               memset(&hic, 0, sizeof(hic));
+               hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
+               hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
+               hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
+               hic.cmd.port_number = hw->bus.lan_id;
+               hic.cmd.activity_id = cpu_to_le16(activity);
+               for (i = 0; i < ARRAY_SIZE(hic.cmd.data); ++i)
+                       hic.cmd.data[i] = cpu_to_be32((*data)[i]);
+
+               rc = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
+                                                 IXGBE_HI_COMMAND_TIMEOUT,
+                                                 true);
+               if (rc)
+                       return rc;
+               if (hic.rsp.hdr.cmd_or_resp.ret_status ==
+                   FW_CEM_RESP_STATUS_SUCCESS) {
+                       for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
+                               (*data)[i] = be32_to_cpu(hic.rsp.data[i]);
+                       return 0;
+               }
+               usleep_range(20, 30);
+               --retries;
+       } while (retries > 0);
+
+       return IXGBE_ERR_HOST_INTERFACE_COMMAND;
+}
+
 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
  *  @hw: pointer to hardware structure
  *