pinctrl: rockchip: Add rv1108 recalculated iomux support

The pins from GPIO1A0 to GPIO1B1 are special, need to recalculate
iomux. And the register offset is larger than the u8 range, so changed
to u32.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index c6f472e1bca63cf7a64fdef4042c4f4a11de1391..b5cb7858ffdcdf43bd399c61af2fc36d4b0c039b 100644 (file)
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -301,7 +301,7 @@ struct rockchip_pin_bank {
 struct rockchip_mux_recalced_data {
        u8 num;
        u8 pin;
-       u8 reg;
+       u32 reg;
        u8 bit;
        u8 mask;
 };
@@ -558,6 +558,70 @@ static const struct pinctrl_ops rockchip_pctrl_ops = {
  * Hardware access
  */
 
+static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
+       {
+               .num = 1,
+               .pin = 0,
+               .reg = 0x418,
+               .bit = 0,
+               .mask = 0x3
+       }, {
+               .num = 1,
+               .pin = 1,
+               .reg = 0x418,
+               .bit = 2,
+               .mask = 0x3
+       }, {
+               .num = 1,
+               .pin = 2,
+               .reg = 0x418,
+               .bit = 4,
+               .mask = 0x3
+       }, {
+               .num = 1,
+               .pin = 3,
+               .reg = 0x418,
+               .bit = 6,
+               .mask = 0x3
+       }, {
+               .num = 1,
+               .pin = 4,
+               .reg = 0x418,
+               .bit = 8,
+               .mask = 0x3
+       }, {
+               .num = 1,
+               .pin = 5,
+               .reg = 0x418,
+               .bit = 10,
+               .mask = 0x3
+       }, {
+               .num = 1,
+               .pin = 6,
+               .reg = 0x418,
+               .bit = 12,
+               .mask = 0x3
+       }, {
+               .num = 1,
+               .pin = 7,
+               .reg = 0x418,
+               .bit = 14,
+               .mask = 0x3
+       }, {
+               .num = 1,
+               .pin = 8,
+               .reg = 0x41c,
+               .bit = 0,
+               .mask = 0x3
+       }, {
+               .num = 1,
+               .pin = 9,
+               .reg = 0x41c,
+               .bit = 2,
+               .mask = 0x3
+       },
+};
+
 static  struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
        {
                .num = 2,
@@ -3162,6 +3226,8 @@ static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
        .type                   = RV1108,
        .grf_mux_offset         = 0x10,
        .pmu_mux_offset         = 0x0,
+       .iomux_recalced         = rv1108_mux_recalced_data,
+       .niomux_recalced        = ARRAY_SIZE(rv1108_mux_recalced_data),
        .pull_calc_reg          = rv1108_calc_pull_reg_and_bit,
        .drv_calc_reg           = rv1108_calc_drv_reg_and_bit,
        .schmitt_calc_reg       = rv1108_calc_schmitt_reg_and_bit,