drm/i915/bdw: Macro for LRCs and module option for Execlists
authorOscar Mateo <oscar.mateo@intel.com>
Thu, 24 Jul 2014 16:04:11 +0000 (17:04 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 11 Aug 2014 14:00:27 +0000 (16:00 +0200)
GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
These expanded contexts enable a number of new abilities, especially
"Execlists".

The macro is defined to off until we have things in place to hope to
work.

v2: Rename "advanced contexts" to the more correct "logical ring
contexts".

v3: Add a module parameter to enable execlists. Execlist are relatively
new, and so it'd be wise to be able to switch back to ring submission
to debug subtle problems that will inevitably arise.

v4: Add an intel_enable_execlists function.

v5: Sanitize early, as suggested by Daniel. Remove lrc_enabled.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v3)
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> (v2, v4 & v5)
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/i915_params.c
drivers/gpu/drm/i915/intel_lrc.c
drivers/gpu/drm/i915/intel_lrc.h

index ec2a094f362297be7bbc553d61d08e0ba5a28ada..fd2aa15ce02b59ed4398d4d1b9cfc1aebf6b9b80 100644 (file)
@@ -2062,6 +2062,7 @@ struct drm_i915_cmd_table {
 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
 
 #define HAS_HW_CONTEXTS(dev)   (INTEL_INFO(dev)->gen >= 6)
+#define HAS_LOGICAL_RING_CONTEXTS(dev) 0
 #define HAS_ALIASING_PPGTT(dev)        (INTEL_INFO(dev)->gen >= 6)
 #define HAS_PPGTT(dev)         (INTEL_INFO(dev)->gen >= 7 && !IS_GEN8(dev))
 #define USES_PPGTT(dev)                (i915.enable_ppgtt)
@@ -2149,6 +2150,7 @@ struct i915_params {
        int enable_rc6;
        int enable_fbc;
        int enable_ppgtt;
+       int enable_execlists;
        int enable_psr;
        unsigned int preliminary_hw_support;
        int disable_power_well;
index 3eec344bdac09b59c71f01c26d5ad2ce29483e34..5646e9ba6383647bf435d034c354de4316c50335 100644 (file)
@@ -4723,6 +4723,9 @@ int i915_gem_init(struct drm_device *dev)
        struct drm_i915_private *dev_priv = dev->dev_private;
        int ret;
 
+       i915.enable_execlists = intel_sanitize_enable_execlists(dev,
+                       i915.enable_execlists);
+
        mutex_lock(&dev->struct_mutex);
 
        if (IS_VALLEYVIEW(dev)) {
index 62ee8308d6829140976b860f9d1e574b3d5c93b2..f7f8350c379397f210f63a49e354d4f22c73fcd3 100644 (file)
@@ -35,6 +35,7 @@ struct i915_params i915 __read_mostly = {
        .vbt_sdvo_panel_type = -1,
        .enable_rc6 = -1,
        .enable_fbc = -1,
+       .enable_execlists = -1,
        .enable_hangcheck = true,
        .enable_ppgtt = -1,
        .enable_psr = 1,
@@ -118,6 +119,11 @@ MODULE_PARM_DESC(enable_ppgtt,
        "Override PPGTT usage. "
        "(-1=auto [default], 0=disabled, 1=aliasing, 2=full)");
 
+module_param_named(enable_execlists, i915.enable_execlists, int, 0400);
+MODULE_PARM_DESC(enable_execlists,
+       "Override execlists usage. "
+       "(-1=auto [default], 0=disabled, 1=enabled)");
+
 module_param_named(enable_psr, i915.enable_psr, int, 0600);
 MODULE_PARM_DESC(enable_psr, "Enable PSR (default: true)");
 
index 49bb6fcdface6680361d12e4e7d9ddb10f2c7421..21f7f1cce86ed7f75fe92a87a3ffe8ca941c44da 100644 (file)
 #include <drm/drmP.h>
 #include <drm/i915_drm.h>
 #include "i915_drv.h"
+
+int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists)
+{
+       if (enable_execlists == 0)
+               return 0;
+
+       if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev))
+               return 1;
+
+       return 0;
+}
index f6830a4ec773d11bea63d81556ea5401df98603d..75ee9c3cb7dc067c5f7c82e8f71d52f3aa68794c 100644 (file)
@@ -24,4 +24,7 @@
 #ifndef _INTEL_LRC_H_
 #define _INTEL_LRC_H_
 
+/* Execlists */
+int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists);
+
 #endif /* _INTEL_LRC_H_ */