e1000: updated whitespace and comments
authorJesse Brandeburg <jesse.brandeburg@intel.com>
Fri, 25 Sep 2009 22:19:46 +0000 (15:19 -0700)
committerDavid S. Miller <davem@davemloft.net>
Sun, 27 Sep 2009 03:15:55 +0000 (20:15 -0700)
A large whitespace change to e1000_hw.[ch] in order to update it to kernel coding
style (by running lindent).  Updated function header comments into kdoc style.

Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/e1000/e1000_hw.c
drivers/net/e1000/e1000_hw.h
drivers/net/e1000/e1000_main.c

index 076db19f69f4f5b8ee7ba54a71f352d7b5c2bacc..6aba88304407d571acafa7e11e8a4ae6bfb75bad 100644 (file)
   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 
-*******************************************************************************/
+ */
 
 /* e1000_hw.c
  * Shared functions for accessing and configuring the MAC
  */
 
-
 #include "e1000_hw.h"
 
 static s32 e1000_check_downshift(struct e1000_hw *hw);
@@ -69,12 +68,11 @@ static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
 static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
-static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data,
-                                    u16 count);
+static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);
 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
-                                      u16 words, u16 *data);
+                                 u16 words, u16 *data);
 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
                                        u16 words, u16 *data);
 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
@@ -83,7 +81,7 @@ static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
                                  u16 phy_data);
-static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw,u32 reg_addr,
+static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
                                 u16 *phy_data);
 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
 static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
@@ -92,159 +90,164 @@ static void e1000_standby_eeprom(struct e1000_hw *hw);
 static s32 e1000_set_vco_speed(struct e1000_hw *hw);
 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
 static s32 e1000_set_phy_mode(struct e1000_hw *hw);
-static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
-static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
+static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
+                               u16 *data);
+static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
+                                u16 *data);
 
 /* IGP cable length table */
 static const
-u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
-    { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
-      5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
-      25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
-      40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
-      60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
-      90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
-      100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
-      110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
+u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {
+       5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
+       5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
+       25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
+       40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
+       60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
+       90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,
+           100,
+       100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
+           110, 110,
+       110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,
+           120, 120
+};
 
 static DEFINE_SPINLOCK(e1000_eeprom_lock);
 
-/******************************************************************************
- * Set the phy type member in the hw struct.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+/**
+ * e1000_set_phy_type - Set the phy type member in the hw struct.
+ * @hw: Struct containing variables accessed by shared code
+ */
 static s32 e1000_set_phy_type(struct e1000_hw *hw)
 {
-    DEBUGFUNC("e1000_set_phy_type");
-
-    if (hw->mac_type == e1000_undefined)
-        return -E1000_ERR_PHY_TYPE;
-
-    switch (hw->phy_id) {
-    case M88E1000_E_PHY_ID:
-    case M88E1000_I_PHY_ID:
-    case M88E1011_I_PHY_ID:
-    case M88E1111_I_PHY_ID:
-        hw->phy_type = e1000_phy_m88;
-        break;
-    case IGP01E1000_I_PHY_ID:
-        if (hw->mac_type == e1000_82541 ||
-            hw->mac_type == e1000_82541_rev_2 ||
-            hw->mac_type == e1000_82547 ||
-            hw->mac_type == e1000_82547_rev_2) {
-            hw->phy_type = e1000_phy_igp;
-            break;
-        }
-    default:
-        /* Should never have loaded on this device */
-        hw->phy_type = e1000_phy_undefined;
-        return -E1000_ERR_PHY_TYPE;
-    }
-
-    return E1000_SUCCESS;
-}
-
-/******************************************************************************
- * IGP phy init script - initializes the GbE PHY
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static void e1000_phy_init_script(struct e1000_hw *hw)
-{
-    u32 ret_val;
-    u16 phy_saved_data;
-
-    DEBUGFUNC("e1000_phy_init_script");
-
-    if (hw->phy_init_script) {
-        msleep(20);
-
-        /* Save off the current value of register 0x2F5B to be restored at
-         * the end of this routine. */
-        ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
-
-        /* Disabled the PHY transmitter */
-        e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
-
-        msleep(20);
-
-        e1000_write_phy_reg(hw,0x0000,0x0140);
-
-        msleep(5);
-
-        switch (hw->mac_type) {
-        case e1000_82541:
-        case e1000_82547:
-            e1000_write_phy_reg(hw, 0x1F95, 0x0001);
-
-            e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
-
-            e1000_write_phy_reg(hw, 0x1F79, 0x0018);
-
-            e1000_write_phy_reg(hw, 0x1F30, 0x1600);
-
-            e1000_write_phy_reg(hw, 0x1F31, 0x0014);
-
-            e1000_write_phy_reg(hw, 0x1F32, 0x161C);
-
-            e1000_write_phy_reg(hw, 0x1F94, 0x0003);
-
-            e1000_write_phy_reg(hw, 0x1F96, 0x003F);
-
-            e1000_write_phy_reg(hw, 0x2010, 0x0008);
-            break;
-
-        case e1000_82541_rev_2:
-        case e1000_82547_rev_2:
-            e1000_write_phy_reg(hw, 0x1F73, 0x0099);
-            break;
-        default:
-            break;
-        }
-
-        e1000_write_phy_reg(hw, 0x0000, 0x3300);
-
-        msleep(20);
-
-        /* Now enable the transmitter */
-        e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
-
-        if (hw->mac_type == e1000_82547) {
-            u16 fused, fine, coarse;
+       DEBUGFUNC("e1000_set_phy_type");
 
-            /* Move to analog registers page */
-            e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
+       if (hw->mac_type == e1000_undefined)
+               return -E1000_ERR_PHY_TYPE;
 
-            if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
-                e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
+       switch (hw->phy_id) {
+       case M88E1000_E_PHY_ID:
+       case M88E1000_I_PHY_ID:
+       case M88E1011_I_PHY_ID:
+       case M88E1111_I_PHY_ID:
+               hw->phy_type = e1000_phy_m88;
+               break;
+       case IGP01E1000_I_PHY_ID:
+               if (hw->mac_type == e1000_82541 ||
+                   hw->mac_type == e1000_82541_rev_2 ||
+                   hw->mac_type == e1000_82547 ||
+                   hw->mac_type == e1000_82547_rev_2) {
+                       hw->phy_type = e1000_phy_igp;
+                       break;
+               }
+       default:
+               /* Should never have loaded on this device */
+               hw->phy_type = e1000_phy_undefined;
+               return -E1000_ERR_PHY_TYPE;
+       }
 
-                fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
-                coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
+       return E1000_SUCCESS;
+}
 
-                if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
-                    coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
-                    fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
-                } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
-                    fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
+/**
+ * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY
+ * @hw: Struct containing variables accessed by shared code
+ */
+static void e1000_phy_init_script(struct e1000_hw *hw)
+{
+       u32 ret_val;
+       u16 phy_saved_data;
+
+       DEBUGFUNC("e1000_phy_init_script");
+
+       if (hw->phy_init_script) {
+               msleep(20);
+
+               /* Save off the current value of register 0x2F5B to be restored at
+                * the end of this routine. */
+               ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
+
+               /* Disabled the PHY transmitter */
+               e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
+               msleep(20);
+
+               e1000_write_phy_reg(hw, 0x0000, 0x0140);
+               msleep(5);
+
+               switch (hw->mac_type) {
+               case e1000_82541:
+               case e1000_82547:
+                       e1000_write_phy_reg(hw, 0x1F95, 0x0001);
+                       e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
+                       e1000_write_phy_reg(hw, 0x1F79, 0x0018);
+                       e1000_write_phy_reg(hw, 0x1F30, 0x1600);
+                       e1000_write_phy_reg(hw, 0x1F31, 0x0014);
+                       e1000_write_phy_reg(hw, 0x1F32, 0x161C);
+                       e1000_write_phy_reg(hw, 0x1F94, 0x0003);
+                       e1000_write_phy_reg(hw, 0x1F96, 0x003F);
+                       e1000_write_phy_reg(hw, 0x2010, 0x0008);
+                       break;
 
-                fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
-                        (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
-                        (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
+               case e1000_82541_rev_2:
+               case e1000_82547_rev_2:
+                       e1000_write_phy_reg(hw, 0x1F73, 0x0099);
+                       break;
+               default:
+                       break;
+               }
 
-                e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
-                e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
-                                    IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
-            }
-        }
-    }
+               e1000_write_phy_reg(hw, 0x0000, 0x3300);
+               msleep(20);
+
+               /* Now enable the transmitter */
+               e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
+
+               if (hw->mac_type == e1000_82547) {
+                       u16 fused, fine, coarse;
+
+                       /* Move to analog registers page */
+                       e1000_read_phy_reg(hw,
+                                          IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
+                                          &fused);
+
+                       if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
+                               e1000_read_phy_reg(hw,
+                                                  IGP01E1000_ANALOG_FUSE_STATUS,
+                                                  &fused);
+
+                               fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
+                               coarse =
+                                   fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
+
+                               if (coarse >
+                                   IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
+                                       coarse -=
+                                           IGP01E1000_ANALOG_FUSE_COARSE_10;
+                                       fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
+                               } else if (coarse ==
+                                          IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
+                                       fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
+
+                               fused =
+                                   (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
+                                   (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
+                                   (coarse &
+                                    IGP01E1000_ANALOG_FUSE_COARSE_MASK);
+
+                               e1000_write_phy_reg(hw,
+                                                   IGP01E1000_ANALOG_FUSE_CONTROL,
+                                                   fused);
+                               e1000_write_phy_reg(hw,
+                                                   IGP01E1000_ANALOG_FUSE_BYPASS,
+                                                   IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
+                       }
+               }
+       }
 }
 
-/******************************************************************************
- * Set the mac type member in the hw struct.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+/**
+ * e1000_set_mac_type - Set the mac type member in the hw struct.
+ * @hw: Struct containing variables accessed by shared code
+ */
 s32 e1000_set_mac_type(struct e1000_hw *hw)
 {
        DEBUGFUNC("e1000_set_mac_type");
@@ -348,1801 +351,1850 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
        return E1000_SUCCESS;
 }
 
-/*****************************************************************************
- * Set media type and TBI compatibility.
- *
- * hw - Struct containing variables accessed by shared code
- * **************************************************************************/
+/**
+ * e1000_set_media_type - Set media type and TBI compatibility.
+ * @hw: Struct containing variables accessed by shared code
+ */
 void e1000_set_media_type(struct e1000_hw *hw)
 {
-    u32 status;
-
-    DEBUGFUNC("e1000_set_media_type");
-
-    if (hw->mac_type != e1000_82543) {
-        /* tbi_compatibility is only valid on 82543 */
-        hw->tbi_compatibility_en = false;
-    }
-
-    switch (hw->device_id) {
-    case E1000_DEV_ID_82545GM_SERDES:
-    case E1000_DEV_ID_82546GB_SERDES:
-        hw->media_type = e1000_media_type_internal_serdes;
-        break;
-    default:
-        switch (hw->mac_type) {
-        case e1000_82542_rev2_0:
-        case e1000_82542_rev2_1:
-            hw->media_type = e1000_media_type_fiber;
-            break;
-        default:
-            status = er32(STATUS);
-            if (status & E1000_STATUS_TBIMODE) {
-                hw->media_type = e1000_media_type_fiber;
-                /* tbi_compatibility not valid on fiber */
-                hw->tbi_compatibility_en = false;
-            } else {
-                hw->media_type = e1000_media_type_copper;
-            }
-            break;
-        }
-    }
+       u32 status;
+
+       DEBUGFUNC("e1000_set_media_type");
+
+       if (hw->mac_type != e1000_82543) {
+               /* tbi_compatibility is only valid on 82543 */
+               hw->tbi_compatibility_en = false;
+       }
+
+       switch (hw->device_id) {
+       case E1000_DEV_ID_82545GM_SERDES:
+       case E1000_DEV_ID_82546GB_SERDES:
+               hw->media_type = e1000_media_type_internal_serdes;
+               break;
+       default:
+               switch (hw->mac_type) {
+               case e1000_82542_rev2_0:
+               case e1000_82542_rev2_1:
+                       hw->media_type = e1000_media_type_fiber;
+                       break;
+               default:
+                       status = er32(STATUS);
+                       if (status & E1000_STATUS_TBIMODE) {
+                               hw->media_type = e1000_media_type_fiber;
+                               /* tbi_compatibility not valid on fiber */
+                               hw->tbi_compatibility_en = false;
+                       } else {
+                               hw->media_type = e1000_media_type_copper;
+                       }
+                       break;
+               }
+       }
 }
 
-/******************************************************************************
- * Reset the transmit and receive units; mask and clear all interrupts.
+/**
+ * e1000_reset_hw: reset the hardware completely
+ * @hw: Struct containing variables accessed by shared code
  *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+ * Reset the transmit and receive units; mask and clear all interrupts.
+ */
 s32 e1000_reset_hw(struct e1000_hw *hw)
 {
-    u32 ctrl;
-    u32 ctrl_ext;
-    u32 icr;
-    u32 manc;
-    u32 led_ctrl;
-    s32 ret_val;
-
-    DEBUGFUNC("e1000_reset_hw");
-
-    /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
-    if (hw->mac_type == e1000_82542_rev2_0) {
-        DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
-        e1000_pci_clear_mwi(hw);
-    }
-
-    /* Clear interrupt mask to stop board from generating interrupts */
-    DEBUGOUT("Masking off all interrupts\n");
-    ew32(IMC, 0xffffffff);
-
-    /* Disable the Transmit and Receive units.  Then delay to allow
-     * any pending transactions to complete before we hit the MAC with
-     * the global reset.
-     */
-    ew32(RCTL, 0);
-    ew32(TCTL, E1000_TCTL_PSP);
-    E1000_WRITE_FLUSH();
-
-    /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
-    hw->tbi_compatibility_on = false;
-
-    /* Delay to allow any outstanding PCI transactions to complete before
-     * resetting the device
-     */
-    msleep(10);
-
-    ctrl = er32(CTRL);
-
-    /* Must reset the PHY before resetting the MAC */
-    if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
-        ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
-        msleep(5);
-    }
-
-    /* Issue a global reset to the MAC.  This will reset the chip's
-     * transmit, receive, DMA, and link units.  It will not effect
-     * the current PCI configuration.  The global reset bit is self-
-     * clearing, and should clear within a microsecond.
-     */
-    DEBUGOUT("Issuing a global reset to MAC\n");
-
-    switch (hw->mac_type) {
-        case e1000_82544:
-        case e1000_82540:
-        case e1000_82545:
-        case e1000_82546:
-        case e1000_82541:
-        case e1000_82541_rev_2:
-            /* These controllers can't ack the 64-bit write when issuing the
-             * reset, so use IO-mapping as a workaround to issue the reset */
-            E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
-            break;
-        case e1000_82545_rev_3:
-        case e1000_82546_rev_3:
-            /* Reset is performed on a shadow of the control register */
-            ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
-            break;
-        default:
-            ew32(CTRL, (ctrl | E1000_CTRL_RST));
-            break;
-    }
-
-    /* After MAC reset, force reload of EEPROM to restore power-on settings to
-     * device.  Later controllers reload the EEPROM automatically, so just wait
-     * for reload to complete.
-     */
-    switch (hw->mac_type) {
-        case e1000_82542_rev2_0:
-        case e1000_82542_rev2_1:
-        case e1000_82543:
-        case e1000_82544:
-            /* Wait for reset to complete */
-            udelay(10);
-            ctrl_ext = er32(CTRL_EXT);
-            ctrl_ext |= E1000_CTRL_EXT_EE_RST;
-            ew32(CTRL_EXT, ctrl_ext);
-            E1000_WRITE_FLUSH();
-            /* Wait for EEPROM reload */
-            msleep(2);
-            break;
-        case e1000_82541:
-        case e1000_82541_rev_2:
-        case e1000_82547:
-        case e1000_82547_rev_2:
-            /* Wait for EEPROM reload */
-            msleep(20);
-            break;
-        default:
-            /* Auto read done will delay 5ms or poll based on mac type */
-            ret_val = e1000_get_auto_rd_done(hw);
-            if (ret_val)
-                return ret_val;
-            break;
-    }
-
-    /* Disable HW ARPs on ASF enabled adapters */
-    if (hw->mac_type >= e1000_82540) {
-        manc = er32(MANC);
-        manc &= ~(E1000_MANC_ARP_EN);
-        ew32(MANC, manc);
-    }
-
-    if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
-        e1000_phy_init_script(hw);
-
-        /* Configure activity LED after PHY reset */
-        led_ctrl = er32(LEDCTL);
-        led_ctrl &= IGP_ACTIVITY_LED_MASK;
-        led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
-        ew32(LEDCTL, led_ctrl);
-    }
-
-    /* Clear interrupt mask to stop board from generating interrupts */
-    DEBUGOUT("Masking off all interrupts\n");
-    ew32(IMC, 0xffffffff);
-
-    /* Clear any pending interrupt events. */
-    icr = er32(ICR);
-
-    /* If MWI was previously enabled, reenable it. */
-    if (hw->mac_type == e1000_82542_rev2_0) {
-        if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
-            e1000_pci_set_mwi(hw);
-    }
-
-    return E1000_SUCCESS;
+       u32 ctrl;
+       u32 ctrl_ext;
+       u32 icr;
+       u32 manc;
+       u32 led_ctrl;
+       s32 ret_val;
+
+       DEBUGFUNC("e1000_reset_hw");
+
+       /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
+       if (hw->mac_type == e1000_82542_rev2_0) {
+               DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
+               e1000_pci_clear_mwi(hw);
+       }
+
+       /* Clear interrupt mask to stop board from generating interrupts */
+       DEBUGOUT("Masking off all interrupts\n");
+       ew32(IMC, 0xffffffff);
+
+       /* Disable the Transmit and Receive units.  Then delay to allow
+        * any pending transactions to complete before we hit the MAC with
+        * the global reset.
+        */
+       ew32(RCTL, 0);
+       ew32(TCTL, E1000_TCTL_PSP);
+       E1000_WRITE_FLUSH();
+
+       /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
+       hw->tbi_compatibility_on = false;
+
+       /* Delay to allow any outstanding PCI transactions to complete before
+        * resetting the device
+        */
+       msleep(10);
+
+       ctrl = er32(CTRL);
+
+       /* Must reset the PHY before resetting the MAC */
+       if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
+               ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
+               msleep(5);
+       }
+
+       /* Issue a global reset to the MAC.  This will reset the chip's
+        * transmit, receive, DMA, and link units.  It will not effect
+        * the current PCI configuration.  The global reset bit is self-
+        * clearing, and should clear within a microsecond.
+        */
+       DEBUGOUT("Issuing a global reset to MAC\n");
+
+       switch (hw->mac_type) {
+       case e1000_82544:
+       case e1000_82540:
+       case e1000_82545:
+       case e1000_82546:
+       case e1000_82541:
+       case e1000_82541_rev_2:
+               /* These controllers can't ack the 64-bit write when issuing the
+                * reset, so use IO-mapping as a workaround to issue the reset */
+               E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
+               break;
+       case e1000_82545_rev_3:
+       case e1000_82546_rev_3:
+               /* Reset is performed on a shadow of the control register */
+               ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
+               break;
+       default:
+               ew32(CTRL, (ctrl | E1000_CTRL_RST));
+               break;
+       }
+
+       /* After MAC reset, force reload of EEPROM to restore power-on settings to
+        * device.  Later controllers reload the EEPROM automatically, so just wait
+        * for reload to complete.
+        */
+       switch (hw->mac_type) {
+       case e1000_82542_rev2_0:
+       case e1000_82542_rev2_1:
+       case e1000_82543:
+       case e1000_82544:
+               /* Wait for reset to complete */
+               udelay(10);
+               ctrl_ext = er32(CTRL_EXT);
+               ctrl_ext |= E1000_CTRL_EXT_EE_RST;
+               ew32(CTRL_EXT, ctrl_ext);
+               E1000_WRITE_FLUSH();
+               /* Wait for EEPROM reload */
+               msleep(2);
+               break;
+       case e1000_82541:
+       case e1000_82541_rev_2:
+       case e1000_82547:
+       case e1000_82547_rev_2:
+               /* Wait for EEPROM reload */
+               msleep(20);
+               break;
+       default:
+               /* Auto read done will delay 5ms or poll based on mac type */
+               ret_val = e1000_get_auto_rd_done(hw);
+               if (ret_val)
+                       return ret_val;
+               break;
+       }
+
+       /* Disable HW ARPs on ASF enabled adapters */
+       if (hw->mac_type >= e1000_82540) {
+               manc = er32(MANC);
+               manc &= ~(E1000_MANC_ARP_EN);
+               ew32(MANC, manc);
+       }
+
+       if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
+               e1000_phy_init_script(hw);
+
+               /* Configure activity LED after PHY reset */
+               led_ctrl = er32(LEDCTL);
+               led_ctrl &= IGP_ACTIVITY_LED_MASK;
+               led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
+               ew32(LEDCTL, led_ctrl);
+       }
+
+       /* Clear interrupt mask to stop board from generating interrupts */
+       DEBUGOUT("Masking off all interrupts\n");
+       ew32(IMC, 0xffffffff);
+
+       /* Clear any pending interrupt events. */
+       icr = er32(ICR);
+
+       /* If MWI was previously enabled, reenable it. */
+       if (hw->mac_type == e1000_82542_rev2_0) {
+               if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
+                       e1000_pci_set_mwi(hw);
+       }
+
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Performs basic configuration of the adapter.
- *
- * hw - Struct containing variables accessed by shared code
+/**
+ * e1000_init_hw: Performs basic configuration of the adapter.
+ * @hw: Struct containing variables accessed by shared code
  *
  * Assumes that the controller has previously been reset and is in a
  * post-reset uninitialized state. Initializes the receive address registers,
  * multicast table, and VLAN filter table. Calls routines to setup link
  * configuration and flow control settings. Clears all on-chip counters. Leaves
  * the transmit and receive units disabled and uninitialized.
- *****************************************************************************/
+ */
 s32 e1000_init_hw(struct e1000_hw *hw)
 {
-    u32 ctrl;
-    u32 i;
-    s32 ret_val;
-    u32 mta_size;
-    u32 ctrl_ext;
-
-    DEBUGFUNC("e1000_init_hw");
-
-    /* Initialize Identification LED */
-    ret_val = e1000_id_led_init(hw);
-    if (ret_val) {
-        DEBUGOUT("Error Initializing Identification LED\n");
-        return ret_val;
-    }
-
-    /* Set the media type and TBI compatibility */
-    e1000_set_media_type(hw);
-
-    /* Disabling VLAN filtering. */
-    DEBUGOUT("Initializing the IEEE VLAN\n");
-    if (hw->mac_type < e1000_82545_rev_3)
-        ew32(VET, 0);
-    e1000_clear_vfta(hw);
-
-    /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
-    if (hw->mac_type == e1000_82542_rev2_0) {
-        DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
-        e1000_pci_clear_mwi(hw);
-        ew32(RCTL, E1000_RCTL_RST);
-        E1000_WRITE_FLUSH();
-        msleep(5);
-    }
-
-    /* Setup the receive address. This involves initializing all of the Receive
-     * Address Registers (RARs 0 - 15).
-     */
-    e1000_init_rx_addrs(hw);
-
-    /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
-    if (hw->mac_type == e1000_82542_rev2_0) {
-        ew32(RCTL, 0);
-        E1000_WRITE_FLUSH();
-        msleep(1);
-        if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
-            e1000_pci_set_mwi(hw);
-    }
-
-    /* Zero out the Multicast HASH table */
-    DEBUGOUT("Zeroing the MTA\n");
-    mta_size = E1000_MC_TBL_SIZE;
-    for (i = 0; i < mta_size; i++) {
-        E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
-        /* use write flush to prevent Memory Write Block (MWB) from
-         * occuring when accessing our register space */
-        E1000_WRITE_FLUSH();
-    }
-
-    /* Set the PCI priority bit correctly in the CTRL register.  This
-     * determines if the adapter gives priority to receives, or if it
-     * gives equal priority to transmits and receives.  Valid only on
-     * 82542 and 82543 silicon.
-     */
-    if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
-        ctrl = er32(CTRL);
-        ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
-    }
-
-    switch (hw->mac_type) {
-    case e1000_82545_rev_3:
-    case e1000_82546_rev_3:
-        break;
-    default:
-        /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
-       if (hw->bus_type == e1000_bus_type_pcix && e1000_pcix_get_mmrbc(hw) > 2048)
-               e1000_pcix_set_mmrbc(hw, 2048);
-       break;
-    }
-
-    /* Call a subroutine to configure the link and setup flow control. */
-    ret_val = e1000_setup_link(hw);
-
-    /* Set the transmit descriptor write-back policy */
-    if (hw->mac_type > e1000_82544) {
-        ctrl = er32(TXDCTL);
-        ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
-        ew32(TXDCTL, ctrl);
-    }
-
-    /* Clear all of the statistics registers (clear on read).  It is
-     * important that we do this after we have tried to establish link
-     * because the symbol error count will increment wildly if there
-     * is no link.
-     */
-    e1000_clear_hw_cntrs(hw);
-
-    if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
-        hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
-        ctrl_ext = er32(CTRL_EXT);
-        /* Relaxed ordering must be disabled to avoid a parity
-         * error crash in a PCI slot. */
-        ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
-        ew32(CTRL_EXT, ctrl_ext);
-    }
-
-    return ret_val;
+       u32 ctrl;
+       u32 i;
+       s32 ret_val;
+       u32 mta_size;
+       u32 ctrl_ext;
+
+       DEBUGFUNC("e1000_init_hw");
+
+       /* Initialize Identification LED */
+       ret_val = e1000_id_led_init(hw);
+       if (ret_val) {
+               DEBUGOUT("Error Initializing Identification LED\n");
+               return ret_val;
+       }
+
+       /* Set the media type and TBI compatibility */
+       e1000_set_media_type(hw);
+
+       /* Disabling VLAN filtering. */
+       DEBUGOUT("Initializing the IEEE VLAN\n");
+       if (hw->mac_type < e1000_82545_rev_3)
+               ew32(VET, 0);
+       e1000_clear_vfta(hw);
+
+       /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
+       if (hw->mac_type == e1000_82542_rev2_0) {
+               DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
+               e1000_pci_clear_mwi(hw);
+               ew32(RCTL, E1000_RCTL_RST);
+               E1000_WRITE_FLUSH();
+               msleep(5);
+       }
+
+       /* Setup the receive address. This involves initializing all of the Receive
+        * Address Registers (RARs 0 - 15).
+        */
+       e1000_init_rx_addrs(hw);
+
+       /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
+       if (hw->mac_type == e1000_82542_rev2_0) {
+               ew32(RCTL, 0);
+               E1000_WRITE_FLUSH();
+               msleep(1);
+               if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
+                       e1000_pci_set_mwi(hw);
+       }
+
+       /* Zero out the Multicast HASH table */
+       DEBUGOUT("Zeroing the MTA\n");
+       mta_size = E1000_MC_TBL_SIZE;
+       for (i = 0; i < mta_size; i++) {
+               E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
+               /* use write flush to prevent Memory Write Block (MWB) from
+                * occurring when accessing our register space */
+               E1000_WRITE_FLUSH();
+       }
+
+       /* Set the PCI priority bit correctly in the CTRL register.  This
+        * determines if the adapter gives priority to receives, or if it
+        * gives equal priority to transmits and receives.  Valid only on
+        * 82542 and 82543 silicon.
+        */
+       if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
+               ctrl = er32(CTRL);
+               ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
+       }
+
+       switch (hw->mac_type) {
+       case e1000_82545_rev_3:
+       case e1000_82546_rev_3:
+               break;
+       default:
+               /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
+               if (hw->bus_type == e1000_bus_type_pcix
+                   && e1000_pcix_get_mmrbc(hw) > 2048)
+                       e1000_pcix_set_mmrbc(hw, 2048);
+               break;
+       }
+
+       /* Call a subroutine to configure the link and setup flow control. */
+       ret_val = e1000_setup_link(hw);
+
+       /* Set the transmit descriptor write-back policy */
+       if (hw->mac_type > e1000_82544) {
+               ctrl = er32(TXDCTL);
+               ctrl =
+                   (ctrl & ~E1000_TXDCTL_WTHRESH) |
+                   E1000_TXDCTL_FULL_TX_DESC_WB;
+               ew32(TXDCTL, ctrl);
+       }
+
+       /* Clear all of the statistics registers (clear on read).  It is
+        * important that we do this after we have tried to establish link
+        * because the symbol error count will increment wildly if there
+        * is no link.
+        */
+       e1000_clear_hw_cntrs(hw);
+
+       if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
+           hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
+               ctrl_ext = er32(CTRL_EXT);
+               /* Relaxed ordering must be disabled to avoid a parity
+                * error crash in a PCI slot. */
+               ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
+               ew32(CTRL_EXT, ctrl_ext);
+       }
+
+       return ret_val;
 }
 
-/******************************************************************************
- * Adjust SERDES output amplitude based on EEPROM setting.
- *
- * hw - Struct containing variables accessed by shared code.
- *****************************************************************************/
+/**
+ * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting.
+ * @hw: Struct containing variables accessed by shared code.
+ */
 static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
 {
-    u16 eeprom_data;
-    s32  ret_val;
-
-    DEBUGFUNC("e1000_adjust_serdes_amplitude");
-
-    if (hw->media_type != e1000_media_type_internal_serdes)
-        return E1000_SUCCESS;
-
-    switch (hw->mac_type) {
-    case e1000_82545_rev_3:
-    case e1000_82546_rev_3:
-        break;
-    default:
-        return E1000_SUCCESS;
-    }
-
-    ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
-    if (ret_val) {
-        return ret_val;
-    }
-
-    if (eeprom_data != EEPROM_RESERVED_WORD) {
-        /* Adjust SERDES output amplitude only. */
-        eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
-        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
-        if (ret_val)
-            return ret_val;
-    }
-
-    return E1000_SUCCESS;
+       u16 eeprom_data;
+       s32 ret_val;
+
+       DEBUGFUNC("e1000_adjust_serdes_amplitude");
+
+       if (hw->media_type != e1000_media_type_internal_serdes)
+               return E1000_SUCCESS;
+
+       switch (hw->mac_type) {
+       case e1000_82545_rev_3:
+       case e1000_82546_rev_3:
+               break;
+       default:
+               return E1000_SUCCESS;
+       }
+
+       ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
+                                   &eeprom_data);
+       if (ret_val) {
+               return ret_val;
+       }
+
+       if (eeprom_data != EEPROM_RESERVED_WORD) {
+               /* Adjust SERDES output amplitude only. */
+               eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
+               ret_val =
+                   e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
+               if (ret_val)
+                       return ret_val;
+       }
+
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Configures flow control and link settings.
- *
- * hw - Struct containing variables accessed by shared code
+/**
+ * e1000_setup_link - Configures flow control and link settings.
+ * @hw: Struct containing variables accessed by shared code
  *
- * Determines which flow control settings to use. Calls the apropriate media-
+ * Determines which flow control settings to use. Calls the appropriate media-
  * specific link configuration function. Configures the flow control settings.
  * Assuming the adapter has a valid link partner, a valid link should be
  * established. Assumes the hardware has previously been reset and the
  * transmitter and receiver are not enabled.
- *****************************************************************************/
+ */
 s32 e1000_setup_link(struct e1000_hw *hw)
 {
-    u32 ctrl_ext;
-    s32 ret_val;
-    u16 eeprom_data;
-
-    DEBUGFUNC("e1000_setup_link");
-
-    /* Read and store word 0x0F of the EEPROM. This word contains bits
-     * that determine the hardware's default PAUSE (flow control) mode,
-     * a bit that determines whether the HW defaults to enabling or
-     * disabling auto-negotiation, and the direction of the
-     * SW defined pins. If there is no SW over-ride of the flow
-     * control setting, then the variable hw->fc will
-     * be initialized based on a value in the EEPROM.
-     */
-    if (hw->fc == E1000_FC_DEFAULT) {
-        ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
-                                    1, &eeprom_data);
-        if (ret_val) {
-            DEBUGOUT("EEPROM Read Error\n");
-            return -E1000_ERR_EEPROM;
-        }
-        if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
-            hw->fc = E1000_FC_NONE;
-        else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
-                 EEPROM_WORD0F_ASM_DIR)
-            hw->fc = E1000_FC_TX_PAUSE;
-        else
-            hw->fc = E1000_FC_FULL;
-    }
-
-    /* We want to save off the original Flow Control configuration just
-     * in case we get disconnected and then reconnected into a different
-     * hub or switch with different Flow Control capabilities.
-     */
-    if (hw->mac_type == e1000_82542_rev2_0)
-        hw->fc &= (~E1000_FC_TX_PAUSE);
-
-    if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
-        hw->fc &= (~E1000_FC_RX_PAUSE);
-
-    hw->original_fc = hw->fc;
-
-    DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
-
-    /* Take the 4 bits from EEPROM word 0x0F that determine the initial
-     * polarity value for the SW controlled pins, and setup the
-     * Extended Device Control reg with that info.
-     * This is needed because one of the SW controlled pins is used for
-     * signal detection.  So this should be done before e1000_setup_pcs_link()
-     * or e1000_phy_setup() is called.
-     */
-    if (hw->mac_type == e1000_82543) {
-        ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
-                                    1, &eeprom_data);
-        if (ret_val) {
-            DEBUGOUT("EEPROM Read Error\n");
-            return -E1000_ERR_EEPROM;
-        }
-        ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
-                    SWDPIO__EXT_SHIFT);
-        ew32(CTRL_EXT, ctrl_ext);
-    }
-
-    /* Call the necessary subroutine to configure the link. */
-    ret_val = (hw->media_type == e1000_media_type_copper) ?
-              e1000_setup_copper_link(hw) :
-              e1000_setup_fiber_serdes_link(hw);
-
-    /* Initialize the flow control address, type, and PAUSE timer
-     * registers to their default values.  This is done even if flow
-     * control is disabled, because it does not hurt anything to
-     * initialize these registers.
-     */
-    DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
-
-    ew32(FCT, FLOW_CONTROL_TYPE);
-    ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
-    ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
-
-    ew32(FCTTV, hw->fc_pause_time);
-
-    /* Set the flow control receive threshold registers.  Normally,
-     * these registers will be set to a default threshold that may be
-     * adjusted later by the driver's runtime code.  However, if the
-     * ability to transmit pause frames in not enabled, then these
-     * registers will be set to 0.
-     */
-    if (!(hw->fc & E1000_FC_TX_PAUSE)) {
-        ew32(FCRTL, 0);
-        ew32(FCRTH, 0);
-    } else {
-        /* We need to set up the Receive Threshold high and low water marks
-         * as well as (optionally) enabling the transmission of XON frames.
-         */
-        if (hw->fc_send_xon) {
-            ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
-            ew32(FCRTH, hw->fc_high_water);
-        } else {
-            ew32(FCRTL, hw->fc_low_water);
-            ew32(FCRTH, hw->fc_high_water);
-        }
-    }
-    return ret_val;
-}
+       u32 ctrl_ext;
+       s32 ret_val;
+       u16 eeprom_data;
+
+       DEBUGFUNC("e1000_setup_link");
+
+       /* Read and store word 0x0F of the EEPROM. This word contains bits
+        * that determine the hardware's default PAUSE (flow control) mode,
+        * a bit that determines whether the HW defaults to enabling or
+        * disabling auto-negotiation, and the direction of the
+        * SW defined pins. If there is no SW over-ride of the flow
+        * control setting, then the variable hw->fc will
+        * be initialized based on a value in the EEPROM.
+        */
+       if (hw->fc == E1000_FC_DEFAULT) {
+               ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
+                                           1, &eeprom_data);
+               if (ret_val) {
+                       DEBUGOUT("EEPROM Read Error\n");
+                       return -E1000_ERR_EEPROM;
+               }
+               if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
+                       hw->fc = E1000_FC_NONE;
+               else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
+                        EEPROM_WORD0F_ASM_DIR)
+                       hw->fc = E1000_FC_TX_PAUSE;
+               else
+                       hw->fc = E1000_FC_FULL;
+       }
 
-/******************************************************************************
- * Sets up link for a fiber based or serdes based adapter
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Manipulates Physical Coding Sublayer functions in order to configure
- * link. Assumes the hardware has been previously reset and the transmitter
- * and receiver are not enabled.
- *****************************************************************************/
-static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
-{
-    u32 ctrl;
-    u32 status;
-    u32 txcw = 0;
-    u32 i;
-    u32 signal = 0;
-    s32 ret_val;
-
-    DEBUGFUNC("e1000_setup_fiber_serdes_link");
-
-    /* On adapters with a MAC newer than 82544, SWDP 1 will be
-     * set when the optics detect a signal. On older adapters, it will be
-     * cleared when there is a signal.  This applies to fiber media only.
-     * If we're on serdes media, adjust the output amplitude to value
-     * set in the EEPROM.
-     */
-    ctrl = er32(CTRL);
-    if (hw->media_type == e1000_media_type_fiber)
-        signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
-
-    ret_val = e1000_adjust_serdes_amplitude(hw);
-    if (ret_val)
-        return ret_val;
-
-    /* Take the link out of reset */
-    ctrl &= ~(E1000_CTRL_LRST);
-
-    /* Adjust VCO speed to improve BER performance */
-    ret_val = e1000_set_vco_speed(hw);
-    if (ret_val)
-        return ret_val;
-
-    e1000_config_collision_dist(hw);
-
-    /* Check for a software override of the flow control settings, and setup
-     * the device accordingly.  If auto-negotiation is enabled, then software
-     * will have to set the "PAUSE" bits to the correct value in the Tranmsit
-     * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
-     * auto-negotiation is disabled, then software will have to manually
-     * configure the two flow control enable bits in the CTRL register.
-     *
-     * The possible values of the "fc" parameter are:
-     *      0:  Flow control is completely disabled
-     *      1:  Rx flow control is enabled (we can receive pause frames, but
-     *          not send pause frames).
-     *      2:  Tx flow control is enabled (we can send pause frames but we do
-     *          not support receiving pause frames).
-     *      3:  Both Rx and TX flow control (symmetric) are enabled.
-     */
-    switch (hw->fc) {
-    case E1000_FC_NONE:
-        /* Flow control is completely disabled by a software over-ride. */
-        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
-        break;
-    case E1000_FC_RX_PAUSE:
-        /* RX Flow control is enabled and TX Flow control is disabled by a
-         * software over-ride. Since there really isn't a way to advertise
-         * that we are capable of RX Pause ONLY, we will advertise that we
-         * support both symmetric and asymmetric RX PAUSE. Later, we will
-         *  disable the adapter's ability to send PAUSE frames.
-         */
-        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
-        break;
-    case E1000_FC_TX_PAUSE:
-        /* TX Flow control is enabled, and RX Flow control is disabled, by a
-         * software over-ride.
-         */
-        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
-        break;
-    case E1000_FC_FULL:
-        /* Flow control (both RX and TX) is enabled by a software over-ride. */
-        txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
-        break;
-    default:
-        DEBUGOUT("Flow control param set incorrectly\n");
-        return -E1000_ERR_CONFIG;
-        break;
-    }
-
-    /* Since auto-negotiation is enabled, take the link out of reset (the link
-     * will be in reset, because we previously reset the chip). This will
-     * restart auto-negotiation.  If auto-neogtiation is successful then the
-     * link-up status bit will be set and the flow control enable bits (RFCE
-     * and TFCE) will be set according to their negotiated value.
-     */
-    DEBUGOUT("Auto-negotiation enabled\n");
-
-    ew32(TXCW, txcw);
-    ew32(CTRL, ctrl);
-    E1000_WRITE_FLUSH();
-
-    hw->txcw = txcw;
-    msleep(1);
-
-    /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
-     * indication in the Device Status Register.  Time-out if a link isn't
-     * seen in 500 milliseconds seconds (Auto-negotiation should complete in
-     * less than 500 milliseconds even if the other end is doing it in SW).
-     * For internal serdes, we just assume a signal is present, then poll.
-     */
-    if (hw->media_type == e1000_media_type_internal_serdes ||
-       (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
-        DEBUGOUT("Looking for Link\n");
-        for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
-            msleep(10);
-            status = er32(STATUS);
-            if (status & E1000_STATUS_LU) break;
-        }
-        if (i == (LINK_UP_TIMEOUT / 10)) {
-            DEBUGOUT("Never got a valid link from auto-neg!!!\n");
-            hw->autoneg_failed = 1;
-            /* AutoNeg failed to achieve a link, so we'll call
-             * e1000_check_for_link. This routine will force the link up if
-             * we detect a signal. This will allow us to communicate with
-             * non-autonegotiating link partners.
-             */
-            ret_val = e1000_check_for_link(hw);
-            if (ret_val) {
-                DEBUGOUT("Error while checking for link\n");
-                return ret_val;
-            }
-            hw->autoneg_failed = 0;
-        } else {
-            hw->autoneg_failed = 0;
-            DEBUGOUT("Valid Link Found\n");
-        }
-    } else {
-        DEBUGOUT("No Signal Detected\n");
-    }
-    return E1000_SUCCESS;
-}
+       /* We want to save off the original Flow Control configuration just
+        * in case we get disconnected and then reconnected into a different
+        * hub or switch with different Flow Control capabilities.
+        */
+       if (hw->mac_type == e1000_82542_rev2_0)
+               hw->fc &= (~E1000_FC_TX_PAUSE);
 
-/******************************************************************************
-* Make sure we have a valid PHY and change PHY mode before link setup.
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
-{
-    u32 ctrl;
-    s32 ret_val;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_copper_link_preconfig");
-
-    ctrl = er32(CTRL);
-    /* With 82543, we need to force speed and duplex on the MAC equal to what
-     * the PHY speed and duplex configuration is. In addition, we need to
-     * perform a hardware reset on the PHY to take it out of reset.
-     */
-    if (hw->mac_type > e1000_82543) {
-        ctrl |= E1000_CTRL_SLU;
-        ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
-        ew32(CTRL, ctrl);
-    } else {
-        ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
-        ew32(CTRL, ctrl);
-        ret_val = e1000_phy_hw_reset(hw);
-        if (ret_val)
-            return ret_val;
-    }
-
-    /* Make sure we have a valid PHY */
-    ret_val = e1000_detect_gig_phy(hw);
-    if (ret_val) {
-        DEBUGOUT("Error, did not detect valid phy.\n");
-        return ret_val;
-    }
-    DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
-
-    /* Set PHY to class A mode (if necessary) */
-    ret_val = e1000_set_phy_mode(hw);
-    if (ret_val)
-        return ret_val;
-
-    if ((hw->mac_type == e1000_82545_rev_3) ||
-       (hw->mac_type == e1000_82546_rev_3)) {
-        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
-        phy_data |= 0x00000008;
-        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
-    }
-
-    if (hw->mac_type <= e1000_82543 ||
-        hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
-        hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
-        hw->phy_reset_disable = false;
-
-   return E1000_SUCCESS;
-}
+       if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
+               hw->fc &= (~E1000_FC_RX_PAUSE);
 
+       hw->original_fc = hw->fc;
 
-/********************************************************************
-* Copper link setup for e1000_phy_igp series.
-*
-* hw - Struct containing variables accessed by shared code
-*********************************************************************/
-static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
-{
-    u32 led_ctrl;
-    s32 ret_val;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_copper_link_igp_setup");
-
-    if (hw->phy_reset_disable)
-        return E1000_SUCCESS;
-
-    ret_val = e1000_phy_reset(hw);
-    if (ret_val) {
-        DEBUGOUT("Error Resetting the PHY\n");
-        return ret_val;
-    }
-
-    /* Wait 15ms for MAC to configure PHY from eeprom settings */
-    msleep(15);
-    /* Configure activity LED after PHY reset */
-    led_ctrl = er32(LEDCTL);
-    led_ctrl &= IGP_ACTIVITY_LED_MASK;
-    led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
-    ew32(LEDCTL, led_ctrl);
-
-    /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
-    if (hw->phy_type == e1000_phy_igp) {
-        /* disable lplu d3 during driver init */
-        ret_val = e1000_set_d3_lplu_state(hw, false);
-        if (ret_val) {
-            DEBUGOUT("Error Disabling LPLU D3\n");
-            return ret_val;
-        }
-    }
-
-    /* Configure mdi-mdix settings */
-    ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
-    if (ret_val)
-        return ret_val;
-
-    if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
-        hw->dsp_config_state = e1000_dsp_config_disabled;
-        /* Force MDI for earlier revs of the IGP PHY */
-        phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
-        hw->mdix = 1;
-
-    } else {
-        hw->dsp_config_state = e1000_dsp_config_enabled;
-        phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
-
-        switch (hw->mdix) {
-        case 1:
-            phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
-            break;
-        case 2:
-            phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
-            break;
-        case 0:
-        default:
-            phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
-            break;
-        }
-    }
-    ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
-    if (ret_val)
-        return ret_val;
-
-    /* set auto-master slave resolution settings */
-    if (hw->autoneg) {
-        e1000_ms_type phy_ms_setting = hw->master_slave;
-
-        if (hw->ffe_config_state == e1000_ffe_config_active)
-            hw->ffe_config_state = e1000_ffe_config_enabled;
-
-        if (hw->dsp_config_state == e1000_dsp_config_activated)
-            hw->dsp_config_state = e1000_dsp_config_enabled;
-
-        /* when autonegotiation advertisment is only 1000Mbps then we
-          * should disable SmartSpeed and enable Auto MasterSlave
-          * resolution as hardware default. */
-        if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
-            /* Disable SmartSpeed */
-            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-                                         &phy_data);
-            if (ret_val)
-                return ret_val;
-            phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
-            ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-                                          phy_data);
-            if (ret_val)
-                return ret_val;
-            /* Set auto Master/Slave resolution process */
-            ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
-            if (ret_val)
-                return ret_val;
-            phy_data &= ~CR_1000T_MS_ENABLE;
-            ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
-            if (ret_val)
-                return ret_val;
-        }
-
-        ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        /* load defaults for future use */
-        hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
-                                        ((phy_data & CR_1000T_MS_VALUE) ?
-                                         e1000_ms_force_master :
-                                         e1000_ms_force_slave) :
-                                         e1000_ms_auto;
-
-        switch (phy_ms_setting) {
-        case e1000_ms_force_master:
-            phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
-            break;
-        case e1000_ms_force_slave:
-            phy_data |= CR_1000T_MS_ENABLE;
-            phy_data &= ~(CR_1000T_MS_VALUE);
-            break;
-        case e1000_ms_auto:
-            phy_data &= ~CR_1000T_MS_ENABLE;
-            default:
-            break;
-        }
-        ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
-        if (ret_val)
-            return ret_val;
-    }
-
-    return E1000_SUCCESS;
-}
+       DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
 
-/********************************************************************
-* Copper link setup for e1000_phy_m88 series.
-*
-* hw - Struct containing variables accessed by shared code
-*********************************************************************/
-static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
-{
-    s32 ret_val;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_copper_link_mgp_setup");
-
-    if (hw->phy_reset_disable)
-        return E1000_SUCCESS;
-
-    /* Enable CRS on TX. This must be set for half-duplex operation. */
-    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
-    if (ret_val)
-        return ret_val;
-
-    phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
-
-    /* Options:
-     *   MDI/MDI-X = 0 (default)
-     *   0 - Auto for all speeds
-     *   1 - MDI mode
-     *   2 - MDI-X mode
-     *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
-     */
-    phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
-
-    switch (hw->mdix) {
-    case 1:
-        phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
-        break;
-    case 2:
-        phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
-        break;
-    case 3:
-        phy_data |= M88E1000_PSCR_AUTO_X_1000T;
-        break;
-    case 0:
-    default:
-        phy_data |= M88E1000_PSCR_AUTO_X_MODE;
-        break;
-    }
-
-    /* Options:
-     *   disable_polarity_correction = 0 (default)
-     *       Automatic Correction for Reversed Cable Polarity
-     *   0 - Disabled
-     *   1 - Enabled
-     */
-    phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
-    if (hw->disable_polarity_correction == 1)
-        phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
-    if (ret_val)
-        return ret_val;
-
-    if (hw->phy_revision < M88E1011_I_REV_4) {
-        /* Force TX_CLK in the Extended PHY Specific Control Register
-         * to 25MHz clock.
-         */
-        ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        phy_data |= M88E1000_EPSCR_TX_CLK_25;
-
-        if ((hw->phy_revision == E1000_REVISION_2) &&
-            (hw->phy_id == M88E1111_I_PHY_ID)) {
-            /* Vidalia Phy, set the downshift counter to 5x */
-            phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
-            phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
-            ret_val = e1000_write_phy_reg(hw,
-                                        M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
-            if (ret_val)
-                return ret_val;
-        } else {
-            /* Configure Master and Slave downshift values */
-            phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
-                              M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
-            phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
-                             M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
-            ret_val = e1000_write_phy_reg(hw,
-                                        M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
-            if (ret_val)
-               return ret_val;
-        }
-    }
-
-    /* SW Reset the PHY so all changes take effect */
-    ret_val = e1000_phy_reset(hw);
-    if (ret_val) {
-        DEBUGOUT("Error Resetting the PHY\n");
-        return ret_val;
-    }
-
-   return E1000_SUCCESS;
-}
+       /* Take the 4 bits from EEPROM word 0x0F that determine the initial
+        * polarity value for the SW controlled pins, and setup the
+        * Extended Device Control reg with that info.
+        * This is needed because one of the SW controlled pins is used for
+        * signal detection.  So this should be done before e1000_setup_pcs_link()
+        * or e1000_phy_setup() is called.
+        */
+       if (hw->mac_type == e1000_82543) {
+               ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
+                                           1, &eeprom_data);
+               if (ret_val) {
+                       DEBUGOUT("EEPROM Read Error\n");
+                       return -E1000_ERR_EEPROM;
+               }
+               ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
+                           SWDPIO__EXT_SHIFT);
+               ew32(CTRL_EXT, ctrl_ext);
+       }
 
-/********************************************************************
-* Setup auto-negotiation and flow control advertisements,
-* and then perform auto-negotiation.
-*
-* hw - Struct containing variables accessed by shared code
-*********************************************************************/
-static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
-{
-    s32 ret_val;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_copper_link_autoneg");
-
-    /* Perform some bounds checking on the hw->autoneg_advertised
-     * parameter.  If this variable is zero, then set it to the default.
-     */
-    hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
-
-    /* If autoneg_advertised is zero, we assume it was not defaulted
-     * by the calling code so we set to advertise full capability.
-     */
-    if (hw->autoneg_advertised == 0)
-        hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
-
-    DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
-    ret_val = e1000_phy_setup_autoneg(hw);
-    if (ret_val) {
-        DEBUGOUT("Error Setting up Auto-Negotiation\n");
-        return ret_val;
-    }
-    DEBUGOUT("Restarting Auto-Neg\n");
-
-    /* Restart auto-negotiation by setting the Auto Neg Enable bit and
-     * the Auto Neg Restart bit in the PHY control register.
-     */
-    ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
-    if (ret_val)
-        return ret_val;
-
-    phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
-    ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
-    if (ret_val)
-        return ret_val;
-
-    /* Does the user want to wait for Auto-Neg to complete here, or
-     * check at a later time (for example, callback routine).
-     */
-    if (hw->wait_autoneg_complete) {
-        ret_val = e1000_wait_autoneg(hw);
-        if (ret_val) {
-            DEBUGOUT("Error while waiting for autoneg to complete\n");
-            return ret_val;
-        }
-    }
-
-    hw->get_link_status = true;
-
-    return E1000_SUCCESS;
-}
+       /* Call the necessary subroutine to configure the link. */
+       ret_val = (hw->media_type == e1000_media_type_copper) ?
+           e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);
 
-/******************************************************************************
-* Config the MAC and the PHY after link is up.
-*   1) Set up the MAC to the current PHY speed/duplex
-*      if we are on 82543.  If we
-*      are on newer silicon, we only need to configure
-*      collision distance in the Transmit Control Register.
-*   2) Set up flow control on the MAC to that established with
-*      the link partner.
-*   3) Config DSP to improve Gigabit link quality for some PHY revisions.
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
-{
-    s32 ret_val;
-    DEBUGFUNC("e1000_copper_link_postconfig");
-
-    if (hw->mac_type >= e1000_82544) {
-        e1000_config_collision_dist(hw);
-    } else {
-        ret_val = e1000_config_mac_to_phy(hw);
-        if (ret_val) {
-            DEBUGOUT("Error configuring MAC to PHY settings\n");
-            return ret_val;
-        }
-    }
-    ret_val = e1000_config_fc_after_link_up(hw);
-    if (ret_val) {
-        DEBUGOUT("Error Configuring Flow Control\n");
-        return ret_val;
-    }
-
-    /* Config DSP to improve Giga link quality */
-    if (hw->phy_type == e1000_phy_igp) {
-        ret_val = e1000_config_dsp_after_link_change(hw, true);
-        if (ret_val) {
-            DEBUGOUT("Error Configuring DSP after link up\n");
-            return ret_val;
-        }
-    }
-
-    return E1000_SUCCESS;
-}
+       /* Initialize the flow control address, type, and PAUSE timer
+        * registers to their default values.  This is done even if flow
+        * control is disabled, because it does not hurt anything to
+        * initialize these registers.
+        */
+       DEBUGOUT
+           ("Initializing the Flow Control address, type and timer regs\n");
 
-/******************************************************************************
-* Detects which PHY is present and setup the speed and duplex
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static s32 e1000_setup_copper_link(struct e1000_hw *hw)
-{
-    s32 ret_val;
-    u16 i;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_setup_copper_link");
-
-    /* Check if it is a valid PHY and set PHY mode if necessary. */
-    ret_val = e1000_copper_link_preconfig(hw);
-    if (ret_val)
-        return ret_val;
-
-    if (hw->phy_type == e1000_phy_igp) {
-        ret_val = e1000_copper_link_igp_setup(hw);
-        if (ret_val)
-            return ret_val;
-    } else if (hw->phy_type == e1000_phy_m88) {
-        ret_val = e1000_copper_link_mgp_setup(hw);
-        if (ret_val)
-            return ret_val;
-    }
-
-    if (hw->autoneg) {
-        /* Setup autoneg and flow control advertisement
-          * and perform autonegotiation */
-        ret_val = e1000_copper_link_autoneg(hw);
-        if (ret_val)
-            return ret_val;
-    } else {
-        /* PHY will be set to 10H, 10F, 100H,or 100F
-          * depending on value from forced_speed_duplex. */
-        DEBUGOUT("Forcing speed and duplex\n");
-        ret_val = e1000_phy_force_speed_duplex(hw);
-        if (ret_val) {
-            DEBUGOUT("Error Forcing Speed and Duplex\n");
-            return ret_val;
-        }
-    }
-
-    /* Check link status. Wait up to 100 microseconds for link to become
-     * valid.
-     */
-    for (i = 0; i < 10; i++) {
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-        if (ret_val)
-            return ret_val;
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        if (phy_data & MII_SR_LINK_STATUS) {
-            /* Config the MAC and PHY after link is up */
-            ret_val = e1000_copper_link_postconfig(hw);
-            if (ret_val)
-                return ret_val;
-
-            DEBUGOUT("Valid link established!!!\n");
-            return E1000_SUCCESS;
-        }
-        udelay(10);
-    }
-
-    DEBUGOUT("Unable to establish link!!!\n");
-    return E1000_SUCCESS;
-}
+       ew32(FCT, FLOW_CONTROL_TYPE);
+       ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
+       ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
 
-/******************************************************************************
-* Configures PHY autoneg and flow control advertisement settings
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
-{
-    s32 ret_val;
-    u16 mii_autoneg_adv_reg;
-    u16 mii_1000t_ctrl_reg;
-
-    DEBUGFUNC("e1000_phy_setup_autoneg");
-
-    /* Read the MII Auto-Neg Advertisement Register (Address 4). */
-    ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
-    if (ret_val)
-        return ret_val;
-
-    /* Read the MII 1000Base-T Control Register (Address 9). */
-    ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
-    if (ret_val)
-        return ret_val;
-
-    /* Need to parse both autoneg_advertised and fc and set up
-     * the appropriate PHY registers.  First we will parse for
-     * autoneg_advertised software override.  Since we can advertise
-     * a plethora of combinations, we need to check each bit
-     * individually.
-     */
-
-    /* First we clear all the 10/100 mb speed bits in the Auto-Neg
-     * Advertisement Register (Address 4) and the 1000 mb speed bits in
-     * the  1000Base-T Control Register (Address 9).
-     */
-    mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
-    mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
-
-    DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
-
-    /* Do we want to advertise 10 Mb Half Duplex? */
-    if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
-        DEBUGOUT("Advertise 10mb Half duplex\n");
-        mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
-    }
-
-    /* Do we want to advertise 10 Mb Full Duplex? */
-    if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
-        DEBUGOUT("Advertise 10mb Full duplex\n");
-        mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
-    }
-
-    /* Do we want to advertise 100 Mb Half Duplex? */
-    if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
-        DEBUGOUT("Advertise 100mb Half duplex\n");
-        mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
-    }
-
-    /* Do we want to advertise 100 Mb Full Duplex? */
-    if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
-        DEBUGOUT("Advertise 100mb Full duplex\n");
-        mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
-    }
-
-    /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
-    if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
-        DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
-    }
-
-    /* Do we want to advertise 1000 Mb Full Duplex? */
-    if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
-        DEBUGOUT("Advertise 1000mb Full duplex\n");
-        mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
-    }
-
-    /* Check for a software override of the flow control settings, and
-     * setup the PHY advertisement registers accordingly.  If
-     * auto-negotiation is enabled, then software will have to set the
-     * "PAUSE" bits to the correct value in the Auto-Negotiation
-     * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
-     *
-     * The possible values of the "fc" parameter are:
-     *      0:  Flow control is completely disabled
-     *      1:  Rx flow control is enabled (we can receive pause frames
-     *          but not send pause frames).
-     *      2:  Tx flow control is enabled (we can send pause frames
-     *          but we do not support receiving pause frames).
-     *      3:  Both Rx and TX flow control (symmetric) are enabled.
-     *  other:  No software override.  The flow control configuration
-     *          in the EEPROM is used.
-     */
-    switch (hw->fc) {
-    case E1000_FC_NONE: /* 0 */
-        /* Flow control (RX & TX) is completely disabled by a
-         * software over-ride.
-         */
-        mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
-        break;
-    case E1000_FC_RX_PAUSE: /* 1 */
-        /* RX Flow control is enabled, and TX Flow control is
-         * disabled, by a software over-ride.
-         */
-        /* Since there really isn't a way to advertise that we are
-         * capable of RX Pause ONLY, we will advertise that we
-         * support both symmetric and asymmetric RX PAUSE.  Later
-         * (in e1000_config_fc_after_link_up) we will disable the
-         *hw's ability to send PAUSE frames.
-         */
-        mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
-        break;
-    case E1000_FC_TX_PAUSE: /* 2 */
-        /* TX Flow control is enabled, and RX Flow control is
-         * disabled, by a software over-ride.
-         */
-        mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
-        mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
-        break;
-    case E1000_FC_FULL: /* 3 */
-        /* Flow control (both RX and TX) is enabled by a software
-         * over-ride.
-         */
-        mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
-        break;
-    default:
-        DEBUGOUT("Flow control param set incorrectly\n");
-        return -E1000_ERR_CONFIG;
-    }
-
-    ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
-    if (ret_val)
-        return ret_val;
-
-    DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
-
-    ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
-    if (ret_val)
-        return ret_val;
-
-    return E1000_SUCCESS;
-}
+       ew32(FCTTV, hw->fc_pause_time);
 
-/******************************************************************************
-* Force PHY speed and duplex settings to hw->forced_speed_duplex
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
-{
-    u32 ctrl;
-    s32 ret_val;
-    u16 mii_ctrl_reg;
-    u16 mii_status_reg;
-    u16 phy_data;
-    u16 i;
-
-    DEBUGFUNC("e1000_phy_force_speed_duplex");
-
-    /* Turn off Flow control if we are forcing speed and duplex. */
-    hw->fc = E1000_FC_NONE;
-
-    DEBUGOUT1("hw->fc = %d\n", hw->fc);
-
-    /* Read the Device Control Register. */
-    ctrl = er32(CTRL);
-
-    /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
-    ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
-    ctrl &= ~(DEVICE_SPEED_MASK);
-
-    /* Clear the Auto Speed Detect Enable bit. */
-    ctrl &= ~E1000_CTRL_ASDE;
-
-    /* Read the MII Control Register. */
-    ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
-    if (ret_val)
-        return ret_val;
-
-    /* We need to disable autoneg in order to force link and duplex. */
-
-    mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
-
-    /* Are we forcing Full or Half Duplex? */
-    if (hw->forced_speed_duplex == e1000_100_full ||
-        hw->forced_speed_duplex == e1000_10_full) {
-        /* We want to force full duplex so we SET the full duplex bits in the
-         * Device and MII Control Registers.
-         */
-        ctrl |= E1000_CTRL_FD;
-        mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
-        DEBUGOUT("Full Duplex\n");
-    } else {
-        /* We want to force half duplex so we CLEAR the full duplex bits in
-         * the Device and MII Control Registers.
-         */
-        ctrl &= ~E1000_CTRL_FD;
-        mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
-        DEBUGOUT("Half Duplex\n");
-    }
-
-    /* Are we forcing 100Mbps??? */
-    if (hw->forced_speed_duplex == e1000_100_full ||
-       hw->forced_speed_duplex == e1000_100_half) {
-        /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
-        ctrl |= E1000_CTRL_SPD_100;
-        mii_ctrl_reg |= MII_CR_SPEED_100;
-        mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
-        DEBUGOUT("Forcing 100mb ");
-    } else {
-        /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
-        ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
-        mii_ctrl_reg |= MII_CR_SPEED_10;
-        mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
-        DEBUGOUT("Forcing 10mb ");
-    }
-
-    e1000_config_collision_dist(hw);
-
-    /* Write the configured values back to the Device Control Reg. */
-    ew32(CTRL, ctrl);
-
-    if (hw->phy_type == e1000_phy_m88) {
-        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
-         * forced whenever speed are duplex are forced.
-         */
-        phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
-        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
-        if (ret_val)
-            return ret_val;
-
-        DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
-
-        /* Need to reset the PHY or these changes will be ignored */
-        mii_ctrl_reg |= MII_CR_RESET;
-
-    } else {
-        /* Clear Auto-Crossover to force MDI manually.  IGP requires MDI
-         * forced whenever speed or duplex are forced.
-         */
-        ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
-        phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
-
-        ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
-        if (ret_val)
-            return ret_val;
-    }
-
-    /* Write back the modified PHY MII control register. */
-    ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
-    if (ret_val)
-        return ret_val;
-
-    udelay(1);
-
-    /* The wait_autoneg_complete flag may be a little misleading here.
-     * Since we are forcing speed and duplex, Auto-Neg is not enabled.
-     * But we do want to delay for a period while forcing only so we
-     * don't generate false No Link messages.  So we will wait here
-     * only if the user has set wait_autoneg_complete to 1, which is
-     * the default.
-     */
-    if (hw->wait_autoneg_complete) {
-        /* We will wait for autoneg to complete. */
-        DEBUGOUT("Waiting for forced speed/duplex link.\n");
-        mii_status_reg = 0;
-
-        /* We will wait for autoneg to complete or 4.5 seconds to expire. */
-        for (i = PHY_FORCE_TIME; i > 0; i--) {
-            /* Read the MII Status Register and wait for Auto-Neg Complete bit
-             * to be set.
-             */
-            ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-            if (ret_val)
-                return ret_val;
-
-            ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-            if (ret_val)
-                return ret_val;
-
-            if (mii_status_reg & MII_SR_LINK_STATUS) break;
-            msleep(100);
-        }
-        if ((i == 0) &&
-           (hw->phy_type == e1000_phy_m88)) {
-            /* We didn't get link.  Reset the DSP and wait again for link. */
-            ret_val = e1000_phy_reset_dsp(hw);
-            if (ret_val) {
-                DEBUGOUT("Error Resetting PHY DSP\n");
-                return ret_val;
-            }
-        }
-        /* This loop will early-out if the link condition has been met.  */
-        for (i = PHY_FORCE_TIME; i > 0; i--) {
-            if (mii_status_reg & MII_SR_LINK_STATUS) break;
-            msleep(100);
-            /* Read the MII Status Register and wait for Auto-Neg Complete bit
-             * to be set.
-             */
-            ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-            if (ret_val)
-                return ret_val;
-
-            ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-            if (ret_val)
-                return ret_val;
-        }
-    }
-
-    if (hw->phy_type == e1000_phy_m88) {
-        /* Because we reset the PHY above, we need to re-force TX_CLK in the
-         * Extended PHY Specific Control Register to 25MHz clock.  This value
-         * defaults back to a 2.5MHz clock when the PHY is reset.
-         */
-        ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        phy_data |= M88E1000_EPSCR_TX_CLK_25;
-        ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
-        if (ret_val)
-            return ret_val;
-
-        /* In addition, because of the s/w reset above, we need to enable CRS on
-         * TX.  This must be set for both full and half duplex operation.
-         */
-        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
-        ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
-        if (ret_val)
-            return ret_val;
-
-        if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
-            (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
-             hw->forced_speed_duplex == e1000_10_half)) {
-            ret_val = e1000_polarity_reversal_workaround(hw);
-            if (ret_val)
-                return ret_val;
-        }
-    }
-    return E1000_SUCCESS;
+       /* Set the flow control receive threshold registers.  Normally,
+        * these registers will be set to a default threshold that may be
+        * adjusted later by the driver's runtime code.  However, if the
+        * ability to transmit pause frames in not enabled, then these
+        * registers will be set to 0.
+        */
+       if (!(hw->fc & E1000_FC_TX_PAUSE)) {
+               ew32(FCRTL, 0);
+               ew32(FCRTH, 0);
+       } else {
+               /* We need to set up the Receive Threshold high and low water marks
+                * as well as (optionally) enabling the transmission of XON frames.
+                */
+               if (hw->fc_send_xon) {
+                       ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
+                       ew32(FCRTH, hw->fc_high_water);
+               } else {
+                       ew32(FCRTL, hw->fc_low_water);
+                       ew32(FCRTH, hw->fc_high_water);
+               }
+       }
+       return ret_val;
 }
 
-/******************************************************************************
-* Sets the collision distance in the Transmit Control register
-*
-* hw - Struct containing variables accessed by shared code
-*
-* Link should have been established previously. Reads the speed and duplex
-* information from the Device Status register.
-******************************************************************************/
-void e1000_config_collision_dist(struct e1000_hw *hw)
+/**
+ * e1000_setup_fiber_serdes_link - prepare fiber or serdes link
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Manipulates Physical Coding Sublayer functions in order to configure
+ * link. Assumes the hardware has been previously reset and the transmitter
+ * and receiver are not enabled.
+ */
+static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
 {
-    u32 tctl, coll_dist;
-
-    DEBUGFUNC("e1000_config_collision_dist");
+       u32 ctrl;
+       u32 status;
+       u32 txcw = 0;
+       u32 i;
+       u32 signal = 0;
+       s32 ret_val;
+
+       DEBUGFUNC("e1000_setup_fiber_serdes_link");
+
+       /* On adapters with a MAC newer than 82544, SWDP 1 will be
+        * set when the optics detect a signal. On older adapters, it will be
+        * cleared when there is a signal.  This applies to fiber media only.
+        * If we're on serdes media, adjust the output amplitude to value
+        * set in the EEPROM.
+        */
+       ctrl = er32(CTRL);
+       if (hw->media_type == e1000_media_type_fiber)
+               signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
+
+       ret_val = e1000_adjust_serdes_amplitude(hw);
+       if (ret_val)
+               return ret_val;
+
+       /* Take the link out of reset */
+       ctrl &= ~(E1000_CTRL_LRST);
+
+       /* Adjust VCO speed to improve BER performance */
+       ret_val = e1000_set_vco_speed(hw);
+       if (ret_val)
+               return ret_val;
+
+       e1000_config_collision_dist(hw);
+
+       /* Check for a software override of the flow control settings, and setup
+        * the device accordingly.  If auto-negotiation is enabled, then software
+        * will have to set the "PAUSE" bits to the correct value in the Tranmsit
+        * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
+        * auto-negotiation is disabled, then software will have to manually
+        * configure the two flow control enable bits in the CTRL register.
+        *
+        * The possible values of the "fc" parameter are:
+        *      0:  Flow control is completely disabled
+        *      1:  Rx flow control is enabled (we can receive pause frames, but
+        *          not send pause frames).
+        *      2:  Tx flow control is enabled (we can send pause frames but we do
+        *          not support receiving pause frames).
+        *      3:  Both Rx and TX flow control (symmetric) are enabled.
+        */
+       switch (hw->fc) {
+       case E1000_FC_NONE:
+               /* Flow control is completely disabled by a software over-ride. */
+               txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
+               break;
+       case E1000_FC_RX_PAUSE:
+               /* RX Flow control is enabled and TX Flow control is disabled by a
+                * software over-ride. Since there really isn't a way to advertise
+                * that we are capable of RX Pause ONLY, we will advertise that we
+                * support both symmetric and asymmetric RX PAUSE. Later, we will
+                *  disable the adapter's ability to send PAUSE frames.
+                */
+               txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
+               break;
+       case E1000_FC_TX_PAUSE:
+               /* TX Flow control is enabled, and RX Flow control is disabled, by a
+                * software over-ride.
+                */
+               txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
+               break;
+       case E1000_FC_FULL:
+               /* Flow control (both RX and TX) is enabled by a software over-ride. */
+               txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
+               break;
+       default:
+               DEBUGOUT("Flow control param set incorrectly\n");
+               return -E1000_ERR_CONFIG;
+               break;
+       }
 
-    if (hw->mac_type < e1000_82543)
-        coll_dist = E1000_COLLISION_DISTANCE_82542;
-    else
-        coll_dist = E1000_COLLISION_DISTANCE;
+       /* Since auto-negotiation is enabled, take the link out of reset (the link
+        * will be in reset, because we previously reset the chip). This will
+        * restart auto-negotiation.  If auto-negotiation is successful then the
+        * link-up status bit will be set and the flow control enable bits (RFCE
+        * and TFCE) will be set according to their negotiated value.
+        */
+       DEBUGOUT("Auto-negotiation enabled\n");
 
-    tctl = er32(TCTL);
+       ew32(TXCW, txcw);
+       ew32(CTRL, ctrl);
+       E1000_WRITE_FLUSH();
 
-    tctl &= ~E1000_TCTL_COLD;
-    tctl |= coll_dist << E1000_COLD_SHIFT;
+       hw->txcw = txcw;
+       msleep(1);
 
-    ew32(TCTL, tctl);
-    E1000_WRITE_FLUSH();
+       /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
+        * indication in the Device Status Register.  Time-out if a link isn't
+        * seen in 500 milliseconds seconds (Auto-negotiation should complete in
+        * less than 500 milliseconds even if the other end is doing it in SW).
+        * For internal serdes, we just assume a signal is present, then poll.
+        */
+       if (hw->media_type == e1000_media_type_internal_serdes ||
+           (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
+               DEBUGOUT("Looking for Link\n");
+               for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
+                       msleep(10);
+                       status = er32(STATUS);
+                       if (status & E1000_STATUS_LU)
+                               break;
+               }
+               if (i == (LINK_UP_TIMEOUT / 10)) {
+                       DEBUGOUT("Never got a valid link from auto-neg!!!\n");
+                       hw->autoneg_failed = 1;
+                       /* AutoNeg failed to achieve a link, so we'll call
+                        * e1000_check_for_link. This routine will force the link up if
+                        * we detect a signal. This will allow us to communicate with
+                        * non-autonegotiating link partners.
+                        */
+                       ret_val = e1000_check_for_link(hw);
+                       if (ret_val) {
+                               DEBUGOUT("Error while checking for link\n");
+                               return ret_val;
+                       }
+                       hw->autoneg_failed = 0;
+               } else {
+                       hw->autoneg_failed = 0;
+                       DEBUGOUT("Valid Link Found\n");
+               }
+       } else {
+               DEBUGOUT("No Signal Detected\n");
+       }
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
-* Sets MAC speed and duplex settings to reflect the those in the PHY
-*
-* hw - Struct containing variables accessed by shared code
-* mii_reg - data to write to the MII control register
-*
-* The contents of the PHY register containing the needed information need to
-* be passed in.
-******************************************************************************/
-static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
+/**
+ * e1000_copper_link_preconfig - early configuration for copper
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Make sure we have a valid PHY and change PHY mode before link setup.
+ */
+static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
 {
-    u32 ctrl;
-    s32 ret_val;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_config_mac_to_phy");
-
-    /* 82544 or newer MAC, Auto Speed Detection takes care of
-    * MAC speed/duplex configuration.*/
-    if (hw->mac_type >= e1000_82544)
-        return E1000_SUCCESS;
-
-    /* Read the Device Control Register and set the bits to Force Speed
-     * and Duplex.
-     */
-    ctrl = er32(CTRL);
-    ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
-    ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
-
-    /* Set up duplex in the Device Control and Transmit Control
-     * registers depending on negotiated values.
-     */
-    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
-    if (ret_val)
-        return ret_val;
-
-    if (phy_data & M88E1000_PSSR_DPLX)
-        ctrl |= E1000_CTRL_FD;
-    else
-        ctrl &= ~E1000_CTRL_FD;
-
-    e1000_config_collision_dist(hw);
-
-    /* Set up speed in the Device Control register depending on
-     * negotiated values.
-     */
-    if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
-        ctrl |= E1000_CTRL_SPD_1000;
-    else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
-        ctrl |= E1000_CTRL_SPD_100;
-
-    /* Write the configured values back to the Device Control Reg. */
-    ew32(CTRL, ctrl);
-    return E1000_SUCCESS;
+       u32 ctrl;
+       s32 ret_val;
+       u16 phy_data;
+
+       DEBUGFUNC("e1000_copper_link_preconfig");
+
+       ctrl = er32(CTRL);
+       /* With 82543, we need to force speed and duplex on the MAC equal to what
+        * the PHY speed and duplex configuration is. In addition, we need to
+        * perform a hardware reset on the PHY to take it out of reset.
+        */
+       if (hw->mac_type > e1000_82543) {
+               ctrl |= E1000_CTRL_SLU;
+               ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
+               ew32(CTRL, ctrl);
+       } else {
+               ctrl |=
+                   (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
+               ew32(CTRL, ctrl);
+               ret_val = e1000_phy_hw_reset(hw);
+               if (ret_val)
+                       return ret_val;
+       }
+
+       /* Make sure we have a valid PHY */
+       ret_val = e1000_detect_gig_phy(hw);
+       if (ret_val) {
+               DEBUGOUT("Error, did not detect valid phy.\n");
+               return ret_val;
+       }
+       DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
+
+       /* Set PHY to class A mode (if necessary) */
+       ret_val = e1000_set_phy_mode(hw);
+       if (ret_val)
+               return ret_val;
+
+       if ((hw->mac_type == e1000_82545_rev_3) ||
+           (hw->mac_type == e1000_82546_rev_3)) {
+               ret_val =
+                   e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+               phy_data |= 0x00000008;
+               ret_val =
+                   e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
+       }
+
+       if (hw->mac_type <= e1000_82543 ||
+           hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
+           hw->mac_type == e1000_82541_rev_2
+           || hw->mac_type == e1000_82547_rev_2)
+               hw->phy_reset_disable = false;
+
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Forces the MAC's flow control settings.
+/**
+ * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series.
+ * @hw: Struct containing variables accessed by shared code
+ */
+static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
+{
+       u32 led_ctrl;
+       s32 ret_val;
+       u16 phy_data;
+
+       DEBUGFUNC("e1000_copper_link_igp_setup");
+
+       if (hw->phy_reset_disable)
+               return E1000_SUCCESS;
+
+       ret_val = e1000_phy_reset(hw);
+       if (ret_val) {
+               DEBUGOUT("Error Resetting the PHY\n");
+               return ret_val;
+       }
+
+       /* Wait 15ms for MAC to configure PHY from eeprom settings */
+       msleep(15);
+       /* Configure activity LED after PHY reset */
+       led_ctrl = er32(LEDCTL);
+       led_ctrl &= IGP_ACTIVITY_LED_MASK;
+       led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
+       ew32(LEDCTL, led_ctrl);
+
+       /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
+       if (hw->phy_type == e1000_phy_igp) {
+               /* disable lplu d3 during driver init */
+               ret_val = e1000_set_d3_lplu_state(hw, false);
+               if (ret_val) {
+                       DEBUGOUT("Error Disabling LPLU D3\n");
+                       return ret_val;
+               }
+       }
+
+       /* Configure mdi-mdix settings */
+       ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
+       if (ret_val)
+               return ret_val;
+
+       if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
+               hw->dsp_config_state = e1000_dsp_config_disabled;
+               /* Force MDI for earlier revs of the IGP PHY */
+               phy_data &=
+                   ~(IGP01E1000_PSCR_AUTO_MDIX |
+                     IGP01E1000_PSCR_FORCE_MDI_MDIX);
+               hw->mdix = 1;
+
+       } else {
+               hw->dsp_config_state = e1000_dsp_config_enabled;
+               phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
+
+               switch (hw->mdix) {
+               case 1:
+                       phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
+                       break;
+               case 2:
+                       phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
+                       break;
+               case 0:
+               default:
+                       phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
+                       break;
+               }
+       }
+       ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
+       if (ret_val)
+               return ret_val;
+
+       /* set auto-master slave resolution settings */
+       if (hw->autoneg) {
+               e1000_ms_type phy_ms_setting = hw->master_slave;
+
+               if (hw->ffe_config_state == e1000_ffe_config_active)
+                       hw->ffe_config_state = e1000_ffe_config_enabled;
+
+               if (hw->dsp_config_state == e1000_dsp_config_activated)
+                       hw->dsp_config_state = e1000_dsp_config_enabled;
+
+               /* when autonegotiation advertisement is only 1000Mbps then we
+                * should disable SmartSpeed and enable Auto MasterSlave
+                * resolution as hardware default. */
+               if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
+                       /* Disable SmartSpeed */
+                       ret_val =
+                           e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                              &phy_data);
+                       if (ret_val)
+                               return ret_val;
+                       phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+                       ret_val =
+                           e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                               phy_data);
+                       if (ret_val)
+                               return ret_val;
+                       /* Set auto Master/Slave resolution process */
+                       ret_val =
+                           e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
+                       if (ret_val)
+                               return ret_val;
+                       phy_data &= ~CR_1000T_MS_ENABLE;
+                       ret_val =
+                           e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
+                       if (ret_val)
+                               return ret_val;
+               }
+
+               ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
+               if (ret_val)
+                       return ret_val;
+
+               /* load defaults for future use */
+               hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
+                   ((phy_data & CR_1000T_MS_VALUE) ?
+                    e1000_ms_force_master :
+                    e1000_ms_force_slave) : e1000_ms_auto;
+
+               switch (phy_ms_setting) {
+               case e1000_ms_force_master:
+                       phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
+                       break;
+               case e1000_ms_force_slave:
+                       phy_data |= CR_1000T_MS_ENABLE;
+                       phy_data &= ~(CR_1000T_MS_VALUE);
+                       break;
+               case e1000_ms_auto:
+                       phy_data &= ~CR_1000T_MS_ENABLE;
+               default:
+                       break;
+               }
+               ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
+               if (ret_val)
+                       return ret_val;
+       }
+
+       return E1000_SUCCESS;
+}
+
+/**
+ * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series.
+ * @hw: Struct containing variables accessed by shared code
+ */
+static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
+{
+       s32 ret_val;
+       u16 phy_data;
+
+       DEBUGFUNC("e1000_copper_link_mgp_setup");
+
+       if (hw->phy_reset_disable)
+               return E1000_SUCCESS;
+
+       /* Enable CRS on TX. This must be set for half-duplex operation. */
+       ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+       if (ret_val)
+               return ret_val;
+
+       phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
+
+       /* Options:
+        *   MDI/MDI-X = 0 (default)
+        *   0 - Auto for all speeds
+        *   1 - MDI mode
+        *   2 - MDI-X mode
+        *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
+        */
+       phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
+
+       switch (hw->mdix) {
+       case 1:
+               phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
+               break;
+       case 2:
+               phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
+               break;
+       case 3:
+               phy_data |= M88E1000_PSCR_AUTO_X_1000T;
+               break;
+       case 0:
+       default:
+               phy_data |= M88E1000_PSCR_AUTO_X_MODE;
+               break;
+       }
+
+       /* Options:
+        *   disable_polarity_correction = 0 (default)
+        *       Automatic Correction for Reversed Cable Polarity
+        *   0 - Disabled
+        *   1 - Enabled
+        */
+       phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
+       if (hw->disable_polarity_correction == 1)
+               phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
+       ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
+       if (ret_val)
+               return ret_val;
+
+       if (hw->phy_revision < M88E1011_I_REV_4) {
+               /* Force TX_CLK in the Extended PHY Specific Control Register
+                * to 25MHz clock.
+                */
+               ret_val =
+                   e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
+                                      &phy_data);
+               if (ret_val)
+                       return ret_val;
+
+               phy_data |= M88E1000_EPSCR_TX_CLK_25;
+
+               if ((hw->phy_revision == E1000_REVISION_2) &&
+                   (hw->phy_id == M88E1111_I_PHY_ID)) {
+                       /* Vidalia Phy, set the downshift counter to 5x */
+                       phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
+                       phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
+                       ret_val = e1000_write_phy_reg(hw,
+                                                     M88E1000_EXT_PHY_SPEC_CTRL,
+                                                     phy_data);
+                       if (ret_val)
+                               return ret_val;
+               } else {
+                       /* Configure Master and Slave downshift values */
+                       phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
+                                     M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
+                       phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
+                                    M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
+                       ret_val = e1000_write_phy_reg(hw,
+                                                     M88E1000_EXT_PHY_SPEC_CTRL,
+                                                     phy_data);
+                       if (ret_val)
+                               return ret_val;
+               }
+       }
+
+       /* SW Reset the PHY so all changes take effect */
+       ret_val = e1000_phy_reset(hw);
+       if (ret_val) {
+               DEBUGOUT("Error Resetting the PHY\n");
+               return ret_val;
+       }
+
+       return E1000_SUCCESS;
+}
+
+/**
+ * e1000_copper_link_autoneg - setup auto-neg
+ * @hw: Struct containing variables accessed by shared code
  *
- * hw - Struct containing variables accessed by shared code
+ * Setup auto-negotiation and flow control advertisements,
+ * and then perform auto-negotiation.
+ */
+static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
+{
+       s32 ret_val;
+       u16 phy_data;
+
+       DEBUGFUNC("e1000_copper_link_autoneg");
+
+       /* Perform some bounds checking on the hw->autoneg_advertised
+        * parameter.  If this variable is zero, then set it to the default.
+        */
+       hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
+
+       /* If autoneg_advertised is zero, we assume it was not defaulted
+        * by the calling code so we set to advertise full capability.
+        */
+       if (hw->autoneg_advertised == 0)
+               hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
+
+       DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
+       ret_val = e1000_phy_setup_autoneg(hw);
+       if (ret_val) {
+               DEBUGOUT("Error Setting up Auto-Negotiation\n");
+               return ret_val;
+       }
+       DEBUGOUT("Restarting Auto-Neg\n");
+
+       /* Restart auto-negotiation by setting the Auto Neg Enable bit and
+        * the Auto Neg Restart bit in the PHY control register.
+        */
+       ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
+       if (ret_val)
+               return ret_val;
+
+       phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
+       ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
+       if (ret_val)
+               return ret_val;
+
+       /* Does the user want to wait for Auto-Neg to complete here, or
+        * check at a later time (for example, callback routine).
+        */
+       if (hw->wait_autoneg_complete) {
+               ret_val = e1000_wait_autoneg(hw);
+               if (ret_val) {
+                       DEBUGOUT
+                           ("Error while waiting for autoneg to complete\n");
+                       return ret_val;
+               }
+       }
+
+       hw->get_link_status = true;
+
+       return E1000_SUCCESS;
+}
+
+/**
+ * e1000_copper_link_postconfig - post link setup
+ * @hw: Struct containing variables accessed by shared code
  *
+ * Config the MAC and the PHY after link is up.
+ *   1) Set up the MAC to the current PHY speed/duplex
+ *      if we are on 82543.  If we
+ *      are on newer silicon, we only need to configure
+ *      collision distance in the Transmit Control Register.
+ *   2) Set up flow control on the MAC to that established with
+ *      the link partner.
+ *   3) Config DSP to improve Gigabit link quality for some PHY revisions.
+ */
+static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
+{
+       s32 ret_val;
+       DEBUGFUNC("e1000_copper_link_postconfig");
+
+       if (hw->mac_type >= e1000_82544) {
+               e1000_config_collision_dist(hw);
+       } else {
+               ret_val = e1000_config_mac_to_phy(hw);
+               if (ret_val) {
+                       DEBUGOUT("Error configuring MAC to PHY settings\n");
+                       return ret_val;
+               }
+       }
+       ret_val = e1000_config_fc_after_link_up(hw);
+       if (ret_val) {
+               DEBUGOUT("Error Configuring Flow Control\n");
+               return ret_val;
+       }
+
+       /* Config DSP to improve Giga link quality */
+       if (hw->phy_type == e1000_phy_igp) {
+               ret_val = e1000_config_dsp_after_link_change(hw, true);
+               if (ret_val) {
+                       DEBUGOUT("Error Configuring DSP after link up\n");
+                       return ret_val;
+               }
+       }
+
+       return E1000_SUCCESS;
+}
+
+/**
+ * e1000_setup_copper_link - phy/speed/duplex setting
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Detects which PHY is present and sets up the speed and duplex
+ */
+static s32 e1000_setup_copper_link(struct e1000_hw *hw)
+{
+       s32 ret_val;
+       u16 i;
+       u16 phy_data;
+
+       DEBUGFUNC("e1000_setup_copper_link");
+
+       /* Check if it is a valid PHY and set PHY mode if necessary. */
+       ret_val = e1000_copper_link_preconfig(hw);
+       if (ret_val)
+               return ret_val;
+
+       if (hw->phy_type == e1000_phy_igp) {
+               ret_val = e1000_copper_link_igp_setup(hw);
+               if (ret_val)
+                       return ret_val;
+       } else if (hw->phy_type == e1000_phy_m88) {
+               ret_val = e1000_copper_link_mgp_setup(hw);
+               if (ret_val)
+                       return ret_val;
+       }
+
+       if (hw->autoneg) {
+               /* Setup autoneg and flow control advertisement
+                * and perform autonegotiation */
+               ret_val = e1000_copper_link_autoneg(hw);
+               if (ret_val)
+                       return ret_val;
+       } else {
+               /* PHY will be set to 10H, 10F, 100H,or 100F
+                * depending on value from forced_speed_duplex. */
+               DEBUGOUT("Forcing speed and duplex\n");
+               ret_val = e1000_phy_force_speed_duplex(hw);
+               if (ret_val) {
+                       DEBUGOUT("Error Forcing Speed and Duplex\n");
+                       return ret_val;
+               }
+       }
+
+       /* Check link status. Wait up to 100 microseconds for link to become
+        * valid.
+        */
+       for (i = 0; i < 10; i++) {
+               ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+               if (ret_val)
+                       return ret_val;
+               ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+               if (ret_val)
+                       return ret_val;
+
+               if (phy_data & MII_SR_LINK_STATUS) {
+                       /* Config the MAC and PHY after link is up */
+                       ret_val = e1000_copper_link_postconfig(hw);
+                       if (ret_val)
+                               return ret_val;
+
+                       DEBUGOUT("Valid link established!!!\n");
+                       return E1000_SUCCESS;
+               }
+               udelay(10);
+       }
+
+       DEBUGOUT("Unable to establish link!!!\n");
+       return E1000_SUCCESS;
+}
+
+/**
+ * e1000_phy_setup_autoneg - phy settings
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Configures PHY autoneg and flow control advertisement settings
+ */
+s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
+{
+       s32 ret_val;
+       u16 mii_autoneg_adv_reg;
+       u16 mii_1000t_ctrl_reg;
+
+       DEBUGFUNC("e1000_phy_setup_autoneg");
+
+       /* Read the MII Auto-Neg Advertisement Register (Address 4). */
+       ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
+       if (ret_val)
+               return ret_val;
+
+       /* Read the MII 1000Base-T Control Register (Address 9). */
+       ret_val =
+           e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
+       if (ret_val)
+               return ret_val;
+
+       /* Need to parse both autoneg_advertised and fc and set up
+        * the appropriate PHY registers.  First we will parse for
+        * autoneg_advertised software override.  Since we can advertise
+        * a plethora of combinations, we need to check each bit
+        * individually.
+        */
+
+       /* First we clear all the 10/100 mb speed bits in the Auto-Neg
+        * Advertisement Register (Address 4) and the 1000 mb speed bits in
+        * the  1000Base-T Control Register (Address 9).
+        */
+       mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
+       mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
+
+       DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
+
+       /* Do we want to advertise 10 Mb Half Duplex? */
+       if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
+               DEBUGOUT("Advertise 10mb Half duplex\n");
+               mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
+       }
+
+       /* Do we want to advertise 10 Mb Full Duplex? */
+       if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
+               DEBUGOUT("Advertise 10mb Full duplex\n");
+               mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
+       }
+
+       /* Do we want to advertise 100 Mb Half Duplex? */
+       if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
+               DEBUGOUT("Advertise 100mb Half duplex\n");
+               mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
+       }
+
+       /* Do we want to advertise 100 Mb Full Duplex? */
+       if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
+               DEBUGOUT("Advertise 100mb Full duplex\n");
+               mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
+       }
+
+       /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
+       if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
+               DEBUGOUT
+                   ("Advertise 1000mb Half duplex requested, request denied!\n");
+       }
+
+       /* Do we want to advertise 1000 Mb Full Duplex? */
+       if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
+               DEBUGOUT("Advertise 1000mb Full duplex\n");
+               mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
+       }
+
+       /* Check for a software override of the flow control settings, and
+        * setup the PHY advertisement registers accordingly.  If
+        * auto-negotiation is enabled, then software will have to set the
+        * "PAUSE" bits to the correct value in the Auto-Negotiation
+        * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
+        *
+        * The possible values of the "fc" parameter are:
+        *      0:  Flow control is completely disabled
+        *      1:  Rx flow control is enabled (we can receive pause frames
+        *          but not send pause frames).
+        *      2:  Tx flow control is enabled (we can send pause frames
+        *          but we do not support receiving pause frames).
+        *      3:  Both Rx and TX flow control (symmetric) are enabled.
+        *  other:  No software override.  The flow control configuration
+        *          in the EEPROM is used.
+        */
+       switch (hw->fc) {
+       case E1000_FC_NONE:     /* 0 */
+               /* Flow control (RX & TX) is completely disabled by a
+                * software over-ride.
+                */
+               mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
+               break;
+       case E1000_FC_RX_PAUSE: /* 1 */
+               /* RX Flow control is enabled, and TX Flow control is
+                * disabled, by a software over-ride.
+                */
+               /* Since there really isn't a way to advertise that we are
+                * capable of RX Pause ONLY, we will advertise that we
+                * support both symmetric and asymmetric RX PAUSE.  Later
+                * (in e1000_config_fc_after_link_up) we will disable the
+                *hw's ability to send PAUSE frames.
+                */
+               mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
+               break;
+       case E1000_FC_TX_PAUSE: /* 2 */
+               /* TX Flow control is enabled, and RX Flow control is
+                * disabled, by a software over-ride.
+                */
+               mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
+               mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
+               break;
+       case E1000_FC_FULL:     /* 3 */
+               /* Flow control (both RX and TX) is enabled by a software
+                * over-ride.
+                */
+               mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
+               break;
+       default:
+               DEBUGOUT("Flow control param set incorrectly\n");
+               return -E1000_ERR_CONFIG;
+       }
+
+       ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
+       if (ret_val)
+               return ret_val;
+
+       DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
+
+       ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
+       if (ret_val)
+               return ret_val;
+
+       return E1000_SUCCESS;
+}
+
+/**
+ * e1000_phy_force_speed_duplex - force link settings
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Force PHY speed and duplex settings to hw->forced_speed_duplex
+ */
+static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
+{
+       u32 ctrl;
+       s32 ret_val;
+       u16 mii_ctrl_reg;
+       u16 mii_status_reg;
+       u16 phy_data;
+       u16 i;
+
+       DEBUGFUNC("e1000_phy_force_speed_duplex");
+
+       /* Turn off Flow control if we are forcing speed and duplex. */
+       hw->fc = E1000_FC_NONE;
+
+       DEBUGOUT1("hw->fc = %d\n", hw->fc);
+
+       /* Read the Device Control Register. */
+       ctrl = er32(CTRL);
+
+       /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
+       ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
+       ctrl &= ~(DEVICE_SPEED_MASK);
+
+       /* Clear the Auto Speed Detect Enable bit. */
+       ctrl &= ~E1000_CTRL_ASDE;
+
+       /* Read the MII Control Register. */
+       ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
+       if (ret_val)
+               return ret_val;
+
+       /* We need to disable autoneg in order to force link and duplex. */
+
+       mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
+
+       /* Are we forcing Full or Half Duplex? */
+       if (hw->forced_speed_duplex == e1000_100_full ||
+           hw->forced_speed_duplex == e1000_10_full) {
+               /* We want to force full duplex so we SET the full duplex bits in the
+                * Device and MII Control Registers.
+                */
+               ctrl |= E1000_CTRL_FD;
+               mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
+               DEBUGOUT("Full Duplex\n");
+       } else {
+               /* We want to force half duplex so we CLEAR the full duplex bits in
+                * the Device and MII Control Registers.
+                */
+               ctrl &= ~E1000_CTRL_FD;
+               mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
+               DEBUGOUT("Half Duplex\n");
+       }
+
+       /* Are we forcing 100Mbps??? */
+       if (hw->forced_speed_duplex == e1000_100_full ||
+           hw->forced_speed_duplex == e1000_100_half) {
+               /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
+               ctrl |= E1000_CTRL_SPD_100;
+               mii_ctrl_reg |= MII_CR_SPEED_100;
+               mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
+               DEBUGOUT("Forcing 100mb ");
+       } else {
+               /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
+               ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
+               mii_ctrl_reg |= MII_CR_SPEED_10;
+               mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
+               DEBUGOUT("Forcing 10mb ");
+       }
+
+       e1000_config_collision_dist(hw);
+
+       /* Write the configured values back to the Device Control Reg. */
+       ew32(CTRL, ctrl);
+
+       if (hw->phy_type == e1000_phy_m88) {
+               ret_val =
+                   e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+               if (ret_val)
+                       return ret_val;
+
+               /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
+                * forced whenever speed are duplex are forced.
+                */
+               phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
+               ret_val =
+                   e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
+               if (ret_val)
+                       return ret_val;
+
+               DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
+
+               /* Need to reset the PHY or these changes will be ignored */
+               mii_ctrl_reg |= MII_CR_RESET;
+
+               /* Disable MDI-X support for 10/100 */
+       } else {
+               /* Clear Auto-Crossover to force MDI manually.  IGP requires MDI
+                * forced whenever speed or duplex are forced.
+                */
+               ret_val =
+                   e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
+               if (ret_val)
+                       return ret_val;
+
+               phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
+               phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
+
+               ret_val =
+                   e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
+               if (ret_val)
+                       return ret_val;
+       }
+
+       /* Write back the modified PHY MII control register. */
+       ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
+       if (ret_val)
+               return ret_val;
+
+       udelay(1);
+
+       /* The wait_autoneg_complete flag may be a little misleading here.
+        * Since we are forcing speed and duplex, Auto-Neg is not enabled.
+        * But we do want to delay for a period while forcing only so we
+        * don't generate false No Link messages.  So we will wait here
+        * only if the user has set wait_autoneg_complete to 1, which is
+        * the default.
+        */
+       if (hw->wait_autoneg_complete) {
+               /* We will wait for autoneg to complete. */
+               DEBUGOUT("Waiting for forced speed/duplex link.\n");
+               mii_status_reg = 0;
+
+               /* We will wait for autoneg to complete or 4.5 seconds to expire. */
+               for (i = PHY_FORCE_TIME; i > 0; i--) {
+                       /* Read the MII Status Register and wait for Auto-Neg Complete bit
+                        * to be set.
+                        */
+                       ret_val =
+                           e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+                       if (ret_val)
+                               return ret_val;
+
+                       ret_val =
+                           e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+                       if (ret_val)
+                               return ret_val;
+
+                       if (mii_status_reg & MII_SR_LINK_STATUS)
+                               break;
+                       msleep(100);
+               }
+               if ((i == 0) && (hw->phy_type == e1000_phy_m88)) {
+                       /* We didn't get link.  Reset the DSP and wait again for link. */
+                       ret_val = e1000_phy_reset_dsp(hw);
+                       if (ret_val) {
+                               DEBUGOUT("Error Resetting PHY DSP\n");
+                               return ret_val;
+                       }
+               }
+               /* This loop will early-out if the link condition has been met.  */
+               for (i = PHY_FORCE_TIME; i > 0; i--) {
+                       if (mii_status_reg & MII_SR_LINK_STATUS)
+                               break;
+                       msleep(100);
+                       /* Read the MII Status Register and wait for Auto-Neg Complete bit
+                        * to be set.
+                        */
+                       ret_val =
+                           e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+                       if (ret_val)
+                               return ret_val;
+
+                       ret_val =
+                           e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+                       if (ret_val)
+                               return ret_val;
+               }
+       }
+
+       if (hw->phy_type == e1000_phy_m88) {
+               /* Because we reset the PHY above, we need to re-force TX_CLK in the
+                * Extended PHY Specific Control Register to 25MHz clock.  This value
+                * defaults back to a 2.5MHz clock when the PHY is reset.
+                */
+               ret_val =
+                   e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
+                                      &phy_data);
+               if (ret_val)
+                       return ret_val;
+
+               phy_data |= M88E1000_EPSCR_TX_CLK_25;
+               ret_val =
+                   e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
+                                       phy_data);
+               if (ret_val)
+                       return ret_val;
+
+               /* In addition, because of the s/w reset above, we need to enable CRS on
+                * TX.  This must be set for both full and half duplex operation.
+                */
+               ret_val =
+                   e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+               if (ret_val)
+                       return ret_val;
+
+               phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
+               ret_val =
+                   e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
+               if (ret_val)
+                       return ret_val;
+
+               if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543)
+                   && (!hw->autoneg)
+                   && (hw->forced_speed_duplex == e1000_10_full
+                       || hw->forced_speed_duplex == e1000_10_half)) {
+                       ret_val = e1000_polarity_reversal_workaround(hw);
+                       if (ret_val)
+                               return ret_val;
+               }
+       }
+       return E1000_SUCCESS;
+}
+
+/**
+ * e1000_config_collision_dist - set collision distance register
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Sets the collision distance in the Transmit Control register.
+ * Link should have been established previously. Reads the speed and duplex
+ * information from the Device Status register.
+ */
+void e1000_config_collision_dist(struct e1000_hw *hw)
+{
+       u32 tctl, coll_dist;
+
+       DEBUGFUNC("e1000_config_collision_dist");
+
+       if (hw->mac_type < e1000_82543)
+               coll_dist = E1000_COLLISION_DISTANCE_82542;
+       else
+               coll_dist = E1000_COLLISION_DISTANCE;
+
+       tctl = er32(TCTL);
+
+       tctl &= ~E1000_TCTL_COLD;
+       tctl |= coll_dist << E1000_COLD_SHIFT;
+
+       ew32(TCTL, tctl);
+       E1000_WRITE_FLUSH();
+}
+
+/**
+ * e1000_config_mac_to_phy - sync phy and mac settings
+ * @hw: Struct containing variables accessed by shared code
+ * @mii_reg: data to write to the MII control register
+ *
+ * Sets MAC speed and duplex settings to reflect the those in the PHY
+ * The contents of the PHY register containing the needed information need to
+ * be passed in.
+ */
+static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
+{
+       u32 ctrl;
+       s32 ret_val;
+       u16 phy_data;
+
+       DEBUGFUNC("e1000_config_mac_to_phy");
+
+       /* 82544 or newer MAC, Auto Speed Detection takes care of
+        * MAC speed/duplex configuration.*/
+       if (hw->mac_type >= e1000_82544)
+               return E1000_SUCCESS;
+
+       /* Read the Device Control Register and set the bits to Force Speed
+        * and Duplex.
+        */
+       ctrl = er32(CTRL);
+       ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
+       ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
+
+       /* Set up duplex in the Device Control and Transmit Control
+        * registers depending on negotiated values.
+        */
+       ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
+       if (ret_val)
+               return ret_val;
+
+       if (phy_data & M88E1000_PSSR_DPLX)
+               ctrl |= E1000_CTRL_FD;
+       else
+               ctrl &= ~E1000_CTRL_FD;
+
+       e1000_config_collision_dist(hw);
+
+       /* Set up speed in the Device Control register depending on
+        * negotiated values.
+        */
+       if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
+               ctrl |= E1000_CTRL_SPD_1000;
+       else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
+               ctrl |= E1000_CTRL_SPD_100;
+
+       /* Write the configured values back to the Device Control Reg. */
+       ew32(CTRL, ctrl);
+       return E1000_SUCCESS;
+}
+
+/**
+ * e1000_force_mac_fc - force flow control settings
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Forces the MAC's flow control settings.
  * Sets the TFCE and RFCE bits in the device control register to reflect
  * the adapter settings. TFCE and RFCE need to be explicitly set by
  * software when a Copper PHY is used because autonegotiation is managed
  * by the PHY rather than the MAC. Software must also configure these
  * bits when link is forced on a fiber connection.
- *****************************************************************************/
+ */
 s32 e1000_force_mac_fc(struct e1000_hw *hw)
 {
-    u32 ctrl;
-
-    DEBUGFUNC("e1000_force_mac_fc");
-
-    /* Get the current configuration of the Device Control Register */
-    ctrl = er32(CTRL);
-
-    /* Because we didn't get link via the internal auto-negotiation
-     * mechanism (we either forced link or we got link via PHY
-     * auto-neg), we have to manually enable/disable transmit an
-     * receive flow control.
-     *
-     * The "Case" statement below enables/disable flow control
-     * according to the "hw->fc" parameter.
-     *
-     * The possible values of the "fc" parameter are:
-     *      0:  Flow control is completely disabled
-     *      1:  Rx flow control is enabled (we can receive pause
-     *          frames but not send pause frames).
-     *      2:  Tx flow control is enabled (we can send pause frames
-     *          frames but we do not receive pause frames).
-     *      3:  Both Rx and TX flow control (symmetric) is enabled.
-     *  other:  No other values should be possible at this point.
-     */
-
-    switch (hw->fc) {
-    case E1000_FC_NONE:
-        ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
-        break;
-    case E1000_FC_RX_PAUSE:
-        ctrl &= (~E1000_CTRL_TFCE);
-        ctrl |= E1000_CTRL_RFCE;
-        break;
-    case E1000_FC_TX_PAUSE:
-        ctrl &= (~E1000_CTRL_RFCE);
-        ctrl |= E1000_CTRL_TFCE;
-        break;
-    case E1000_FC_FULL:
-        ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
-        break;
-    default:
-        DEBUGOUT("Flow control param set incorrectly\n");
-        return -E1000_ERR_CONFIG;
-    }
-
-    /* Disable TX Flow Control for 82542 (rev 2.0) */
-    if (hw->mac_type == e1000_82542_rev2_0)
-        ctrl &= (~E1000_CTRL_TFCE);
-
-    ew32(CTRL, ctrl);
-    return E1000_SUCCESS;
+       u32 ctrl;
+
+       DEBUGFUNC("e1000_force_mac_fc");
+
+       /* Get the current configuration of the Device Control Register */
+       ctrl = er32(CTRL);
+
+       /* Because we didn't get link via the internal auto-negotiation
+        * mechanism (we either forced link or we got link via PHY
+        * auto-neg), we have to manually enable/disable transmit an
+        * receive flow control.
+        *
+        * The "Case" statement below enables/disable flow control
+        * according to the "hw->fc" parameter.
+        *
+        * The possible values of the "fc" parameter are:
+        *      0:  Flow control is completely disabled
+        *      1:  Rx flow control is enabled (we can receive pause
+        *          frames but not send pause frames).
+        *      2:  Tx flow control is enabled (we can send pause frames
+        *          frames but we do not receive pause frames).
+        *      3:  Both Rx and TX flow control (symmetric) is enabled.
+        *  other:  No other values should be possible at this point.
+        */
+
+       switch (hw->fc) {
+       case E1000_FC_NONE:
+               ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
+               break;
+       case E1000_FC_RX_PAUSE:
+               ctrl &= (~E1000_CTRL_TFCE);
+               ctrl |= E1000_CTRL_RFCE;
+               break;
+       case E1000_FC_TX_PAUSE:
+               ctrl &= (~E1000_CTRL_RFCE);
+               ctrl |= E1000_CTRL_TFCE;
+               break;
+       case E1000_FC_FULL:
+               ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
+               break;
+       default:
+               DEBUGOUT("Flow control param set incorrectly\n");
+               return -E1000_ERR_CONFIG;
+       }
+
+       /* Disable TX Flow Control for 82542 (rev 2.0) */
+       if (hw->mac_type == e1000_82542_rev2_0)
+               ctrl &= (~E1000_CTRL_TFCE);
+
+       ew32(CTRL, ctrl);
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Configures flow control settings after link is established
- *
- * hw - Struct containing variables accessed by shared code
+/**
+ * e1000_config_fc_after_link_up - configure flow control after autoneg
+ * @hw: Struct containing variables accessed by shared code
  *
+ * Configures flow control settings after link is established
  * Should be called immediately after a valid link has been established.
  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
  * and autonegotiation is enabled, the MAC flow control settings will be set
  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
- * and RFCE bits will be automaticaly set to the negotiated flow control mode.
- *****************************************************************************/
+ * and RFCE bits will be automatically set to the negotiated flow control mode.
+ */
 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
 {
-    s32 ret_val;
-    u16 mii_status_reg;
-    u16 mii_nway_adv_reg;
-    u16 mii_nway_lp_ability_reg;
-    u16 speed;
-    u16 duplex;
-
-    DEBUGFUNC("e1000_config_fc_after_link_up");
-
-    /* Check for the case where we have fiber media and auto-neg failed
-     * so we had to force link.  In this case, we need to force the
-     * configuration of the MAC to match the "fc" parameter.
-     */
-    if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
-        ((hw->media_type == e1000_media_type_internal_serdes) &&
-         (hw->autoneg_failed)) ||
-        ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
-        ret_val = e1000_force_mac_fc(hw);
-        if (ret_val) {
-            DEBUGOUT("Error forcing flow control settings\n");
-            return ret_val;
-        }
-    }
-
-    /* Check for the case where we have copper media and auto-neg is
-     * enabled.  In this case, we need to check and see if Auto-Neg
-     * has completed, and if so, how the PHY and link partner has
-     * flow control configured.
-     */
-    if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
-        /* Read the MII Status Register and check to see if AutoNeg
-         * has completed.  We read this twice because this reg has
-         * some "sticky" (latched) bits.
-         */
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-        if (ret_val)
-            return ret_val;
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-        if (ret_val)
-            return ret_val;
-
-        if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
-            /* The AutoNeg process has completed, so we now need to
-             * read both the Auto Negotiation Advertisement Register
-             * (Address 4) and the Auto_Negotiation Base Page Ability
-             * Register (Address 5) to determine how flow control was
-             * negotiated.
-             */
-            ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
-                                         &mii_nway_adv_reg);
-            if (ret_val)
-                return ret_val;
-            ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
-                                         &mii_nway_lp_ability_reg);
-            if (ret_val)
-                return ret_val;
-
-            /* Two bits in the Auto Negotiation Advertisement Register
-             * (Address 4) and two bits in the Auto Negotiation Base
-             * Page Ability Register (Address 5) determine flow control
-             * for both the PHY and the link partner.  The following
-             * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
-             * 1999, describes these PAUSE resolution bits and how flow
-             * control is determined based upon these settings.
-             * NOTE:  DC = Don't Care
-             *
-             *   LOCAL DEVICE  |   LINK PARTNER
-             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
-             *-------|---------|-------|---------|--------------------
-             *   0   |    0    |  DC   |   DC    | E1000_FC_NONE
-             *   0   |    1    |   0   |   DC    | E1000_FC_NONE
-             *   0   |    1    |   1   |    0    | E1000_FC_NONE
-             *   0   |    1    |   1   |    1    | E1000_FC_TX_PAUSE
-             *   1   |    0    |   0   |   DC    | E1000_FC_NONE
-             *   1   |   DC    |   1   |   DC    | E1000_FC_FULL
-             *   1   |    1    |   0   |    0    | E1000_FC_NONE
-             *   1   |    1    |   0   |    1    | E1000_FC_RX_PAUSE
-             *
-             */
-            /* Are both PAUSE bits set to 1?  If so, this implies
-             * Symmetric Flow Control is enabled at both ends.  The
-             * ASM_DIR bits are irrelevant per the spec.
-             *
-             * For Symmetric Flow Control:
-             *
-             *   LOCAL DEVICE  |   LINK PARTNER
-             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
-             *-------|---------|-------|---------|--------------------
-             *   1   |   DC    |   1   |   DC    | E1000_FC_FULL
-             *
-             */
-            if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
-                (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
-                /* Now we need to check if the user selected RX ONLY
-                 * of pause frames.  In this case, we had to advertise
-                 * FULL flow control because we could not advertise RX
-                 * ONLY. Hence, we must now check to see if we need to
-                 * turn OFF  the TRANSMISSION of PAUSE frames.
-                 */
-                if (hw->original_fc == E1000_FC_FULL) {
-                    hw->fc = E1000_FC_FULL;
-                    DEBUGOUT("Flow Control = FULL.\n");
-                } else {
-                    hw->fc = E1000_FC_RX_PAUSE;
-                    DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
-                }
-            }
-            /* For receiving PAUSE frames ONLY.
-             *
-             *   LOCAL DEVICE  |   LINK PARTNER
-             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
-             *-------|---------|-------|---------|--------------------
-             *   0   |    1    |   1   |    1    | E1000_FC_TX_PAUSE
-             *
-             */
-            else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
-                     (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
-                     (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
-                     (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
-                hw->fc = E1000_FC_TX_PAUSE;
-                DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
-            }
-            /* For transmitting PAUSE frames ONLY.
-             *
-             *   LOCAL DEVICE  |   LINK PARTNER
-             * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
-             *-------|---------|-------|---------|--------------------
-             *   1   |    1    |   0   |    1    | E1000_FC_RX_PAUSE
-             *
-             */
-            else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
-                     (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
-                     !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
-                     (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
-                hw->fc = E1000_FC_RX_PAUSE;
-                DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
-            }
-            /* Per the IEEE spec, at this point flow control should be
-             * disabled.  However, we want to consider that we could
-             * be connected to a legacy switch that doesn't advertise
-             * desired flow control, but can be forced on the link
-             * partner.  So if we advertised no flow control, that is
-             * what we will resolve to.  If we advertised some kind of
-             * receive capability (Rx Pause Only or Full Flow Control)
-             * and the link partner advertised none, we will configure
-             * ourselves to enable Rx Flow Control only.  We can do
-             * this safely for two reasons:  If the link partner really
-             * didn't want flow control enabled, and we enable Rx, no
-             * harm done since we won't be receiving any PAUSE frames
-             * anyway.  If the intent on the link partner was to have
-             * flow control enabled, then by us enabling RX only, we
-             * can at least receive pause frames and process them.
-             * This is a good idea because in most cases, since we are
-             * predominantly a server NIC, more times than not we will
-             * be asked to delay transmission of packets than asking
-             * our link partner to pause transmission of frames.
-             */
-            else if ((hw->original_fc == E1000_FC_NONE ||
-                      hw->original_fc == E1000_FC_TX_PAUSE) ||
-                      hw->fc_strict_ieee) {
-                hw->fc = E1000_FC_NONE;
-                DEBUGOUT("Flow Control = NONE.\n");
-            } else {
-                hw->fc = E1000_FC_RX_PAUSE;
-                DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
-            }
-
-            /* Now we need to do one last check...  If we auto-
-             * negotiated to HALF DUPLEX, flow control should not be
-             * enabled per IEEE 802.3 spec.
-             */
-            ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
-            if (ret_val) {
-                DEBUGOUT("Error getting link speed and duplex\n");
-                return ret_val;
-            }
-
-            if (duplex == HALF_DUPLEX)
-                hw->fc = E1000_FC_NONE;
-
-            /* Now we call a subroutine to actually force the MAC
-             * controller to use the correct flow control settings.
-             */
-            ret_val = e1000_force_mac_fc(hw);
-            if (ret_val) {
-                DEBUGOUT("Error forcing flow control settings\n");
-                return ret_val;
-            }
-        } else {
-            DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
-        }
-    }
-    return E1000_SUCCESS;
+       s32 ret_val;
+       u16 mii_status_reg;
+       u16 mii_nway_adv_reg;
+       u16 mii_nway_lp_ability_reg;
+       u16 speed;
+       u16 duplex;
+
+       DEBUGFUNC("e1000_config_fc_after_link_up");
+
+       /* Check for the case where we have fiber media and auto-neg failed
+        * so we had to force link.  In this case, we need to force the
+        * configuration of the MAC to match the "fc" parameter.
+        */
+       if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
+           || ((hw->media_type == e1000_media_type_internal_serdes)
+               && (hw->autoneg_failed))
+           || ((hw->media_type == e1000_media_type_copper)
+               && (!hw->autoneg))) {
+               ret_val = e1000_force_mac_fc(hw);
+               if (ret_val) {
+                       DEBUGOUT("Error forcing flow control settings\n");
+                       return ret_val;
+               }
+       }
+
+       /* Check for the case where we have copper media and auto-neg is
+        * enabled.  In this case, we need to check and see if Auto-Neg
+        * has completed, and if so, how the PHY and link partner has
+        * flow control configured.
+        */
+       if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
+               /* Read the MII Status Register and check to see if AutoNeg
+                * has completed.  We read this twice because this reg has
+                * some "sticky" (latched) bits.
+                */
+               ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+               if (ret_val)
+                       return ret_val;
+               ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+               if (ret_val)
+                       return ret_val;
+
+               if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
+                       /* The AutoNeg process has completed, so we now need to
+                        * read both the Auto Negotiation Advertisement Register
+                        * (Address 4) and the Auto_Negotiation Base Page Ability
+                        * Register (Address 5) to determine how flow control was
+                        * negotiated.
+                        */
+                       ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
+                                                    &mii_nway_adv_reg);
+                       if (ret_val)
+                               return ret_val;
+                       ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
+                                                    &mii_nway_lp_ability_reg);
+                       if (ret_val)
+                               return ret_val;
+
+                       /* Two bits in the Auto Negotiation Advertisement Register
+                        * (Address 4) and two bits in the Auto Negotiation Base
+                        * Page Ability Register (Address 5) determine flow control
+                        * for both the PHY and the link partner.  The following
+                        * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
+                        * 1999, describes these PAUSE resolution bits and how flow
+                        * control is determined based upon these settings.
+                        * NOTE:  DC = Don't Care
+                        *
+                        *   LOCAL DEVICE  |   LINK PARTNER
+                        * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
+                        *-------|---------|-------|---------|--------------------
+                        *   0   |    0    |  DC   |   DC    | E1000_FC_NONE
+                        *   0   |    1    |   0   |   DC    | E1000_FC_NONE
+                        *   0   |    1    |   1   |    0    | E1000_FC_NONE
+                        *   0   |    1    |   1   |    1    | E1000_FC_TX_PAUSE
+                        *   1   |    0    |   0   |   DC    | E1000_FC_NONE
+                        *   1   |   DC    |   1   |   DC    | E1000_FC_FULL
+                        *   1   |    1    |   0   |    0    | E1000_FC_NONE
+                        *   1   |    1    |   0   |    1    | E1000_FC_RX_PAUSE
+                        *
+                        */
+                       /* Are both PAUSE bits set to 1?  If so, this implies
+                        * Symmetric Flow Control is enabled at both ends.  The
+                        * ASM_DIR bits are irrelevant per the spec.
+                        *
+                        * For Symmetric Flow Control:
+                        *
+                        *   LOCAL DEVICE  |   LINK PARTNER
+                        * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
+                        *-------|---------|-------|---------|--------------------
+                        *   1   |   DC    |   1   |   DC    | E1000_FC_FULL
+                        *
+                        */
+                       if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
+                           (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
+                               /* Now we need to check if the user selected RX ONLY
+                                * of pause frames.  In this case, we had to advertise
+                                * FULL flow control because we could not advertise RX
+                                * ONLY. Hence, we must now check to see if we need to
+                                * turn OFF  the TRANSMISSION of PAUSE frames.
+                                */
+                               if (hw->original_fc == E1000_FC_FULL) {
+                                       hw->fc = E1000_FC_FULL;
+                                       DEBUGOUT("Flow Control = FULL.\n");
+                               } else {
+                                       hw->fc = E1000_FC_RX_PAUSE;
+                                       DEBUGOUT
+                                           ("Flow Control = RX PAUSE frames only.\n");
+                               }
+                       }
+                       /* For receiving PAUSE frames ONLY.
+                        *
+                        *   LOCAL DEVICE  |   LINK PARTNER
+                        * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
+                        *-------|---------|-------|---------|--------------------
+                        *   0   |    1    |   1   |    1    | E1000_FC_TX_PAUSE
+                        *
+                        */
+                       else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
+                                (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
+                                (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
+                                (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
+                       {
+                               hw->fc = E1000_FC_TX_PAUSE;
+                               DEBUGOUT
+                                   ("Flow Control = TX PAUSE frames only.\n");
+                       }
+                       /* For transmitting PAUSE frames ONLY.
+                        *
+                        *   LOCAL DEVICE  |   LINK PARTNER
+                        * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
+                        *-------|---------|-------|---------|--------------------
+                        *   1   |    1    |   0   |    1    | E1000_FC_RX_PAUSE
+                        *
+                        */
+                       else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
+                                (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
+                                !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
+                                (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
+                       {
+                               hw->fc = E1000_FC_RX_PAUSE;
+                               DEBUGOUT
+                                   ("Flow Control = RX PAUSE frames only.\n");
+                       }
+                       /* Per the IEEE spec, at this point flow control should be
+                        * disabled.  However, we want to consider that we could
+                        * be connected to a legacy switch that doesn't advertise
+                        * desired flow control, but can be forced on the link
+                        * partner.  So if we advertised no flow control, that is
+                        * what we will resolve to.  If we advertised some kind of
+                        * receive capability (Rx Pause Only or Full Flow Control)
+                        * and the link partner advertised none, we will configure
+                        * ourselves to enable Rx Flow Control only.  We can do
+                        * this safely for two reasons:  If the link partner really
+                        * didn't want flow control enabled, and we enable Rx, no
+                        * harm done since we won't be receiving any PAUSE frames
+                        * anyway.  If the intent on the link partner was to have
+                        * flow control enabled, then by us enabling RX only, we
+                        * can at least receive pause frames and process them.
+                        * This is a good idea because in most cases, since we are
+                        * predominantly a server NIC, more times than not we will
+                        * be asked to delay transmission of packets than asking
+                        * our link partner to pause transmission of frames.
+                        */
+                       else if ((hw->original_fc == E1000_FC_NONE ||
+                                 hw->original_fc == E1000_FC_TX_PAUSE) ||
+                                hw->fc_strict_ieee) {
+                               hw->fc = E1000_FC_NONE;
+                               DEBUGOUT("Flow Control = NONE.\n");
+                       } else {
+                               hw->fc = E1000_FC_RX_PAUSE;
+                               DEBUGOUT
+                                   ("Flow Control = RX PAUSE frames only.\n");
+                       }
+
+                       /* Now we need to do one last check...  If we auto-
+                        * negotiated to HALF DUPLEX, flow control should not be
+                        * enabled per IEEE 802.3 spec.
+                        */
+                       ret_val =
+                           e1000_get_speed_and_duplex(hw, &speed, &duplex);
+                       if (ret_val) {
+                               DEBUGOUT
+                                   ("Error getting link speed and duplex\n");
+                               return ret_val;
+                       }
+
+                       if (duplex == HALF_DUPLEX)
+                               hw->fc = E1000_FC_NONE;
+
+                       /* Now we call a subroutine to actually force the MAC
+                        * controller to use the correct flow control settings.
+                        */
+                       ret_val = e1000_force_mac_fc(hw);
+                       if (ret_val) {
+                               DEBUGOUT
+                                   ("Error forcing flow control settings\n");
+                               return ret_val;
+                       }
+               } else {
+                       DEBUGOUT
+                           ("Copper PHY and Auto Neg has not completed.\n");
+               }
+       }
+       return E1000_SUCCESS;
 }
 
 /**
- *  e1000_check_for_serdes_link_generic - Check for link (Serdes)
- *  @hw: pointer to the HW structure
+ * e1000_check_for_serdes_link_generic - Check for link (Serdes)
+ * @hw: pointer to the HW structure
  *
- *  Checks for link up on the hardware.  If link is not up and we have
- *  a signal, then we need to force link up.
- **/
+ * Checks for link up on the hardware.  If link is not up and we have
+ * a signal, then we need to force link up.
+ */
 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
 {
        u32 rxcw;
@@ -2227,2647 +2279,2676 @@ s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
                                if (!(rxcw & E1000_RXCW_IV)) {
                                        hw->serdes_has_link = true;
                                        DEBUGOUT("SERDES: Link up - autoneg "
-                                          "completed sucessfully.\n");
+                                                "completed successfully.\n");
                                } else {
                                        hw->serdes_has_link = false;
                                        DEBUGOUT("SERDES: Link down - invalid"
-                                          "codewords detected in autoneg.\n");
+                                                "codewords detected in autoneg.\n");
+                               }
+                       } else {
+                               hw->serdes_has_link = false;
+                               DEBUGOUT("SERDES: Link down - no sync.\n");
+                       }
+               } else {
+                       hw->serdes_has_link = false;
+                       DEBUGOUT("SERDES: Link down - autoneg failed\n");
+               }
+       }
+
+      out:
+       return ret_val;
+}
+
+/**
+ * e1000_check_for_link
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Checks to see if the link status of the hardware has changed.
+ * Called by any function that needs to check the link status of the adapter.
+ */
+s32 e1000_check_for_link(struct e1000_hw *hw)
+{
+       u32 rxcw = 0;
+       u32 ctrl;
+       u32 status;
+       u32 rctl;
+       u32 icr;
+       u32 signal = 0;
+       s32 ret_val;
+       u16 phy_data;
+
+       DEBUGFUNC("e1000_check_for_link");
+
+       ctrl = er32(CTRL);
+       status = er32(STATUS);
+
+       /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be
+        * set when the optics detect a signal. On older adapters, it will be
+        * cleared when there is a signal.  This applies to fiber media only.
+        */
+       if ((hw->media_type == e1000_media_type_fiber) ||
+           (hw->media_type == e1000_media_type_internal_serdes)) {
+               rxcw = er32(RXCW);
+
+               if (hw->media_type == e1000_media_type_fiber) {
+                       signal =
+                           (hw->mac_type >
+                            e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
+                       if (status & E1000_STATUS_LU)
+                               hw->get_link_status = false;
+               }
+       }
+
+       /* If we have a copper PHY then we only want to go out to the PHY
+        * registers to see if Auto-Neg has completed and/or if our link
+        * status has changed.  The get_link_status flag will be set if we
+        * receive a Link Status Change interrupt or we have Rx Sequence
+        * Errors.
+        */
+       if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
+               /* First we want to see if the MII Status Register reports
+                * link.  If so, then we want to get the current speed/duplex
+                * of the PHY.
+                * Read the register twice since the link bit is sticky.
+                */
+               ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+               if (ret_val)
+                       return ret_val;
+               ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+               if (ret_val)
+                       return ret_val;
+
+               if (phy_data & MII_SR_LINK_STATUS) {
+                       hw->get_link_status = false;
+                       /* Check if there was DownShift, must be checked immediately after
+                        * link-up */
+                       e1000_check_downshift(hw);
+
+                       /* If we are on 82544 or 82543 silicon and speed/duplex
+                        * are forced to 10H or 10F, then we will implement the polarity
+                        * reversal workaround.  We disable interrupts first, and upon
+                        * returning, place the devices interrupt state to its previous
+                        * value except for the link status change interrupt which will
+                        * happen due to the execution of this workaround.
+                        */
+
+                       if ((hw->mac_type == e1000_82544
+                            || hw->mac_type == e1000_82543) && (!hw->autoneg)
+                           && (hw->forced_speed_duplex == e1000_10_full
+                               || hw->forced_speed_duplex == e1000_10_half)) {
+                               ew32(IMC, 0xffffffff);
+                               ret_val =
+                                   e1000_polarity_reversal_workaround(hw);
+                               icr = er32(ICR);
+                               ew32(ICS, (icr & ~E1000_ICS_LSC));
+                               ew32(IMS, IMS_ENABLE_MASK);
+                       }
+
+               } else {
+                       /* No link detected */
+                       e1000_config_dsp_after_link_change(hw, false);
+                       return 0;
+               }
+
+               /* If we are forcing speed/duplex, then we simply return since
+                * we have already determined whether we have link or not.
+                */
+               if (!hw->autoneg)
+                       return -E1000_ERR_CONFIG;
+
+               /* optimize the dsp settings for the igp phy */
+               e1000_config_dsp_after_link_change(hw, true);
+
+               /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
+                * have Si on board that is 82544 or newer, Auto
+                * Speed Detection takes care of MAC speed/duplex
+                * configuration.  So we only need to configure Collision
+                * Distance in the MAC.  Otherwise, we need to force
+                * speed/duplex on the MAC to the current PHY speed/duplex
+                * settings.
+                */
+               if (hw->mac_type >= e1000_82544)
+                       e1000_config_collision_dist(hw);
+               else {
+                       ret_val = e1000_config_mac_to_phy(hw);
+                       if (ret_val) {
+                               DEBUGOUT
+                                   ("Error configuring MAC to PHY settings\n");
+                               return ret_val;
+                       }
+               }
+
+               /* Configure Flow Control now that Auto-Neg has completed. First, we
+                * need to restore the desired flow control settings because we may
+                * have had to re-autoneg with a different link partner.
+                */
+               ret_val = e1000_config_fc_after_link_up(hw);
+               if (ret_val) {
+                       DEBUGOUT("Error configuring flow control\n");
+                       return ret_val;
+               }
+
+               /* At this point we know that we are on copper and we have
+                * auto-negotiated link.  These are conditions for checking the link
+                * partner capability register.  We use the link speed to determine if
+                * TBI compatibility needs to be turned on or off.  If the link is not
+                * at gigabit speed, then TBI compatibility is not needed.  If we are
+                * at gigabit speed, we turn on TBI compatibility.
+                */
+               if (hw->tbi_compatibility_en) {
+                       u16 speed, duplex;
+                       ret_val =
+                           e1000_get_speed_and_duplex(hw, &speed, &duplex);
+                       if (ret_val) {
+                               DEBUGOUT
+                                   ("Error getting link speed and duplex\n");
+                               return ret_val;
+                       }
+                       if (speed != SPEED_1000) {
+                               /* If link speed is not set to gigabit speed, we do not need
+                                * to enable TBI compatibility.
+                                */
+                               if (hw->tbi_compatibility_on) {
+                                       /* If we previously were in the mode, turn it off. */
+                                       rctl = er32(RCTL);
+                                       rctl &= ~E1000_RCTL_SBP;
+                                       ew32(RCTL, rctl);
+                                       hw->tbi_compatibility_on = false;
                                }
                        } else {
-                               hw->serdes_has_link = false;
-                               DEBUGOUT("SERDES: Link down - no sync.\n");
+                               /* If TBI compatibility is was previously off, turn it on. For
+                                * compatibility with a TBI link partner, we will store bad
+                                * packets. Some frames have an additional byte on the end and
+                                * will look like CRC errors to to the hardware.
+                                */
+                               if (!hw->tbi_compatibility_on) {
+                                       hw->tbi_compatibility_on = true;
+                                       rctl = er32(RCTL);
+                                       rctl |= E1000_RCTL_SBP;
+                                       ew32(RCTL, rctl);
+                               }
                        }
-               } else {
-                       hw->serdes_has_link = false;
-                       DEBUGOUT("SERDES: Link down - autoneg failed\n");
                }
        }
 
-out:
-       return ret_val;
-}
-/******************************************************************************
- * Checks to see if the link status of the hardware has changed.
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Called by any function that needs to check the link status of the adapter.
- *****************************************************************************/
-s32 e1000_check_for_link(struct e1000_hw *hw)
-{
-    u32 rxcw = 0;
-    u32 ctrl;
-    u32 status;
-    u32 rctl;
-    u32 icr;
-    u32 signal = 0;
-    s32 ret_val;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_check_for_link");
-
-    ctrl = er32(CTRL);
-    status = er32(STATUS);
-
-    /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
-     * set when the optics detect a signal. On older adapters, it will be
-     * cleared when there is a signal.  This applies to fiber media only.
-     */
-    if ((hw->media_type == e1000_media_type_fiber) ||
-        (hw->media_type == e1000_media_type_internal_serdes)) {
-        rxcw = er32(RXCW);
-
-        if (hw->media_type == e1000_media_type_fiber) {
-            signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
-            if (status & E1000_STATUS_LU)
-                hw->get_link_status = false;
-        }
-    }
-
-    /* If we have a copper PHY then we only want to go out to the PHY
-     * registers to see if Auto-Neg has completed and/or if our link
-     * status has changed.  The get_link_status flag will be set if we
-     * receive a Link Status Change interrupt or we have Rx Sequence
-     * Errors.
-     */
-    if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
-        /* First we want to see if the MII Status Register reports
-         * link.  If so, then we want to get the current speed/duplex
-         * of the PHY.
-         * Read the register twice since the link bit is sticky.
-         */
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-        if (ret_val)
-            return ret_val;
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        if (phy_data & MII_SR_LINK_STATUS) {
-            hw->get_link_status = false;
-            /* Check if there was DownShift, must be checked immediately after
-             * link-up */
-            e1000_check_downshift(hw);
-
-            /* If we are on 82544 or 82543 silicon and speed/duplex
-             * are forced to 10H or 10F, then we will implement the polarity
-             * reversal workaround.  We disable interrupts first, and upon
-             * returning, place the devices interrupt state to its previous
-             * value except for the link status change interrupt which will
-             * happen due to the execution of this workaround.
-             */
-
-            if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
-                (!hw->autoneg) &&
-                (hw->forced_speed_duplex == e1000_10_full ||
-                 hw->forced_speed_duplex == e1000_10_half)) {
-                ew32(IMC, 0xffffffff);
-                ret_val = e1000_polarity_reversal_workaround(hw);
-                icr = er32(ICR);
-                ew32(ICS, (icr & ~E1000_ICS_LSC));
-                ew32(IMS, IMS_ENABLE_MASK);
-            }
-
-        } else {
-            /* No link detected */
-            e1000_config_dsp_after_link_change(hw, false);
-            return 0;
-        }
-
-        /* If we are forcing speed/duplex, then we simply return since
-         * we have already determined whether we have link or not.
-         */
-        if (!hw->autoneg) return -E1000_ERR_CONFIG;
-
-        /* optimize the dsp settings for the igp phy */
-        e1000_config_dsp_after_link_change(hw, true);
-
-        /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
-         * have Si on board that is 82544 or newer, Auto
-         * Speed Detection takes care of MAC speed/duplex
-         * configuration.  So we only need to configure Collision
-         * Distance in the MAC.  Otherwise, we need to force
-         * speed/duplex on the MAC to the current PHY speed/duplex
-         * settings.
-         */
-        if (hw->mac_type >= e1000_82544)
-            e1000_config_collision_dist(hw);
-        else {
-            ret_val = e1000_config_mac_to_phy(hw);
-            if (ret_val) {
-                DEBUGOUT("Error configuring MAC to PHY settings\n");
-                return ret_val;
-            }
-        }
-
-        /* Configure Flow Control now that Auto-Neg has completed. First, we
-         * need to restore the desired flow control settings because we may
-         * have had to re-autoneg with a different link partner.
-         */
-        ret_val = e1000_config_fc_after_link_up(hw);
-        if (ret_val) {
-            DEBUGOUT("Error configuring flow control\n");
-            return ret_val;
-        }
-
-        /* At this point we know that we are on copper and we have
-         * auto-negotiated link.  These are conditions for checking the link
-         * partner capability register.  We use the link speed to determine if
-         * TBI compatibility needs to be turned on or off.  If the link is not
-         * at gigabit speed, then TBI compatibility is not needed.  If we are
-         * at gigabit speed, we turn on TBI compatibility.
-         */
-        if (hw->tbi_compatibility_en) {
-            u16 speed, duplex;
-            ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
-            if (ret_val) {
-                DEBUGOUT("Error getting link speed and duplex\n");
-                return ret_val;
-            }
-            if (speed != SPEED_1000) {
-                /* If link speed is not set to gigabit speed, we do not need
-                 * to enable TBI compatibility.
-                 */
-                if (hw->tbi_compatibility_on) {
-                    /* If we previously were in the mode, turn it off. */
-                    rctl = er32(RCTL);
-                    rctl &= ~E1000_RCTL_SBP;
-                    ew32(RCTL, rctl);
-                    hw->tbi_compatibility_on = false;
-                }
-            } else {
-                /* If TBI compatibility is was previously off, turn it on. For
-                 * compatibility with a TBI link partner, we will store bad
-                 * packets. Some frames have an additional byte on the end and
-                 * will look like CRC errors to the hardware.
-                 */
-                if (!hw->tbi_compatibility_on) {
-                    hw->tbi_compatibility_on = true;
-                    rctl = er32(RCTL);
-                    rctl |= E1000_RCTL_SBP;
-                    ew32(RCTL, rctl);
-                }
-            }
-        }
-    }
-
-    if ((hw->media_type == e1000_media_type_fiber) ||
-        (hw->media_type == e1000_media_type_internal_serdes))
-        e1000_check_for_serdes_link_generic(hw);
-
-    return E1000_SUCCESS;
+       if ((hw->media_type == e1000_media_type_fiber) ||
+           (hw->media_type == e1000_media_type_internal_serdes))
+               e1000_check_for_serdes_link_generic(hw);
+
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
+/**
+ * e1000_get_speed_and_duplex
+ * @hw: Struct containing variables accessed by shared code
+ * @speed: Speed of the connection
+ * @duplex: Duplex setting of the connection
+
  * Detects the current speed and duplex settings of the hardware.
- *
- * hw - Struct containing variables accessed by shared code
- * speed - Speed of the connection
- * duplex - Duplex setting of the connection
- *****************************************************************************/
+ */
 s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
 {
-    u32 status;
-    s32 ret_val;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_get_speed_and_duplex");
-
-    if (hw->mac_type >= e1000_82543) {
-        status = er32(STATUS);
-        if (status & E1000_STATUS_SPEED_1000) {
-            *speed = SPEED_1000;
-            DEBUGOUT("1000 Mbs, ");
-        } else if (status & E1000_STATUS_SPEED_100) {
-            *speed = SPEED_100;
-            DEBUGOUT("100 Mbs, ");
-        } else {
-            *speed = SPEED_10;
-            DEBUGOUT("10 Mbs, ");
-        }
-
-        if (status & E1000_STATUS_FD) {
-            *duplex = FULL_DUPLEX;
-            DEBUGOUT("Full Duplex\n");
-        } else {
-            *duplex = HALF_DUPLEX;
-            DEBUGOUT(" Half Duplex\n");
-        }
-    } else {
-        DEBUGOUT("1000 Mbs, Full Duplex\n");
-        *speed = SPEED_1000;
-        *duplex = FULL_DUPLEX;
-    }
-
-    /* IGP01 PHY may advertise full duplex operation after speed downgrade even
-     * if it is operating at half duplex.  Here we set the duplex settings to
-     * match the duplex in the link partner's capabilities.
-     */
-    if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
-        ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
-            *duplex = HALF_DUPLEX;
-        else {
-            ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
-            if (ret_val)
-                return ret_val;
-            if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
-               (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
-                *duplex = HALF_DUPLEX;
-        }
-    }
-
-    return E1000_SUCCESS;
+       u32 status;
+       s32 ret_val;
+       u16 phy_data;
+
+       DEBUGFUNC("e1000_get_speed_and_duplex");
+
+       if (hw->mac_type >= e1000_82543) {
+               status = er32(STATUS);
+               if (status & E1000_STATUS_SPEED_1000) {
+                       *speed = SPEED_1000;
+                       DEBUGOUT("1000 Mbs, ");
+               } else if (status & E1000_STATUS_SPEED_100) {
+                       *speed = SPEED_100;
+                       DEBUGOUT("100 Mbs, ");
+               } else {
+                       *speed = SPEED_10;
+                       DEBUGOUT("10 Mbs, ");
+               }
+
+               if (status & E1000_STATUS_FD) {
+                       *duplex = FULL_DUPLEX;
+                       DEBUGOUT("Full Duplex\n");
+               } else {
+                       *duplex = HALF_DUPLEX;
+                       DEBUGOUT(" Half Duplex\n");
+               }
+       } else {
+               DEBUGOUT("1000 Mbs, Full Duplex\n");
+               *speed = SPEED_1000;
+               *duplex = FULL_DUPLEX;
+       }
+
+       /* IGP01 PHY may advertise full duplex operation after speed downgrade even
+        * if it is operating at half duplex.  Here we set the duplex settings to
+        * match the duplex in the link partner's capabilities.
+        */
+       if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
+               ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
+               if (ret_val)
+                       return ret_val;
+
+               if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
+                       *duplex = HALF_DUPLEX;
+               else {
+                       ret_val =
+                           e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
+                       if (ret_val)
+                               return ret_val;
+                       if ((*speed == SPEED_100
+                            && !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
+                           || (*speed == SPEED_10
+                               && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
+                               *duplex = HALF_DUPLEX;
+               }
+       }
+
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
-* Blocks until autoneg completes or times out (~4.5 seconds)
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
+/**
+ * e1000_wait_autoneg
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Blocks until autoneg completes or times out (~4.5 seconds)
+ */
 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
 {
-    s32 ret_val;
-    u16 i;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_wait_autoneg");
-    DEBUGOUT("Waiting for Auto-Neg to complete.\n");
-
-    /* We will wait for autoneg to complete or 4.5 seconds to expire. */
-    for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
-        /* Read the MII Status Register and wait for Auto-Neg
-         * Complete bit to be set.
-         */
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-        if (ret_val)
-            return ret_val;
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-        if (ret_val)
-            return ret_val;
-        if (phy_data & MII_SR_AUTONEG_COMPLETE) {
-            return E1000_SUCCESS;
-        }
-        msleep(100);
-    }
-    return E1000_SUCCESS;
+       s32 ret_val;
+       u16 i;
+       u16 phy_data;
+
+       DEBUGFUNC("e1000_wait_autoneg");
+       DEBUGOUT("Waiting for Auto-Neg to complete.\n");
+
+       /* We will wait for autoneg to complete or 4.5 seconds to expire. */
+       for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
+               /* Read the MII Status Register and wait for Auto-Neg
+                * Complete bit to be set.
+                */
+               ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+               if (ret_val)
+                       return ret_val;
+               ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+               if (ret_val)
+                       return ret_val;
+               if (phy_data & MII_SR_AUTONEG_COMPLETE) {
+                       return E1000_SUCCESS;
+               }
+               msleep(100);
+       }
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
-* Raises the Management Data Clock
-*
-* hw - Struct containing variables accessed by shared code
-* ctrl - Device control register's current value
-******************************************************************************/
+/**
+ * e1000_raise_mdi_clk - Raises the Management Data Clock
+ * @hw: Struct containing variables accessed by shared code
+ * @ctrl: Device control register's current value
+ */
 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
 {
-    /* Raise the clock input to the Management Data Clock (by setting the MDC
-     * bit), and then delay 10 microseconds.
-     */
-    ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
-    E1000_WRITE_FLUSH();
-    udelay(10);
+       /* Raise the clock input to the Management Data Clock (by setting the MDC
+        * bit), and then delay 10 microseconds.
+        */
+       ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
+       E1000_WRITE_FLUSH();
+       udelay(10);
 }
 
-/******************************************************************************
-* Lowers the Management Data Clock
-*
-* hw - Struct containing variables accessed by shared code
-* ctrl - Device control register's current value
-******************************************************************************/
+/**
+ * e1000_lower_mdi_clk - Lowers the Management Data Clock
+ * @hw: Struct containing variables accessed by shared code
+ * @ctrl: Device control register's current value
+ */
 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
 {
-    /* Lower the clock input to the Management Data Clock (by clearing the MDC
-     * bit), and then delay 10 microseconds.
-     */
-    ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
-    E1000_WRITE_FLUSH();
-    udelay(10);
+       /* Lower the clock input to the Management Data Clock (by clearing the MDC
+        * bit), and then delay 10 microseconds.
+        */
+       ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
+       E1000_WRITE_FLUSH();
+       udelay(10);
 }
 
-/******************************************************************************
-* Shifts data bits out to the PHY
-*
-* hw - Struct containing variables accessed by shared code
-* data - Data to send out to the PHY
-* count - Number of bits to shift out
-*
-* Bits are shifted out in MSB to LSB order.
-******************************************************************************/
+/**
+ * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY
+ * @hw: Struct containing variables accessed by shared code
+ * @data: Data to send out to the PHY
+ * @count: Number of bits to shift out
+ *
+ * Bits are shifted out in MSB to LSB order.
+ */
 static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
 {
-    u32 ctrl;
-    u32 mask;
-
-    /* We need to shift "count" number of bits out to the PHY. So, the value
-     * in the "data" parameter will be shifted out to the PHY one bit at a
-     * time. In order to do this, "data" must be broken down into bits.
-     */
-    mask = 0x01;
-    mask <<= (count - 1);
-
-    ctrl = er32(CTRL);
-
-    /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
-    ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
-
-    while (mask) {
-        /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
-         * then raising and lowering the Management Data Clock. A "0" is
-         * shifted out to the PHY by setting the MDIO bit to "0" and then
-         * raising and lowering the clock.
-         */
-        if (data & mask)
-            ctrl |= E1000_CTRL_MDIO;
-        else
-            ctrl &= ~E1000_CTRL_MDIO;
-
-        ew32(CTRL, ctrl);
-        E1000_WRITE_FLUSH();
-
-        udelay(10);
-
-        e1000_raise_mdi_clk(hw, &ctrl);
-        e1000_lower_mdi_clk(hw, &ctrl);
-
-        mask = mask >> 1;
-    }
+       u32 ctrl;
+       u32 mask;
+
+       /* We need to shift "count" number of bits out to the PHY. So, the value
+        * in the "data" parameter will be shifted out to the PHY one bit at a
+        * time. In order to do this, "data" must be broken down into bits.
+        */
+       mask = 0x01;
+       mask <<= (count - 1);
+
+       ctrl = er32(CTRL);
+
+       /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
+       ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
+
+       while (mask) {
+               /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
+                * then raising and lowering the Management Data Clock. A "0" is
+                * shifted out to the PHY by setting the MDIO bit to "0" and then
+                * raising and lowering the clock.
+                */
+               if (data & mask)
+                       ctrl |= E1000_CTRL_MDIO;
+               else
+                       ctrl &= ~E1000_CTRL_MDIO;
+
+               ew32(CTRL, ctrl);
+               E1000_WRITE_FLUSH();
+
+               udelay(10);
+
+               e1000_raise_mdi_clk(hw, &ctrl);
+               e1000_lower_mdi_clk(hw, &ctrl);
+
+               mask = mask >> 1;
+       }
 }
 
-/******************************************************************************
-* Shifts data bits in from the PHY
-*
-* hw - Struct containing variables accessed by shared code
-*
-* Bits are shifted in in MSB to LSB order.
-******************************************************************************/
+/**
+ * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Bits are shifted in in MSB to LSB order.
+ */
 static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
 {
-    u32 ctrl;
-    u16 data = 0;
-    u8 i;
-
-    /* In order to read a register from the PHY, we need to shift in a total
-     * of 18 bits from the PHY. The first two bit (turnaround) times are used
-     * to avoid contention on the MDIO pin when a read operation is performed.
-     * These two bits are ignored by us and thrown away. Bits are "shifted in"
-     * by raising the input to the Management Data Clock (setting the MDC bit),
-     * and then reading the value of the MDIO bit.
-     */
-    ctrl = er32(CTRL);
-
-    /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
-    ctrl &= ~E1000_CTRL_MDIO_DIR;
-    ctrl &= ~E1000_CTRL_MDIO;
-
-    ew32(CTRL, ctrl);
-    E1000_WRITE_FLUSH();
-
-    /* Raise and Lower the clock before reading in the data. This accounts for
-     * the turnaround bits. The first clock occurred when we clocked out the
-     * last bit of the Register Address.
-     */
-    e1000_raise_mdi_clk(hw, &ctrl);
-    e1000_lower_mdi_clk(hw, &ctrl);
-
-    for (data = 0, i = 0; i < 16; i++) {
-        data = data << 1;
-        e1000_raise_mdi_clk(hw, &ctrl);
-        ctrl = er32(CTRL);
-        /* Check to see if we shifted in a "1". */
-        if (ctrl & E1000_CTRL_MDIO)
-            data |= 1;
-        e1000_lower_mdi_clk(hw, &ctrl);
-    }
-
-    e1000_raise_mdi_clk(hw, &ctrl);
-    e1000_lower_mdi_clk(hw, &ctrl);
-
-    return data;
+       u32 ctrl;
+       u16 data = 0;
+       u8 i;
+
+       /* In order to read a register from the PHY, we need to shift in a total
+        * of 18 bits from the PHY. The first two bit (turnaround) times are used
+        * to avoid contention on the MDIO pin when a read operation is performed.
+        * These two bits are ignored by us and thrown away. Bits are "shifted in"
+        * by raising the input to the Management Data Clock (setting the MDC bit),
+        * and then reading the value of the MDIO bit.
+        */
+       ctrl = er32(CTRL);
+
+       /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
+       ctrl &= ~E1000_CTRL_MDIO_DIR;
+       ctrl &= ~E1000_CTRL_MDIO;
+
+       ew32(CTRL, ctrl);
+       E1000_WRITE_FLUSH();
+
+       /* Raise and Lower the clock before reading in the data. This accounts for
+        * the turnaround bits. The first clock occurred when we clocked out the
+        * last bit of the Register Address.
+        */
+       e1000_raise_mdi_clk(hw, &ctrl);
+       e1000_lower_mdi_clk(hw, &ctrl);
+
+       for (data = 0, i = 0; i < 16; i++) {
+               data = data << 1;
+               e1000_raise_mdi_clk(hw, &ctrl);
+               ctrl = er32(CTRL);
+               /* Check to see if we shifted in a "1". */
+               if (ctrl & E1000_CTRL_MDIO)
+                       data |= 1;
+               e1000_lower_mdi_clk(hw, &ctrl);
+       }
+
+       e1000_raise_mdi_clk(hw, &ctrl);
+       e1000_lower_mdi_clk(hw, &ctrl);
+
+       return data;
 }
 
-/*****************************************************************************
-* Reads the value from a PHY register, if the value is on a specific non zero
-* page, sets the page first.
-* hw - Struct containing variables accessed by shared code
-* reg_addr - address of the PHY register to read
-******************************************************************************/
+
+/**
+ * e1000_read_phy_reg - read a phy register
+ * @hw: Struct containing variables accessed by shared code
+ * @reg_addr: address of the PHY register to read
+ *
+ * Reads the value from a PHY register, if the value is on a specific non zero
+ * page, sets the page first.
+ */
 s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
 {
-    u32 ret_val;
+       u32 ret_val;
 
-    DEBUGFUNC("e1000_read_phy_reg");
+       DEBUGFUNC("e1000_read_phy_reg");
 
-    if ((hw->phy_type == e1000_phy_igp) &&
-        (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
-        ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
-                                         (u16)reg_addr);
-        if (ret_val)
-            return ret_val;
-    }
+       if ((hw->phy_type == e1000_phy_igp) &&
+           (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
+               ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
+                                                (u16) reg_addr);
+               if (ret_val)
+                       return ret_val;
+       }
+
+       ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
+                                       phy_data);
 
-    ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
-                                    phy_data);
-    return ret_val;
+       return ret_val;
 }
 
 static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
                                 u16 *phy_data)
 {
-    u32 i;
-    u32 mdic = 0;
-    const u32 phy_addr = 1;
-
-    DEBUGFUNC("e1000_read_phy_reg_ex");
-
-    if (reg_addr > MAX_PHY_REG_ADDRESS) {
-        DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
-        return -E1000_ERR_PARAM;
-    }
-
-    if (hw->mac_type > e1000_82543) {
-        /* Set up Op-code, Phy Address, and register address in the MDI
-         * Control register.  The MAC will take care of interfacing with the
-         * PHY to retrieve the desired data.
-         */
-        mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
-                (phy_addr << E1000_MDIC_PHY_SHIFT) |
-                (E1000_MDIC_OP_READ));
-
-        ew32(MDIC, mdic);
-
-        /* Poll the ready bit to see if the MDI read completed */
-        for (i = 0; i < 64; i++) {
-            udelay(50);
-            mdic = er32(MDIC);
-            if (mdic & E1000_MDIC_READY) break;
-        }
-        if (!(mdic & E1000_MDIC_READY)) {
-            DEBUGOUT("MDI Read did not complete\n");
-            return -E1000_ERR_PHY;
-        }
-        if (mdic & E1000_MDIC_ERROR) {
-            DEBUGOUT("MDI Error\n");
-            return -E1000_ERR_PHY;
-        }
-        *phy_data = (u16)mdic;
-    } else {
-        /* We must first send a preamble through the MDIO pin to signal the
-         * beginning of an MII instruction.  This is done by sending 32
-         * consecutive "1" bits.
-         */
-        e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
-
-        /* Now combine the next few fields that are required for a read
-         * operation.  We use this method instead of calling the
-         * e1000_shift_out_mdi_bits routine five different times. The format of
-         * a MII read instruction consists of a shift out of 14 bits and is
-         * defined as follows:
-         *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
-         * followed by a shift in of 18 bits.  This first two bits shifted in
-         * are TurnAround bits used to avoid contention on the MDIO pin when a
-         * READ operation is performed.  These two bits are thrown away
-         * followed by a shift in of 16 bits which contains the desired data.
-         */
-        mdic = ((reg_addr) | (phy_addr << 5) |
-                (PHY_OP_READ << 10) | (PHY_SOF << 12));
-
-        e1000_shift_out_mdi_bits(hw, mdic, 14);
-
-        /* Now that we've shifted out the read command to the MII, we need to
-         * "shift in" the 16-bit value (18 total bits) of the requested PHY
-         * register address.
-         */
-        *phy_data = e1000_shift_in_mdi_bits(hw);
-    }
-    return E1000_SUCCESS;
+       u32 i;
+       u32 mdic = 0;
+       const u32 phy_addr = 1;
+
+       DEBUGFUNC("e1000_read_phy_reg_ex");
+
+       if (reg_addr > MAX_PHY_REG_ADDRESS) {
+               DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
+               return -E1000_ERR_PARAM;
+       }
+
+       if (hw->mac_type > e1000_82543) {
+               /* Set up Op-code, Phy Address, and register address in the MDI
+                * Control register.  The MAC will take care of interfacing with the
+                * PHY to retrieve the desired data.
+                */
+               mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
+                       (phy_addr << E1000_MDIC_PHY_SHIFT) |
+                       (E1000_MDIC_OP_READ));
+
+               ew32(MDIC, mdic);
+
+               /* Poll the ready bit to see if the MDI read completed */
+               for (i = 0; i < 64; i++) {
+                       udelay(50);
+                       mdic = er32(MDIC);
+                       if (mdic & E1000_MDIC_READY)
+                               break;
+               }
+               if (!(mdic & E1000_MDIC_READY)) {
+                       DEBUGOUT("MDI Read did not complete\n");
+                       return -E1000_ERR_PHY;
+               }
+               if (mdic & E1000_MDIC_ERROR) {
+                       DEBUGOUT("MDI Error\n");
+                       return -E1000_ERR_PHY;
+               }
+               *phy_data = (u16) mdic;
+       } else {
+               /* We must first send a preamble through the MDIO pin to signal the
+                * beginning of an MII instruction.  This is done by sending 32
+                * consecutive "1" bits.
+                */
+               e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
+
+               /* Now combine the next few fields that are required for a read
+                * operation.  We use this method instead of calling the
+                * e1000_shift_out_mdi_bits routine five different times. The format of
+                * a MII read instruction consists of a shift out of 14 bits and is
+                * defined as follows:
+                *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
+                * followed by a shift in of 18 bits.  This first two bits shifted in
+                * are TurnAround bits used to avoid contention on the MDIO pin when a
+                * READ operation is performed.  These two bits are thrown away
+                * followed by a shift in of 16 bits which contains the desired data.
+                */
+               mdic = ((reg_addr) | (phy_addr << 5) |
+                       (PHY_OP_READ << 10) | (PHY_SOF << 12));
+
+               e1000_shift_out_mdi_bits(hw, mdic, 14);
+
+               /* Now that we've shifted out the read command to the MII, we need to
+                * "shift in" the 16-bit value (18 total bits) of the requested PHY
+                * register address.
+                */
+               *phy_data = e1000_shift_in_mdi_bits(hw);
+       }
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
-* Writes a value to a PHY register
-*
-* hw - Struct containing variables accessed by shared code
-* reg_addr - address of the PHY register to write
-* data - data to write to the PHY
-******************************************************************************/
+/**
+ * e1000_write_phy_reg - write a phy register
+ *
+ * @hw: Struct containing variables accessed by shared code
+ * @reg_addr: address of the PHY register to write
+ * @data: data to write to the PHY
+
+ * Writes a value to a PHY register
+ */
 s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
 {
-    u32 ret_val;
+       u32 ret_val;
 
-    DEBUGFUNC("e1000_write_phy_reg");
+       DEBUGFUNC("e1000_write_phy_reg");
 
-    if ((hw->phy_type == e1000_phy_igp) &&
-        (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
-        ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
-                                         (u16)reg_addr);
-        if (ret_val)
-            return ret_val;
-    }
+       if ((hw->phy_type == e1000_phy_igp) &&
+           (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
+               ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
+                                                (u16) reg_addr);
+               if (ret_val)
+                       return ret_val;
+       }
 
-    ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
-                                     phy_data);
+       ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
+                                        phy_data);
 
-    return ret_val;
+       return ret_val;
 }
 
 static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
                                  u16 phy_data)
 {
-    u32 i;
-    u32 mdic = 0;
-    const u32 phy_addr = 1;
-
-    DEBUGFUNC("e1000_write_phy_reg_ex");
-
-    if (reg_addr > MAX_PHY_REG_ADDRESS) {
-        DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
-        return -E1000_ERR_PARAM;
-    }
-
-    if (hw->mac_type > e1000_82543) {
-        /* Set up Op-code, Phy Address, register address, and data intended
-         * for the PHY register in the MDI Control register.  The MAC will take
-         * care of interfacing with the PHY to send the desired data.
-         */
-        mdic = (((u32)phy_data) |
-                (reg_addr << E1000_MDIC_REG_SHIFT) |
-                (phy_addr << E1000_MDIC_PHY_SHIFT) |
-                (E1000_MDIC_OP_WRITE));
-
-        ew32(MDIC, mdic);
-
-        /* Poll the ready bit to see if the MDI read completed */
-        for (i = 0; i < 641; i++) {
-            udelay(5);
-            mdic = er32(MDIC);
-            if (mdic & E1000_MDIC_READY) break;
-        }
-        if (!(mdic & E1000_MDIC_READY)) {
-            DEBUGOUT("MDI Write did not complete\n");
-            return -E1000_ERR_PHY;
-        }
-    } else {
-        /* We'll need to use the SW defined pins to shift the write command
-         * out to the PHY. We first send a preamble to the PHY to signal the
-         * beginning of the MII instruction.  This is done by sending 32
-         * consecutive "1" bits.
-         */
-        e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
-
-        /* Now combine the remaining required fields that will indicate a
-         * write operation. We use this method instead of calling the
-         * e1000_shift_out_mdi_bits routine for each field in the command. The
-         * format of a MII write instruction is as follows:
-         * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
-         */
-        mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
-                (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
-        mdic <<= 16;
-        mdic |= (u32)phy_data;
-
-        e1000_shift_out_mdi_bits(hw, mdic, 32);
-    }
-
-    return E1000_SUCCESS;
+       u32 i;
+       u32 mdic = 0;
+       const u32 phy_addr = 1;
+
+       DEBUGFUNC("e1000_write_phy_reg_ex");
+
+       if (reg_addr > MAX_PHY_REG_ADDRESS) {
+               DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
+               return -E1000_ERR_PARAM;
+       }
+
+       if (hw->mac_type > e1000_82543) {
+               /* Set up Op-code, Phy Address, register address, and data intended
+                * for the PHY register in the MDI Control register.  The MAC will take
+                * care of interfacing with the PHY to send the desired data.
+                */
+               mdic = (((u32) phy_data) |
+                       (reg_addr << E1000_MDIC_REG_SHIFT) |
+                       (phy_addr << E1000_MDIC_PHY_SHIFT) |
+                       (E1000_MDIC_OP_WRITE));
+
+               ew32(MDIC, mdic);
+
+               /* Poll the ready bit to see if the MDI read completed */
+               for (i = 0; i < 641; i++) {
+                       udelay(5);
+                       mdic = er32(MDIC);
+                       if (mdic & E1000_MDIC_READY)
+                               break;
+               }
+               if (!(mdic & E1000_MDIC_READY)) {
+                       DEBUGOUT("MDI Write did not complete\n");
+                       return -E1000_ERR_PHY;
+               }
+       } else {
+               /* We'll need to use the SW defined pins to shift the write command
+                * out to the PHY. We first send a preamble to the PHY to signal the
+                * beginning of the MII instruction.  This is done by sending 32
+                * consecutive "1" bits.
+                */
+               e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
+
+               /* Now combine the remaining required fields that will indicate a
+                * write operation. We use this method instead of calling the
+                * e1000_shift_out_mdi_bits routine for each field in the command. The
+                * format of a MII write instruction is as follows:
+                * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
+                */
+               mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
+                       (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
+               mdic <<= 16;
+               mdic |= (u32) phy_data;
+
+               e1000_shift_out_mdi_bits(hw, mdic, 32);
+       }
+
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
-* Returns the PHY to the power-on reset state
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
+/**
+ * e1000_phy_hw_reset - reset the phy, hardware style
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Returns the PHY to the power-on reset state
+ */
 s32 e1000_phy_hw_reset(struct e1000_hw *hw)
 {
-    u32 ctrl, ctrl_ext;
-    u32 led_ctrl;
-    s32 ret_val;
-
-    DEBUGFUNC("e1000_phy_hw_reset");
-
-    DEBUGOUT("Resetting Phy...\n");
-
-    if (hw->mac_type > e1000_82543) {
-        /* Read the device control register and assert the E1000_CTRL_PHY_RST
-         * bit. Then, take it out of reset.
-         * For e1000 hardware, we delay for 10ms between the assert
-         * and deassert.
-         */
-        ctrl = er32(CTRL);
-        ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
-        E1000_WRITE_FLUSH();
-
-        msleep(10);
-
-        ew32(CTRL, ctrl);
-        E1000_WRITE_FLUSH();
-    } else {
-        /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
-         * bit to put the PHY into reset. Then, take it out of reset.
-         */
-        ctrl_ext = er32(CTRL_EXT);
-        ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
-        ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
-        ew32(CTRL_EXT, ctrl_ext);
-        E1000_WRITE_FLUSH();
-        msleep(10);
-        ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
-        ew32(CTRL_EXT, ctrl_ext);
-        E1000_WRITE_FLUSH();
-    }
-    udelay(150);
-
-    if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
-        /* Configure activity LED after PHY reset */
-        led_ctrl = er32(LEDCTL);
-        led_ctrl &= IGP_ACTIVITY_LED_MASK;
-        led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
-        ew32(LEDCTL, led_ctrl);
-    }
-
-    /* Wait for FW to finish PHY configuration. */
-    ret_val = e1000_get_phy_cfg_done(hw);
-    if (ret_val != E1000_SUCCESS)
-        return ret_val;
-
-    return ret_val;
+       u32 ctrl, ctrl_ext;
+       u32 led_ctrl;
+       s32 ret_val;
+
+       DEBUGFUNC("e1000_phy_hw_reset");
+
+       DEBUGOUT("Resetting Phy...\n");
+
+       if (hw->mac_type > e1000_82543) {
+               /* Read the device control register and assert the E1000_CTRL_PHY_RST
+                * bit. Then, take it out of reset.
+                * For e1000 hardware, we delay for 10ms between the assert
+                * and deassert.
+                */
+               ctrl = er32(CTRL);
+               ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
+               E1000_WRITE_FLUSH();
+
+               msleep(10);
+
+               ew32(CTRL, ctrl);
+               E1000_WRITE_FLUSH();
+
+       } else {
+               /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
+                * bit to put the PHY into reset. Then, take it out of reset.
+                */
+               ctrl_ext = er32(CTRL_EXT);
+               ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
+               ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
+               ew32(CTRL_EXT, ctrl_ext);
+               E1000_WRITE_FLUSH();
+               msleep(10);
+               ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
+               ew32(CTRL_EXT, ctrl_ext);
+               E1000_WRITE_FLUSH();
+       }
+       udelay(150);
+
+       if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
+               /* Configure activity LED after PHY reset */
+               led_ctrl = er32(LEDCTL);
+               led_ctrl &= IGP_ACTIVITY_LED_MASK;
+               led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
+               ew32(LEDCTL, led_ctrl);
+       }
+
+       /* Wait for FW to finish PHY configuration. */
+       ret_val = e1000_get_phy_cfg_done(hw);
+       if (ret_val != E1000_SUCCESS)
+               return ret_val;
+
+       return ret_val;
 }
 
-/******************************************************************************
-* Resets the PHY
-*
-* hw - Struct containing variables accessed by shared code
-*
-* Sets bit 15 of the MII Control register
-******************************************************************************/
+/**
+ * e1000_phy_reset - reset the phy to commit settings
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Resets the PHY
+ * Sets bit 15 of the MII Control register
+ */
 s32 e1000_phy_reset(struct e1000_hw *hw)
 {
-    s32 ret_val;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_phy_reset");
-
-    switch (hw->phy_type) {
-    case e1000_phy_igp:
-        ret_val = e1000_phy_hw_reset(hw);
-        if (ret_val)
-            return ret_val;
-        break;
-    default:
-        ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        phy_data |= MII_CR_RESET;
-        ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
-        if (ret_val)
-            return ret_val;
-
-        udelay(1);
-        break;
-    }
-
-    if (hw->phy_type == e1000_phy_igp)
-        e1000_phy_init_script(hw);
-
-    return E1000_SUCCESS;
+       s32 ret_val;
+       u16 phy_data;
+
+       DEBUGFUNC("e1000_phy_reset");
+
+       switch (hw->phy_type) {
+       case e1000_phy_igp:
+               ret_val = e1000_phy_hw_reset(hw);
+               if (ret_val)
+                       return ret_val;
+               break;
+       default:
+               ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
+               if (ret_val)
+                       return ret_val;
+
+               phy_data |= MII_CR_RESET;
+               ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
+               if (ret_val)
+                       return ret_val;
+
+               udelay(1);
+               break;
+       }
+
+       if (hw->phy_type == e1000_phy_igp)
+               e1000_phy_init_script(hw);
+
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
-* Probes the expected PHY address for known PHY IDs
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
+/**
+ * e1000_detect_gig_phy - check the phy type
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Probes the expected PHY address for known PHY IDs
+ */
 static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
 {
-    s32 phy_init_status, ret_val;
-    u16 phy_id_high, phy_id_low;
-    bool match = false;
-
-    DEBUGFUNC("e1000_detect_gig_phy");
-
-    if (hw->phy_id != 0)
-        return E1000_SUCCESS;
-
-    /* Read the PHY ID Registers to identify which PHY is onboard. */
-    ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
-    if (ret_val)
-        return ret_val;
-
-    hw->phy_id = (u32)(phy_id_high << 16);
-    udelay(20);
-    ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
-    if (ret_val)
-        return ret_val;
-
-    hw->phy_id |= (u32)(phy_id_low & PHY_REVISION_MASK);
-    hw->phy_revision = (u32)phy_id_low & ~PHY_REVISION_MASK;
-
-    switch (hw->mac_type) {
-    case e1000_82543:
-        if (hw->phy_id == M88E1000_E_PHY_ID) match = true;
-        break;
-    case e1000_82544:
-        if (hw->phy_id == M88E1000_I_PHY_ID) match = true;
-        break;
-    case e1000_82540:
-    case e1000_82545:
-    case e1000_82545_rev_3:
-    case e1000_82546:
-    case e1000_82546_rev_3:
-        if (hw->phy_id == M88E1011_I_PHY_ID) match = true;
-        break;
-    case e1000_82541:
-    case e1000_82541_rev_2:
-    case e1000_82547:
-    case e1000_82547_rev_2:
-        if (hw->phy_id == IGP01E1000_I_PHY_ID) match = true;
-        break;
-    default:
-        DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
-        return -E1000_ERR_CONFIG;
-    }
-    phy_init_status = e1000_set_phy_type(hw);
-
-    if ((match) && (phy_init_status == E1000_SUCCESS)) {
-        DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
-        return E1000_SUCCESS;
-    }
-    DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
-    return -E1000_ERR_PHY;
+       s32 phy_init_status, ret_val;
+       u16 phy_id_high, phy_id_low;
+       bool match = false;
+
+       DEBUGFUNC("e1000_detect_gig_phy");
+
+       if (hw->phy_id != 0)
+               return E1000_SUCCESS;
+
+       /* Read the PHY ID Registers to identify which PHY is onboard. */
+       ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
+       if (ret_val)
+               return ret_val;
+
+       hw->phy_id = (u32) (phy_id_high << 16);
+       udelay(20);
+       ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
+       if (ret_val)
+               return ret_val;
+
+       hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK);
+       hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK;
+
+       switch (hw->mac_type) {
+       case e1000_82543:
+               if (hw->phy_id == M88E1000_E_PHY_ID)
+                       match = true;
+               break;
+       case e1000_82544:
+               if (hw->phy_id == M88E1000_I_PHY_ID)
+                       match = true;
+               break;
+       case e1000_82540:
+       case e1000_82545:
+       case e1000_82545_rev_3:
+       case e1000_82546:
+       case e1000_82546_rev_3:
+               if (hw->phy_id == M88E1011_I_PHY_ID)
+                       match = true;
+               break;
+       case e1000_82541:
+       case e1000_82541_rev_2:
+       case e1000_82547:
+       case e1000_82547_rev_2:
+               if (hw->phy_id == IGP01E1000_I_PHY_ID)
+                       match = true;
+               break;
+       default:
+               DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
+               return -E1000_ERR_CONFIG;
+       }
+       phy_init_status = e1000_set_phy_type(hw);
+
+       if ((match) && (phy_init_status == E1000_SUCCESS)) {
+               DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
+               return E1000_SUCCESS;
+       }
+       DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
+       return -E1000_ERR_PHY;
 }
 
-/******************************************************************************
-* Resets the PHY's DSP
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
+/**
+ * e1000_phy_reset_dsp - reset DSP
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Resets the PHY's DSP
+ */
 static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
 {
-    s32 ret_val;
-    DEBUGFUNC("e1000_phy_reset_dsp");
-
-    do {
-        ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
-        if (ret_val) break;
-        ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
-        if (ret_val) break;
-        ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
-        if (ret_val) break;
-        ret_val = E1000_SUCCESS;
-    } while (0);
-
-    return ret_val;
+       s32 ret_val;
+       DEBUGFUNC("e1000_phy_reset_dsp");
+
+       do {
+               ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
+               if (ret_val)
+                       break;
+               ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
+               if (ret_val)
+                       break;
+               ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
+               if (ret_val)
+                       break;
+               ret_val = E1000_SUCCESS;
+       } while (0);
+
+       return ret_val;
 }
 
-/******************************************************************************
-* Get PHY information from various PHY registers for igp PHY only.
-*
-* hw - Struct containing variables accessed by shared code
-* phy_info - PHY information structure
-******************************************************************************/
+/**
+ * e1000_phy_igp_get_info - get igp specific registers
+ * @hw: Struct containing variables accessed by shared code
+ * @phy_info: PHY information structure
+ *
+ * Get PHY information from various PHY registers for igp PHY only.
+ */
 static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
                                  struct e1000_phy_info *phy_info)
 {
-    s32 ret_val;
-    u16 phy_data, min_length, max_length, average;
-    e1000_rev_polarity polarity;
-
-    DEBUGFUNC("e1000_phy_igp_get_info");
-
-    /* The downshift status is checked only once, after link is established,
-     * and it stored in the hw->speed_downgraded parameter. */
-    phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
-
-    /* IGP01E1000 does not need to support it. */
-    phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
-
-    /* IGP01E1000 always correct polarity reversal */
-    phy_info->polarity_correction = e1000_polarity_reversal_enabled;
-
-    /* Check polarity status */
-    ret_val = e1000_check_polarity(hw, &polarity);
-    if (ret_val)
-        return ret_val;
-
-    phy_info->cable_polarity = polarity;
-
-    ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
-    if (ret_val)
-        return ret_val;
-
-    phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >>
-                          IGP01E1000_PSSR_MDIX_SHIFT);
-
-    if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
-       IGP01E1000_PSSR_SPEED_1000MBPS) {
-        /* Local/Remote Receiver Information are only valid at 1000 Mbps */
-        ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
-                             SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
-                             e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
-        phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
-                              SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
-                              e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
-
-        /* Get cable length */
-        ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
-        if (ret_val)
-            return ret_val;
-
-        /* Translate to old method */
-        average = (max_length + min_length) / 2;
-
-        if (average <= e1000_igp_cable_length_50)
-            phy_info->cable_length = e1000_cable_length_50;
-        else if (average <= e1000_igp_cable_length_80)
-            phy_info->cable_length = e1000_cable_length_50_80;
-        else if (average <= e1000_igp_cable_length_110)
-            phy_info->cable_length = e1000_cable_length_80_110;
-        else if (average <= e1000_igp_cable_length_140)
-            phy_info->cable_length = e1000_cable_length_110_140;
-        else
-            phy_info->cable_length = e1000_cable_length_140;
-    }
-
-    return E1000_SUCCESS;
-}
+       s32 ret_val;
+       u16 phy_data, min_length, max_length, average;
+       e1000_rev_polarity polarity;
+
+       DEBUGFUNC("e1000_phy_igp_get_info");
+
+       /* The downshift status is checked only once, after link is established,
+        * and it stored in the hw->speed_downgraded parameter. */
+       phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
+
+       /* IGP01E1000 does not need to support it. */
+       phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
+
+       /* IGP01E1000 always correct polarity reversal */
+       phy_info->polarity_correction = e1000_polarity_reversal_enabled;
+
+       /* Check polarity status */
+       ret_val = e1000_check_polarity(hw, &polarity);
+       if (ret_val)
+               return ret_val;
+
+       phy_info->cable_polarity = polarity;
+
+       ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
+       if (ret_val)
+               return ret_val;
+
+       phy_info->mdix_mode =
+           (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >>
+                                IGP01E1000_PSSR_MDIX_SHIFT);
+
+       if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
+           IGP01E1000_PSSR_SPEED_1000MBPS) {
+               /* Local/Remote Receiver Information are only valid at 1000 Mbps */
+               ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
+               if (ret_val)
+                       return ret_val;
+
+               phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
+                                     SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
+                   e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
+               phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
+                                      SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
+                   e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
+
+               /* Get cable length */
+               ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
+               if (ret_val)
+                       return ret_val;
+
+               /* Translate to old method */
+               average = (max_length + min_length) / 2;
+
+               if (average <= e1000_igp_cable_length_50)
+                       phy_info->cable_length = e1000_cable_length_50;
+               else if (average <= e1000_igp_cable_length_80)
+                       phy_info->cable_length = e1000_cable_length_50_80;
+               else if (average <= e1000_igp_cable_length_110)
+                       phy_info->cable_length = e1000_cable_length_80_110;
+               else if (average <= e1000_igp_cable_length_140)
+                       phy_info->cable_length = e1000_cable_length_110_140;
+               else
+                       phy_info->cable_length = e1000_cable_length_140;
+       }
 
+       return E1000_SUCCESS;
+}
 
-/******************************************************************************
-* Get PHY information from various PHY registers fot m88 PHY only.
-*
-* hw - Struct containing variables accessed by shared code
-* phy_info - PHY information structure
-******************************************************************************/
+/**
+ * e1000_phy_m88_get_info - get m88 specific registers
+ * @hw: Struct containing variables accessed by shared code
+ * @phy_info: PHY information structure
+ *
+ * Get PHY information from various PHY registers for m88 PHY only.
+ */
 static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
                                  struct e1000_phy_info *phy_info)
 {
-    s32 ret_val;
-    u16 phy_data;
-    e1000_rev_polarity polarity;
-
-    DEBUGFUNC("e1000_phy_m88_get_info");
-
-    /* The downshift status is checked only once, after link is established,
-     * and it stored in the hw->speed_downgraded parameter. */
-    phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
-
-    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
-    if (ret_val)
-        return ret_val;
-
-    phy_info->extended_10bt_distance =
-        ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
-        M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
-        e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal;
-
-    phy_info->polarity_correction =
-        ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
-        M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
-        e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
-
-    /* Check polarity status */
-    ret_val = e1000_check_polarity(hw, &polarity);
-    if (ret_val)
-        return ret_val;
-    phy_info->cable_polarity = polarity;
-
-    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
-    if (ret_val)
-        return ret_val;
-
-    phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >>
-                          M88E1000_PSSR_MDIX_SHIFT);
-
-    if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
-        /* Cable Length Estimation and Local/Remote Receiver Information
-         * are only valid at 1000 Mbps.
-         */
-        phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
-                                  M88E1000_PSSR_CABLE_LENGTH_SHIFT);
-
-        ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
-                             SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
-                             e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
-        phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
-                              SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
-                              e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
-
-    }
-
-    return E1000_SUCCESS;
+       s32 ret_val;
+       u16 phy_data;
+       e1000_rev_polarity polarity;
+
+       DEBUGFUNC("e1000_phy_m88_get_info");
+
+       /* The downshift status is checked only once, after link is established,
+        * and it stored in the hw->speed_downgraded parameter. */
+       phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
+
+       ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
+       if (ret_val)
+               return ret_val;
+
+       phy_info->extended_10bt_distance =
+           ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
+            M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
+           e1000_10bt_ext_dist_enable_lower :
+           e1000_10bt_ext_dist_enable_normal;
+
+       phy_info->polarity_correction =
+           ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
+            M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
+           e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
+
+       /* Check polarity status */
+       ret_val = e1000_check_polarity(hw, &polarity);
+       if (ret_val)
+               return ret_val;
+       phy_info->cable_polarity = polarity;
+
+       ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
+       if (ret_val)
+               return ret_val;
+
+       phy_info->mdix_mode =
+           (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >>
+                                M88E1000_PSSR_MDIX_SHIFT);
+
+       if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
+               /* Cable Length Estimation and Local/Remote Receiver Information
+                * are only valid at 1000 Mbps.
+                */
+               phy_info->cable_length =
+                   (e1000_cable_length) ((phy_data &
+                                          M88E1000_PSSR_CABLE_LENGTH) >>
+                                         M88E1000_PSSR_CABLE_LENGTH_SHIFT);
+
+               ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
+               if (ret_val)
+                       return ret_val;
+
+               phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
+                                     SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
+                   e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
+               phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
+                                      SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
+                   e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
+
+       }
+
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
-* Get PHY information from various PHY registers
-*
-* hw - Struct containing variables accessed by shared code
-* phy_info - PHY information structure
-******************************************************************************/
+/**
+ * e1000_phy_get_info - request phy info
+ * @hw: Struct containing variables accessed by shared code
+ * @phy_info: PHY information structure
+ *
+ * Get PHY information from various PHY registers
+ */
 s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
 {
-    s32 ret_val;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_phy_get_info");
-
-    phy_info->cable_length = e1000_cable_length_undefined;
-    phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
-    phy_info->cable_polarity = e1000_rev_polarity_undefined;
-    phy_info->downshift = e1000_downshift_undefined;
-    phy_info->polarity_correction = e1000_polarity_reversal_undefined;
-    phy_info->mdix_mode = e1000_auto_x_mode_undefined;
-    phy_info->local_rx = e1000_1000t_rx_status_undefined;
-    phy_info->remote_rx = e1000_1000t_rx_status_undefined;
-
-    if (hw->media_type != e1000_media_type_copper) {
-        DEBUGOUT("PHY info is only valid for copper media\n");
-        return -E1000_ERR_CONFIG;
-    }
-
-    ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-    if (ret_val)
-        return ret_val;
-
-    ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
-    if (ret_val)
-        return ret_val;
-
-    if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
-        DEBUGOUT("PHY info is only valid if link is up\n");
-        return -E1000_ERR_CONFIG;
-    }
-
-    if (hw->phy_type == e1000_phy_igp)
-        return e1000_phy_igp_get_info(hw, phy_info);
-    else
-        return e1000_phy_m88_get_info(hw, phy_info);
+       s32 ret_val;
+       u16 phy_data;
+
+       DEBUGFUNC("e1000_phy_get_info");
+
+       phy_info->cable_length = e1000_cable_length_undefined;
+       phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
+       phy_info->cable_polarity = e1000_rev_polarity_undefined;
+       phy_info->downshift = e1000_downshift_undefined;
+       phy_info->polarity_correction = e1000_polarity_reversal_undefined;
+       phy_info->mdix_mode = e1000_auto_x_mode_undefined;
+       phy_info->local_rx = e1000_1000t_rx_status_undefined;
+       phy_info->remote_rx = e1000_1000t_rx_status_undefined;
+
+       if (hw->media_type != e1000_media_type_copper) {
+               DEBUGOUT("PHY info is only valid for copper media\n");
+               return -E1000_ERR_CONFIG;
+       }
+
+       ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+       if (ret_val)
+               return ret_val;
+
+       ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
+       if (ret_val)
+               return ret_val;
+
+       if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
+               DEBUGOUT("PHY info is only valid if link is up\n");
+               return -E1000_ERR_CONFIG;
+       }
+
+       if (hw->phy_type == e1000_phy_igp)
+               return e1000_phy_igp_get_info(hw, phy_info);
+       else
+               return e1000_phy_m88_get_info(hw, phy_info);
 }
 
 s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
 {
-    DEBUGFUNC("e1000_validate_mdi_settings");
-
-    if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
-        DEBUGOUT("Invalid MDI setting detected\n");
-        hw->mdix = 1;
-        return -E1000_ERR_CONFIG;
-    }
-    return E1000_SUCCESS;
-}
+       DEBUGFUNC("e1000_validate_mdi_settings");
 
+       if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
+               DEBUGOUT("Invalid MDI setting detected\n");
+               hw->mdix = 1;
+               return -E1000_ERR_CONFIG;
+       }
+       return E1000_SUCCESS;
+}
 
-/******************************************************************************
+/**
+ * e1000_init_eeprom_params - initialize sw eeprom vars
+ * @hw: Struct containing variables accessed by shared code
+ *
  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
  * is configured.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+ */
 s32 e1000_init_eeprom_params(struct e1000_hw *hw)
 {
-    struct e1000_eeprom_info *eeprom = &hw->eeprom;
-    u32 eecd = er32(EECD);
-    s32 ret_val = E1000_SUCCESS;
-    u16 eeprom_size;
-
-    DEBUGFUNC("e1000_init_eeprom_params");
-
-    switch (hw->mac_type) {
-    case e1000_82542_rev2_0:
-    case e1000_82542_rev2_1:
-    case e1000_82543:
-    case e1000_82544:
-        eeprom->type = e1000_eeprom_microwire;
-        eeprom->word_size = 64;
-        eeprom->opcode_bits = 3;
-        eeprom->address_bits = 6;
-        eeprom->delay_usec = 50;
-        eeprom->use_eerd = false;
-        eeprom->use_eewr = false;
-        break;
-    case e1000_82540:
-    case e1000_82545:
-    case e1000_82545_rev_3:
-    case e1000_82546:
-    case e1000_82546_rev_3:
-        eeprom->type = e1000_eeprom_microwire;
-        eeprom->opcode_bits = 3;
-        eeprom->delay_usec = 50;
-        if (eecd & E1000_EECD_SIZE) {
-            eeprom->word_size = 256;
-            eeprom->address_bits = 8;
-        } else {
-            eeprom->word_size = 64;
-            eeprom->address_bits = 6;
-        }
-        eeprom->use_eerd = false;
-        eeprom->use_eewr = false;
-        break;
-    case e1000_82541:
-    case e1000_82541_rev_2:
-    case e1000_82547:
-    case e1000_82547_rev_2:
-        if (eecd & E1000_EECD_TYPE) {
-            eeprom->type = e1000_eeprom_spi;
-            eeprom->opcode_bits = 8;
-            eeprom->delay_usec = 1;
-            if (eecd & E1000_EECD_ADDR_BITS) {
-                eeprom->page_size = 32;
-                eeprom->address_bits = 16;
-            } else {
-                eeprom->page_size = 8;
-                eeprom->address_bits = 8;
-            }
-        } else {
-            eeprom->type = e1000_eeprom_microwire;
-            eeprom->opcode_bits = 3;
-            eeprom->delay_usec = 50;
-            if (eecd & E1000_EECD_ADDR_BITS) {
-                eeprom->word_size = 256;
-                eeprom->address_bits = 8;
-            } else {
-                eeprom->word_size = 64;
-                eeprom->address_bits = 6;
-            }
-        }
-        eeprom->use_eerd = false;
-        eeprom->use_eewr = false;
-        break;
-    default:
-        break;
-    }
-
-    if (eeprom->type == e1000_eeprom_spi) {
-        /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
-         * 32KB (incremented by powers of 2).
-         */
-        /* Set to default value for initial eeprom read. */
-        eeprom->word_size = 64;
-        ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
-        if (ret_val)
-            return ret_val;
-        eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
-        /* 256B eeprom size was not supported in earlier hardware, so we
-         * bump eeprom_size up one to ensure that "1" (which maps to 256B)
-         * is never the result used in the shifting logic below. */
-        if (eeprom_size)
-            eeprom_size++;
-
-        eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
-    }
-    return ret_val;
+       struct e1000_eeprom_info *eeprom = &hw->eeprom;
+       u32 eecd = er32(EECD);
+       s32 ret_val = E1000_SUCCESS;
+       u16 eeprom_size;
+
+       DEBUGFUNC("e1000_init_eeprom_params");
+
+       switch (hw->mac_type) {
+       case e1000_82542_rev2_0:
+       case e1000_82542_rev2_1:
+       case e1000_82543:
+       case e1000_82544:
+               eeprom->type = e1000_eeprom_microwire;
+               eeprom->word_size = 64;
+               eeprom->opcode_bits = 3;
+               eeprom->address_bits = 6;
+               eeprom->delay_usec = 50;
+               eeprom->use_eerd = false;
+               eeprom->use_eewr = false;
+               break;
+       case e1000_82540:
+       case e1000_82545:
+       case e1000_82545_rev_3:
+       case e1000_82546:
+       case e1000_82546_rev_3:
+               eeprom->type = e1000_eeprom_microwire;
+               eeprom->opcode_bits = 3;
+               eeprom->delay_usec = 50;
+               if (eecd & E1000_EECD_SIZE) {
+                       eeprom->word_size = 256;
+                       eeprom->address_bits = 8;
+               } else {
+                       eeprom->word_size = 64;
+                       eeprom->address_bits = 6;
+               }
+               eeprom->use_eerd = false;
+               eeprom->use_eewr = false;
+               break;
+       case e1000_82541:
+       case e1000_82541_rev_2:
+       case e1000_82547:
+       case e1000_82547_rev_2:
+               if (eecd & E1000_EECD_TYPE) {
+                       eeprom->type = e1000_eeprom_spi;
+                       eeprom->opcode_bits = 8;
+                       eeprom->delay_usec = 1;
+                       if (eecd & E1000_EECD_ADDR_BITS) {
+                               eeprom->page_size = 32;
+                               eeprom->address_bits = 16;
+                       } else {
+                               eeprom->page_size = 8;
+                               eeprom->address_bits = 8;
+                       }
+               } else {
+                       eeprom->type = e1000_eeprom_microwire;
+                       eeprom->opcode_bits = 3;
+                       eeprom->delay_usec = 50;
+                       if (eecd & E1000_EECD_ADDR_BITS) {
+                               eeprom->word_size = 256;
+                               eeprom->address_bits = 8;
+                       } else {
+                               eeprom->word_size = 64;
+                               eeprom->address_bits = 6;
+                       }
+               }
+               eeprom->use_eerd = false;
+               eeprom->use_eewr = false;
+               break;
+       default:
+               break;
+       }
+
+       if (eeprom->type == e1000_eeprom_spi) {
+               /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
+                * 32KB (incremented by powers of 2).
+                */
+               /* Set to default value for initial eeprom read. */
+               eeprom->word_size = 64;
+               ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
+               if (ret_val)
+                       return ret_val;
+               eeprom_size =
+                   (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
+               /* 256B eeprom size was not supported in earlier hardware, so we
+                * bump eeprom_size up one to ensure that "1" (which maps to 256B)
+                * is never the result used in the shifting logic below. */
+               if (eeprom_size)
+                       eeprom_size++;
+
+               eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
+       }
+       return ret_val;
 }
 
-/******************************************************************************
- * Raises the EEPROM's clock input.
- *
- * hw - Struct containing variables accessed by shared code
- * eecd - EECD's current value
- *****************************************************************************/
+/**
+ * e1000_raise_ee_clk - Raises the EEPROM's clock input.
+ * @hw: Struct containing variables accessed by shared code
+ * @eecd: EECD's current value
+ */
 static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)
 {
-    /* Raise the clock input to the EEPROM (by setting the SK bit), and then
-     * wait <delay> microseconds.
-     */
-    *eecd = *eecd | E1000_EECD_SK;
-    ew32(EECD, *eecd);
-    E1000_WRITE_FLUSH();
-    udelay(hw->eeprom.delay_usec);
+       /* Raise the clock input to the EEPROM (by setting the SK bit), and then
+        * wait <delay> microseconds.
+        */
+       *eecd = *eecd | E1000_EECD_SK;
+       ew32(EECD, *eecd);
+       E1000_WRITE_FLUSH();
+       udelay(hw->eeprom.delay_usec);
 }
 
-/******************************************************************************
- * Lowers the EEPROM's clock input.
- *
- * hw - Struct containing variables accessed by shared code
- * eecd - EECD's current value
- *****************************************************************************/
+/**
+ * e1000_lower_ee_clk - Lowers the EEPROM's clock input.
+ * @hw: Struct containing variables accessed by shared code
+ * @eecd: EECD's current value
+ */
 static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)
 {
-    /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
-     * wait 50 microseconds.
-     */
-    *eecd = *eecd & ~E1000_EECD_SK;
-    ew32(EECD, *eecd);
-    E1000_WRITE_FLUSH();
-    udelay(hw->eeprom.delay_usec);
+       /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
+        * wait 50 microseconds.
+        */
+       *eecd = *eecd & ~E1000_EECD_SK;
+       ew32(EECD, *eecd);
+       E1000_WRITE_FLUSH();
+       udelay(hw->eeprom.delay_usec);
 }
 
-/******************************************************************************
- * Shift data bits out to the EEPROM.
- *
- * hw - Struct containing variables accessed by shared code
- * data - data to send to the EEPROM
- * count - number of bits to shift out
- *****************************************************************************/
+/**
+ * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM.
+ * @hw: Struct containing variables accessed by shared code
+ * @data: data to send to the EEPROM
+ * @count: number of bits to shift out
+ */
 static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
 {
-    struct e1000_eeprom_info *eeprom = &hw->eeprom;
-    u32 eecd;
-    u32 mask;
-
-    /* We need to shift "count" bits out to the EEPROM. So, value in the
-     * "data" parameter will be shifted out to the EEPROM one bit at a time.
-     * In order to do this, "data" must be broken down into bits.
-     */
-    mask = 0x01 << (count - 1);
-    eecd = er32(EECD);
-    if (eeprom->type == e1000_eeprom_microwire) {
-        eecd &= ~E1000_EECD_DO;
-    } else if (eeprom->type == e1000_eeprom_spi) {
-        eecd |= E1000_EECD_DO;
-    }
-    do {
-        /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
-         * and then raising and then lowering the clock (the SK bit controls
-         * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
-         * by setting "DI" to "0" and then raising and then lowering the clock.
-         */
-        eecd &= ~E1000_EECD_DI;
-
-        if (data & mask)
-            eecd |= E1000_EECD_DI;
-
-        ew32(EECD, eecd);
-        E1000_WRITE_FLUSH();
-
-        udelay(eeprom->delay_usec);
-
-        e1000_raise_ee_clk(hw, &eecd);
-        e1000_lower_ee_clk(hw, &eecd);
-
-        mask = mask >> 1;
-
-    } while (mask);
-
-    /* We leave the "DI" bit set to "0" when we leave this routine. */
-    eecd &= ~E1000_EECD_DI;
-    ew32(EECD, eecd);
+       struct e1000_eeprom_info *eeprom = &hw->eeprom;
+       u32 eecd;
+       u32 mask;
+
+       /* We need to shift "count" bits out to the EEPROM. So, value in the
+        * "data" parameter will be shifted out to the EEPROM one bit at a time.
+        * In order to do this, "data" must be broken down into bits.
+        */
+       mask = 0x01 << (count - 1);
+       eecd = er32(EECD);
+       if (eeprom->type == e1000_eeprom_microwire) {
+               eecd &= ~E1000_EECD_DO;
+       } else if (eeprom->type == e1000_eeprom_spi) {
+               eecd |= E1000_EECD_DO;
+       }
+       do {
+               /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
+                * and then raising and then lowering the clock (the SK bit controls
+                * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
+                * by setting "DI" to "0" and then raising and then lowering the clock.
+                */
+               eecd &= ~E1000_EECD_DI;
+
+               if (data & mask)
+                       eecd |= E1000_EECD_DI;
+
+               ew32(EECD, eecd);
+               E1000_WRITE_FLUSH();
+
+               udelay(eeprom->delay_usec);
+
+               e1000_raise_ee_clk(hw, &eecd);
+               e1000_lower_ee_clk(hw, &eecd);
+
+               mask = mask >> 1;
+
+       } while (mask);
+
+       /* We leave the "DI" bit set to "0" when we leave this routine. */
+       eecd &= ~E1000_EECD_DI;
+       ew32(EECD, eecd);
 }
 
-/******************************************************************************
- * Shift data bits in from the EEPROM
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+/**
+ * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM
+ * @hw: Struct containing variables accessed by shared code
+ * @count: number of bits to shift in
+ */
 static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
 {
-    u32 eecd;
-    u32 i;
-    u16 data;
-
-    /* In order to read a register from the EEPROM, we need to shift 'count'
-     * bits in from the EEPROM. Bits are "shifted in" by raising the clock
-     * input to the EEPROM (setting the SK bit), and then reading the value of
-     * the "DO" bit.  During this "shifting in" process the "DI" bit should
-     * always be clear.
-     */
+       u32 eecd;
+       u32 i;
+       u16 data;
+
+       /* In order to read a register from the EEPROM, we need to shift 'count'
+        * bits in from the EEPROM. Bits are "shifted in" by raising the clock
+        * input to the EEPROM (setting the SK bit), and then reading the value of
+        * the "DO" bit.  During this "shifting in" process the "DI" bit should
+        * always be clear.
+        */
 
-    eecd = er32(EECD);
+       eecd = er32(EECD);
 
-    eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
-    data = 0;
+       eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
+       data = 0;
 
-    for (i = 0; i < count; i++) {
-        data = data << 1;
-        e1000_raise_ee_clk(hw, &eecd);
+       for (i = 0; i < count; i++) {
+               data = data << 1;
+               e1000_raise_ee_clk(hw, &eecd);
 
-        eecd = er32(EECD);
+               eecd = er32(EECD);
 
-        eecd &= ~(E1000_EECD_DI);
-        if (eecd & E1000_EECD_DO)
-            data |= 1;
+               eecd &= ~(E1000_EECD_DI);
+               if (eecd & E1000_EECD_DO)
+                       data |= 1;
 
-        e1000_lower_ee_clk(hw, &eecd);
-    }
+               e1000_lower_ee_clk(hw, &eecd);
+       }
 
-    return data;
+       return data;
 }
 
-/******************************************************************************
- * Prepares EEPROM for access
- *
- * hw - Struct containing variables accessed by shared code
+/**
+ * e1000_acquire_eeprom - Prepares EEPROM for access
+ * @hw: Struct containing variables accessed by shared code
  *
  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
  * function should be called before issuing a command to the EEPROM.
- *****************************************************************************/
+ */
 static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
 {
-    struct e1000_eeprom_info *eeprom = &hw->eeprom;
-    u32 eecd, i=0;
-
-    DEBUGFUNC("e1000_acquire_eeprom");
-
-    eecd = er32(EECD);
-
-    /* Request EEPROM Access */
-    if (hw->mac_type > e1000_82544) {
-        eecd |= E1000_EECD_REQ;
-        ew32(EECD, eecd);
-        eecd = er32(EECD);
-        while ((!(eecd & E1000_EECD_GNT)) &&
-               (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
-            i++;
-            udelay(5);
-            eecd = er32(EECD);
-        }
-        if (!(eecd & E1000_EECD_GNT)) {
-            eecd &= ~E1000_EECD_REQ;
-            ew32(EECD, eecd);
-            DEBUGOUT("Could not acquire EEPROM grant\n");
-            return -E1000_ERR_EEPROM;
-        }
-    }
-
-    /* Setup EEPROM for Read/Write */
-
-    if (eeprom->type == e1000_eeprom_microwire) {
-        /* Clear SK and DI */
-        eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
-        ew32(EECD, eecd);
-
-        /* Set CS */
-        eecd |= E1000_EECD_CS;
-        ew32(EECD, eecd);
-    } else if (eeprom->type == e1000_eeprom_spi) {
-        /* Clear SK and CS */
-        eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
-        ew32(EECD, eecd);
-        udelay(1);
-    }
-
-    return E1000_SUCCESS;
+       struct e1000_eeprom_info *eeprom = &hw->eeprom;
+       u32 eecd, i = 0;
+
+       DEBUGFUNC("e1000_acquire_eeprom");
+
+       eecd = er32(EECD);
+
+       /* Request EEPROM Access */
+       if (hw->mac_type > e1000_82544) {
+               eecd |= E1000_EECD_REQ;
+               ew32(EECD, eecd);
+               eecd = er32(EECD);
+               while ((!(eecd & E1000_EECD_GNT)) &&
+                      (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
+                       i++;
+                       udelay(5);
+                       eecd = er32(EECD);
+               }
+               if (!(eecd & E1000_EECD_GNT)) {
+                       eecd &= ~E1000_EECD_REQ;
+                       ew32(EECD, eecd);
+                       DEBUGOUT("Could not acquire EEPROM grant\n");
+                       return -E1000_ERR_EEPROM;
+               }
+       }
+
+       /* Setup EEPROM for Read/Write */
+
+       if (eeprom->type == e1000_eeprom_microwire) {
+               /* Clear SK and DI */
+               eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
+               ew32(EECD, eecd);
+
+               /* Set CS */
+               eecd |= E1000_EECD_CS;
+               ew32(EECD, eecd);
+       } else if (eeprom->type == e1000_eeprom_spi) {
+               /* Clear SK and CS */
+               eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
+               ew32(EECD, eecd);
+               udelay(1);
+       }
+
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Returns EEPROM to a "standby" state
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+/**
+ * e1000_standby_eeprom - Returns EEPROM to a "standby" state
+ * @hw: Struct containing variables accessed by shared code
+ */
 static void e1000_standby_eeprom(struct e1000_hw *hw)
 {
-    struct e1000_eeprom_info *eeprom = &hw->eeprom;
-    u32 eecd;
-
-    eecd = er32(EECD);
-
-    if (eeprom->type == e1000_eeprom_microwire) {
-        eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
-        ew32(EECD, eecd);
-        E1000_WRITE_FLUSH();
-        udelay(eeprom->delay_usec);
-
-        /* Clock high */
-        eecd |= E1000_EECD_SK;
-        ew32(EECD, eecd);
-        E1000_WRITE_FLUSH();
-        udelay(eeprom->delay_usec);
-
-        /* Select EEPROM */
-        eecd |= E1000_EECD_CS;
-        ew32(EECD, eecd);
-        E1000_WRITE_FLUSH();
-        udelay(eeprom->delay_usec);
-
-        /* Clock low */
-        eecd &= ~E1000_EECD_SK;
-        ew32(EECD, eecd);
-        E1000_WRITE_FLUSH();
-        udelay(eeprom->delay_usec);
-    } else if (eeprom->type == e1000_eeprom_spi) {
-        /* Toggle CS to flush commands */
-        eecd |= E1000_EECD_CS;
-        ew32(EECD, eecd);
-        E1000_WRITE_FLUSH();
-        udelay(eeprom->delay_usec);
-        eecd &= ~E1000_EECD_CS;
-        ew32(EECD, eecd);
-        E1000_WRITE_FLUSH();
-        udelay(eeprom->delay_usec);
-    }
+       struct e1000_eeprom_info *eeprom = &hw->eeprom;
+       u32 eecd;
+
+       eecd = er32(EECD);
+
+       if (eeprom->type == e1000_eeprom_microwire) {
+               eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
+               ew32(EECD, eecd);
+               E1000_WRITE_FLUSH();
+               udelay(eeprom->delay_usec);
+
+               /* Clock high */
+               eecd |= E1000_EECD_SK;
+               ew32(EECD, eecd);
+               E1000_WRITE_FLUSH();
+               udelay(eeprom->delay_usec);
+
+               /* Select EEPROM */
+               eecd |= E1000_EECD_CS;
+               ew32(EECD, eecd);
+               E1000_WRITE_FLUSH();
+               udelay(eeprom->delay_usec);
+
+               /* Clock low */
+               eecd &= ~E1000_EECD_SK;
+               ew32(EECD, eecd);
+               E1000_WRITE_FLUSH();
+               udelay(eeprom->delay_usec);
+       } else if (eeprom->type == e1000_eeprom_spi) {
+               /* Toggle CS to flush commands */
+               eecd |= E1000_EECD_CS;
+               ew32(EECD, eecd);
+               E1000_WRITE_FLUSH();
+               udelay(eeprom->delay_usec);
+               eecd &= ~E1000_EECD_CS;
+               ew32(EECD, eecd);
+               E1000_WRITE_FLUSH();
+               udelay(eeprom->delay_usec);
+       }
 }
 
-/******************************************************************************
- * Terminates a command by inverting the EEPROM's chip select pin
+/**
+ * e1000_release_eeprom - drop chip select
+ * @hw: Struct containing variables accessed by shared code
  *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+ * Terminates a command by inverting the EEPROM's chip select pin
+ */
 static void e1000_release_eeprom(struct e1000_hw *hw)
 {
-    u32 eecd;
+       u32 eecd;
 
-    DEBUGFUNC("e1000_release_eeprom");
+       DEBUGFUNC("e1000_release_eeprom");
 
-    eecd = er32(EECD);
+       eecd = er32(EECD);
 
-    if (hw->eeprom.type == e1000_eeprom_spi) {
-        eecd |= E1000_EECD_CS;  /* Pull CS high */
-        eecd &= ~E1000_EECD_SK; /* Lower SCK */
+       if (hw->eeprom.type == e1000_eeprom_spi) {
+               eecd |= E1000_EECD_CS;  /* Pull CS high */
+               eecd &= ~E1000_EECD_SK; /* Lower SCK */
 
-        ew32(EECD, eecd);
+               ew32(EECD, eecd);
 
-        udelay(hw->eeprom.delay_usec);
-    } else if (hw->eeprom.type == e1000_eeprom_microwire) {
-        /* cleanup eeprom */
+               udelay(hw->eeprom.delay_usec);
+       } else if (hw->eeprom.type == e1000_eeprom_microwire) {
+               /* cleanup eeprom */
 
-        /* CS on Microwire is active-high */
-        eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
+               /* CS on Microwire is active-high */
+               eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
 
-        ew32(EECD, eecd);
+               ew32(EECD, eecd);
 
-        /* Rising edge of clock */
-        eecd |= E1000_EECD_SK;
-        ew32(EECD, eecd);
-        E1000_WRITE_FLUSH();
-        udelay(hw->eeprom.delay_usec);
+               /* Rising edge of clock */
+               eecd |= E1000_EECD_SK;
+               ew32(EECD, eecd);
+               E1000_WRITE_FLUSH();
+               udelay(hw->eeprom.delay_usec);
 
-        /* Falling edge of clock */
-        eecd &= ~E1000_EECD_SK;
-        ew32(EECD, eecd);
-        E1000_WRITE_FLUSH();
-        udelay(hw->eeprom.delay_usec);
-    }
+               /* Falling edge of clock */
+               eecd &= ~E1000_EECD_SK;
+               ew32(EECD, eecd);
+               E1000_WRITE_FLUSH();
+               udelay(hw->eeprom.delay_usec);
+       }
 
-    /* Stop requesting EEPROM access */
-    if (hw->mac_type > e1000_82544) {
-        eecd &= ~E1000_EECD_REQ;
-        ew32(EECD, eecd);
-    }
+       /* Stop requesting EEPROM access */
+       if (hw->mac_type > e1000_82544) {
+               eecd &= ~E1000_EECD_REQ;
+               ew32(EECD, eecd);
+       }
 }
 
-/******************************************************************************
- * Reads a 16 bit word from the EEPROM.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+/**
+ * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM.
+ * @hw: Struct containing variables accessed by shared code
+ */
 static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
 {
-    u16 retry_count = 0;
-    u8 spi_stat_reg;
-
-    DEBUGFUNC("e1000_spi_eeprom_ready");
-
-    /* Read "Status Register" repeatedly until the LSB is cleared.  The
-     * EEPROM will signal that the command has been completed by clearing
-     * bit 0 of the internal status register.  If it's not cleared within
-     * 5 milliseconds, then error out.
-     */
-    retry_count = 0;
-    do {
-        e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
-                                hw->eeprom.opcode_bits);
-        spi_stat_reg = (u8)e1000_shift_in_ee_bits(hw, 8);
-        if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
-            break;
-
-        udelay(5);
-        retry_count += 5;
-
-        e1000_standby_eeprom(hw);
-    } while (retry_count < EEPROM_MAX_RETRY_SPI);
-
-    /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
-     * only 0-5mSec on 5V devices)
-     */
-    if (retry_count >= EEPROM_MAX_RETRY_SPI) {
-        DEBUGOUT("SPI EEPROM Status error\n");
-        return -E1000_ERR_EEPROM;
-    }
-
-    return E1000_SUCCESS;
+       u16 retry_count = 0;
+       u8 spi_stat_reg;
+
+       DEBUGFUNC("e1000_spi_eeprom_ready");
+
+       /* Read "Status Register" repeatedly until the LSB is cleared.  The
+        * EEPROM will signal that the command has been completed by clearing
+        * bit 0 of the internal status register.  If it's not cleared within
+        * 5 milliseconds, then error out.
+        */
+       retry_count = 0;
+       do {
+               e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
+                                       hw->eeprom.opcode_bits);
+               spi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8);
+               if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
+                       break;
+
+               udelay(5);
+               retry_count += 5;
+
+               e1000_standby_eeprom(hw);
+       } while (retry_count < EEPROM_MAX_RETRY_SPI);
+
+       /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
+        * only 0-5mSec on 5V devices)
+        */
+       if (retry_count >= EEPROM_MAX_RETRY_SPI) {
+               DEBUGOUT("SPI EEPROM Status error\n");
+               return -E1000_ERR_EEPROM;
+       }
+
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Reads a 16 bit word from the EEPROM.
- *
- * hw - Struct containing variables accessed by shared code
- * offset - offset of  word in the EEPROM to read
- * data - word read from the EEPROM
- * words - number of words to read
- *****************************************************************************/
+/**
+ * e1000_read_eeprom - Reads a 16 bit word from the EEPROM.
+ * @hw: Struct containing variables accessed by shared code
+ * @offset: offset of  word in the EEPROM to read
+ * @data: word read from the EEPROM
+ * @words: number of words to read
+ */
 s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 {
-    s32 ret;
-    spin_lock(&e1000_eeprom_lock);
-    ret = e1000_do_read_eeprom(hw, offset, words, data);
-    spin_unlock(&e1000_eeprom_lock);
-    return ret;
+       s32 ret;
+       spin_lock(&e1000_eeprom_lock);
+       ret = e1000_do_read_eeprom(hw, offset, words, data);
+       spin_unlock(&e1000_eeprom_lock);
+       return ret;
 }
 
-static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
+static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
+                               u16 *data)
 {
-    struct e1000_eeprom_info *eeprom = &hw->eeprom;
-    u32 i = 0;
-
-    DEBUGFUNC("e1000_read_eeprom");
-
-    /* If eeprom is not yet detected, do so now */
-    if (eeprom->word_size == 0)
-        e1000_init_eeprom_params(hw);
-
-    /* A check for invalid values:  offset too large, too many words, and not
-     * enough words.
-     */
-    if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
-       (words == 0)) {
-        DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size);
-        return -E1000_ERR_EEPROM;
-    }
-
-    /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
-     * directly. In this case, we need to acquire the EEPROM so that
-     * FW or other port software does not interrupt.
-     */
-    if (!hw->eeprom.use_eerd) {
-        /* Prepare the EEPROM for bit-bang reading */
-        if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
-            return -E1000_ERR_EEPROM;
-    }
-
-    /* Eerd register EEPROM access requires no eeprom aquire/release */
-    if (eeprom->use_eerd)
-        return e1000_read_eeprom_eerd(hw, offset, words, data);
-
-    /* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
-     * acquired the EEPROM at this point, so any returns should relase it */
-    if (eeprom->type == e1000_eeprom_spi) {
-        u16 word_in;
-        u8 read_opcode = EEPROM_READ_OPCODE_SPI;
-
-        if (e1000_spi_eeprom_ready(hw)) {
-            e1000_release_eeprom(hw);
-            return -E1000_ERR_EEPROM;
-        }
-
-        e1000_standby_eeprom(hw);
-
-        /* Some SPI eeproms use the 8th address bit embedded in the opcode */
-        if ((eeprom->address_bits == 8) && (offset >= 128))
-            read_opcode |= EEPROM_A8_OPCODE_SPI;
-
-        /* Send the READ command (opcode + addr)  */
-        e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
-        e1000_shift_out_ee_bits(hw, (u16)(offset*2), eeprom->address_bits);
-
-        /* Read the data.  The address of the eeprom internally increments with
-         * each byte (spi) being read, saving on the overhead of eeprom setup
-         * and tear-down.  The address counter will roll over if reading beyond
-         * the size of the eeprom, thus allowing the entire memory to be read
-         * starting from any offset. */
-        for (i = 0; i < words; i++) {
-            word_in = e1000_shift_in_ee_bits(hw, 16);
-            data[i] = (word_in >> 8) | (word_in << 8);
-        }
-    } else if (eeprom->type == e1000_eeprom_microwire) {
-        for (i = 0; i < words; i++) {
-            /* Send the READ command (opcode + addr)  */
-            e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
-                                    eeprom->opcode_bits);
-            e1000_shift_out_ee_bits(hw, (u16)(offset + i),
-                                    eeprom->address_bits);
-
-            /* Read the data.  For microwire, each word requires the overhead
-             * of eeprom setup and tear-down. */
-            data[i] = e1000_shift_in_ee_bits(hw, 16);
-            e1000_standby_eeprom(hw);
-        }
-    }
-
-    /* End this read operation */
-    e1000_release_eeprom(hw);
-
-    return E1000_SUCCESS;
+       struct e1000_eeprom_info *eeprom = &hw->eeprom;
+       u32 i = 0;
+
+       DEBUGFUNC("e1000_read_eeprom");
+
+       /* If eeprom is not yet detected, do so now */
+       if (eeprom->word_size == 0)
+               e1000_init_eeprom_params(hw);
+
+       /* A check for invalid values:  offset too large, too many words, and not
+        * enough words.
+        */
+       if ((offset >= eeprom->word_size)
+           || (words > eeprom->word_size - offset) || (words == 0)) {
+               DEBUGOUT2
+                   ("\"words\" parameter out of bounds. Words = %d, size = %d\n",
+                    offset, eeprom->word_size);
+               return -E1000_ERR_EEPROM;
+       }
+
+       /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
+        * directly. In this case, we need to acquire the EEPROM so that
+        * FW or other port software does not interrupt.
+        */
+       if (!hw->eeprom.use_eerd) {
+               /* Prepare the EEPROM for bit-bang reading */
+               if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
+                       return -E1000_ERR_EEPROM;
+       }
+
+       /* Eerd register EEPROM access requires no eeprom aquire/release */
+       if (eeprom->use_eerd)
+               return e1000_read_eeprom_eerd(hw, offset, words, data);
+
+       /* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
+        * acquired the EEPROM at this point, so any returns should release it */
+       if (eeprom->type == e1000_eeprom_spi) {
+               u16 word_in;
+               u8 read_opcode = EEPROM_READ_OPCODE_SPI;
+
+               if (e1000_spi_eeprom_ready(hw)) {
+                       e1000_release_eeprom(hw);
+                       return -E1000_ERR_EEPROM;
+               }
+
+               e1000_standby_eeprom(hw);
+
+               /* Some SPI eeproms use the 8th address bit embedded in the opcode */
+               if ((eeprom->address_bits == 8) && (offset >= 128))
+                       read_opcode |= EEPROM_A8_OPCODE_SPI;
+
+               /* Send the READ command (opcode + addr)  */
+               e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
+               e1000_shift_out_ee_bits(hw, (u16) (offset * 2),
+                                       eeprom->address_bits);
+
+               /* Read the data.  The address of the eeprom internally increments with
+                * each byte (spi) being read, saving on the overhead of eeprom setup
+                * and tear-down.  The address counter will roll over if reading beyond
+                * the size of the eeprom, thus allowing the entire memory to be read
+                * starting from any offset. */
+               for (i = 0; i < words; i++) {
+                       word_in = e1000_shift_in_ee_bits(hw, 16);
+                       data[i] = (word_in >> 8) | (word_in << 8);
+               }
+       } else if (eeprom->type == e1000_eeprom_microwire) {
+               for (i = 0; i < words; i++) {
+                       /* Send the READ command (opcode + addr)  */
+                       e1000_shift_out_ee_bits(hw,
+                                               EEPROM_READ_OPCODE_MICROWIRE,
+                                               eeprom->opcode_bits);
+                       e1000_shift_out_ee_bits(hw, (u16) (offset + i),
+                                               eeprom->address_bits);
+
+                       /* Read the data.  For microwire, each word requires the overhead
+                        * of eeprom setup and tear-down. */
+                       data[i] = e1000_shift_in_ee_bits(hw, 16);
+                       e1000_standby_eeprom(hw);
+               }
+       }
+
+       /* End this read operation */
+       e1000_release_eeprom(hw);
+
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
+/**
  * Reads a 16 bit word from the EEPROM using the EERD register.
  *
- * hw - Struct containing variables accessed by shared code
+ * @hw: Struct containing variables accessed by shared code
  * offset - offset of  word in the EEPROM to read
  * data - word read from the EEPROM
  * words - number of words to read
- *****************************************************************************/
+ */
 static s32 e1000_read_eeprom_eerd(struct e1000_hw *hw, u16 offset, u16 words,
                                  u16 *data)
 {
-    u32 i, eerd = 0;
-    s32 error = 0;
+       u32 i, eerd = 0;
+       s32 error = 0;
 
-    for (i = 0; i < words; i++) {
-        eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
-                         E1000_EEPROM_RW_REG_START;
+       for (i = 0; i < words; i++) {
+               eerd = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) +
+                   E1000_EEPROM_RW_REG_START;
 
-        ew32(EERD, eerd);
-        error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
+               ew32(EERD, eerd);
+               error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
 
-        if (error) {
-            break;
-        }
-        data[i] = (er32(EERD) >> E1000_EEPROM_RW_REG_DATA);
+               if (error) {
+                       break;
+               }
+               data[i] = (er32(EERD) >> E1000_EEPROM_RW_REG_DATA);
 
-    }
+       }
 
-    return error;
+       return error;
 }
 
-/******************************************************************************
+/**
  * Writes a 16 bit word from the EEPROM using the EEWR register.
  *
- * hw - Struct containing variables accessed by shared code
+ * @hw: Struct containing variables accessed by shared code
  * offset - offset of  word in the EEPROM to read
  * data - word read from the EEPROM
  * words - number of words to read
- *****************************************************************************/
+ */
 static s32 e1000_write_eeprom_eewr(struct e1000_hw *hw, u16 offset, u16 words,
                                   u16 *data)
 {
-    u32    register_value = 0;
-    u32    i              = 0;
-    s32     error          = 0;
-
+       u32 register_value = 0;
+       u32 i = 0;
+       s32 error = 0;
 
-    for (i = 0; i < words; i++) {
-        register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
-                         ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
-                         E1000_EEPROM_RW_REG_START;
+       for (i = 0; i < words; i++) {
+               register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
+                   ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT) |
+                   E1000_EEPROM_RW_REG_START;
 
-        error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
-        if (error) {
-            break;
-        }
+               error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
+               if (error) {
+                       break;
+               }
 
-        ew32(EEWR, register_value);
+               ew32(EEWR, register_value);
 
-        error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
+               error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
 
-        if (error) {
-            break;
-        }
-    }
+               if (error) {
+                       break;
+               }
+       }
 
-    return error;
+       return error;
 }
 
-/******************************************************************************
+/**
  * Polls the status bit (bit 1) of the EERD to determine when the read is done.
  *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+ * @hw: Struct containing variables accessed by shared code
+ */
 static s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
 {
-    u32 attempts = 100000;
-    u32 i, reg = 0;
-    s32 done = E1000_ERR_EEPROM;
-
-    for (i = 0; i < attempts; i++) {
-        if (eerd == E1000_EEPROM_POLL_READ)
-            reg = er32(EERD);
-        else
-            reg = er32(EEWR);
-
-        if (reg & E1000_EEPROM_RW_REG_DONE) {
-            done = E1000_SUCCESS;
-            break;
-        }
-        udelay(5);
-    }
-
-    return done;
+       u32 attempts = 100000;
+       u32 i, reg = 0;
+       s32 done = E1000_ERR_EEPROM;
+
+       for (i = 0; i < attempts; i++) {
+               if (eerd == E1000_EEPROM_POLL_READ)
+                       reg = er32(EERD);
+               else
+                       reg = er32(EEWR);
+
+               if (reg & E1000_EEPROM_RW_REG_DONE) {
+                       done = E1000_SUCCESS;
+                       break;
+               }
+               udelay(5);
+       }
+
+       return done;
 }
 
-/******************************************************************************
- * Verifies that the EEPROM has a valid checksum
- *
- * hw - Struct containing variables accessed by shared code
+/**
+ * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum
+ * @hw: Struct containing variables accessed by shared code
  *
  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
  * valid.
- *****************************************************************************/
+ */
 s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
 {
-    u16 checksum = 0;
-    u16 i, eeprom_data;
-
-    DEBUGFUNC("e1000_validate_eeprom_checksum");
-
-    for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
-        if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
-            DEBUGOUT("EEPROM Read Error\n");
-            return -E1000_ERR_EEPROM;
-        }
-        checksum += eeprom_data;
-    }
-
-    if (checksum == (u16)EEPROM_SUM)
-        return E1000_SUCCESS;
-    else {
-        DEBUGOUT("EEPROM Checksum Invalid\n");
-        return -E1000_ERR_EEPROM;
-    }
+       u16 checksum = 0;
+       u16 i, eeprom_data;
+
+       DEBUGFUNC("e1000_validate_eeprom_checksum");
+
+       for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
+               if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
+                       DEBUGOUT("EEPROM Read Error\n");
+                       return -E1000_ERR_EEPROM;
+               }
+               checksum += eeprom_data;
+       }
+
+       if (checksum == (u16) EEPROM_SUM)
+               return E1000_SUCCESS;
+       else {
+               DEBUGOUT("EEPROM Checksum Invalid\n");
+               return -E1000_ERR_EEPROM;
+       }
 }
 
-/******************************************************************************
- * Calculates the EEPROM checksum and writes it to the EEPROM
- *
- * hw - Struct containing variables accessed by shared code
+/**
+ * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum
+ * @hw: Struct containing variables accessed by shared code
  *
  * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
  * Writes the difference to word offset 63 of the EEPROM.
- *****************************************************************************/
+ */
 s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
 {
-    u16 checksum = 0;
-    u16 i, eeprom_data;
-
-    DEBUGFUNC("e1000_update_eeprom_checksum");
-
-    for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
-        if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
-            DEBUGOUT("EEPROM Read Error\n");
-            return -E1000_ERR_EEPROM;
-        }
-        checksum += eeprom_data;
-    }
-    checksum = (u16)EEPROM_SUM - checksum;
-    if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
-        DEBUGOUT("EEPROM Write Error\n");
-        return -E1000_ERR_EEPROM;
-    }
-    return E1000_SUCCESS;
+       u16 checksum = 0;
+       u16 i, eeprom_data;
+
+       DEBUGFUNC("e1000_update_eeprom_checksum");
+
+       for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
+               if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
+                       DEBUGOUT("EEPROM Read Error\n");
+                       return -E1000_ERR_EEPROM;
+               }
+               checksum += eeprom_data;
+       }
+       checksum = (u16) EEPROM_SUM - checksum;
+       if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
+               DEBUGOUT("EEPROM Write Error\n");
+               return -E1000_ERR_EEPROM;
+       }
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Parent function for writing words to the different EEPROM types.
- *
- * hw - Struct containing variables accessed by shared code
- * offset - offset within the EEPROM to be written to
- * words - number of words to write
- * data - 16 bit word to be written to the EEPROM
+/**
+ * e1000_write_eeprom - write words to the different EEPROM types.
+ * @hw: Struct containing variables accessed by shared code
+ * @offset: offset within the EEPROM to be written to
+ * @words: number of words to write
+ * @data: 16 bit word to be written to the EEPROM
  *
  * If e1000_update_eeprom_checksum is not called after this function, the
  * EEPROM will most likely contain an invalid checksum.
- *****************************************************************************/
+ */
 s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 {
-    s32 ret;
-    spin_lock(&e1000_eeprom_lock);
-    ret = e1000_do_write_eeprom(hw, offset, words, data);
-    spin_unlock(&e1000_eeprom_lock);
-    return ret;
+       s32 ret;
+       spin_lock(&e1000_eeprom_lock);
+       ret = e1000_do_write_eeprom(hw, offset, words, data);
+       spin_unlock(&e1000_eeprom_lock);
+       return ret;
 }
 
-
-static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
+static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
+                                u16 *data)
 {
-    struct e1000_eeprom_info *eeprom = &hw->eeprom;
-    s32 status = 0;
-
-    DEBUGFUNC("e1000_write_eeprom");
-
-    /* If eeprom is not yet detected, do so now */
-    if (eeprom->word_size == 0)
-        e1000_init_eeprom_params(hw);
-
-    /* A check for invalid values:  offset too large, too many words, and not
-     * enough words.
-     */
-    if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
-       (words == 0)) {
-        DEBUGOUT("\"words\" parameter out of bounds\n");
-        return -E1000_ERR_EEPROM;
-    }
-
-    if (eeprom->use_eewr)
-        return e1000_write_eeprom_eewr(hw, offset, words, data);
-
-    /* Prepare the EEPROM for writing  */
-    if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
-        return -E1000_ERR_EEPROM;
-
-    if (eeprom->type == e1000_eeprom_microwire) {
-        status = e1000_write_eeprom_microwire(hw, offset, words, data);
-    } else {
-        status = e1000_write_eeprom_spi(hw, offset, words, data);
-        msleep(10);
-    }
-
-    /* Done with writing */
-    e1000_release_eeprom(hw);
-
-    return status;
+       struct e1000_eeprom_info *eeprom = &hw->eeprom;
+       s32 status = 0;
+
+       DEBUGFUNC("e1000_write_eeprom");
+
+       /* If eeprom is not yet detected, do so now */
+       if (eeprom->word_size == 0)
+               e1000_init_eeprom_params(hw);
+
+       /* A check for invalid values:  offset too large, too many words, and not
+        * enough words.
+        */
+       if ((offset >= eeprom->word_size)
+           || (words > eeprom->word_size - offset) || (words == 0)) {
+               DEBUGOUT("\"words\" parameter out of bounds\n");
+               return -E1000_ERR_EEPROM;
+       }
+
+       if (eeprom->use_eewr)
+               return e1000_write_eeprom_eewr(hw, offset, words, data);
+
+       /* Prepare the EEPROM for writing  */
+       if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
+               return -E1000_ERR_EEPROM;
+
+       if (eeprom->type == e1000_eeprom_microwire) {
+               status = e1000_write_eeprom_microwire(hw, offset, words, data);
+       } else {
+               status = e1000_write_eeprom_spi(hw, offset, words, data);
+               msleep(10);
+       }
+
+       /* Done with writing */
+       e1000_release_eeprom(hw);
+
+       return status;
 }
 
-/******************************************************************************
- * Writes a 16 bit word to a given offset in an SPI EEPROM.
- *
- * hw - Struct containing variables accessed by shared code
- * offset - offset within the EEPROM to be written to
- * words - number of words to write
- * data - pointer to array of 8 bit words to be written to the EEPROM
- *
- *****************************************************************************/
+/**
+ * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM.
+ * @hw: Struct containing variables accessed by shared code
+ * @offset: offset within the EEPROM to be written to
+ * @words: number of words to write
+ * @data: pointer to array of 8 bit words to be written to the EEPROM
+ */
 static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
                                  u16 *data)
 {
-    struct e1000_eeprom_info *eeprom = &hw->eeprom;
-    u16 widx = 0;
+       struct e1000_eeprom_info *eeprom = &hw->eeprom;
+       u16 widx = 0;
 
-    DEBUGFUNC("e1000_write_eeprom_spi");
+       DEBUGFUNC("e1000_write_eeprom_spi");
 
-    while (widx < words) {
-        u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
+       while (widx < words) {
+               u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
 
-        if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
+               if (e1000_spi_eeprom_ready(hw))
+                       return -E1000_ERR_EEPROM;
 
-        e1000_standby_eeprom(hw);
+               e1000_standby_eeprom(hw);
 
-        /*  Send the WRITE ENABLE command (8 bit opcode )  */
-        e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
-                                    eeprom->opcode_bits);
+               /*  Send the WRITE ENABLE command (8 bit opcode )  */
+               e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
+                                       eeprom->opcode_bits);
 
-        e1000_standby_eeprom(hw);
+               e1000_standby_eeprom(hw);
 
-        /* Some SPI eeproms use the 8th address bit embedded in the opcode */
-        if ((eeprom->address_bits == 8) && (offset >= 128))
-            write_opcode |= EEPROM_A8_OPCODE_SPI;
+               /* Some SPI eeproms use the 8th address bit embedded in the opcode */
+               if ((eeprom->address_bits == 8) && (offset >= 128))
+                       write_opcode |= EEPROM_A8_OPCODE_SPI;
 
-        /* Send the Write command (8-bit opcode + addr) */
-        e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
+               /* Send the Write command (8-bit opcode + addr) */
+               e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
 
-        e1000_shift_out_ee_bits(hw, (u16)((offset + widx)*2),
-                                eeprom->address_bits);
+               e1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2),
+                                       eeprom->address_bits);
 
-        /* Send the data */
+               /* Send the data */
 
-        /* Loop to allow for up to whole page write (32 bytes) of eeprom */
-        while (widx < words) {
-            u16 word_out = data[widx];
-            word_out = (word_out >> 8) | (word_out << 8);
-            e1000_shift_out_ee_bits(hw, word_out, 16);
-            widx++;
+               /* Loop to allow for up to whole page write (32 bytes) of eeprom */
+               while (widx < words) {
+                       u16 word_out = data[widx];
+                       word_out = (word_out >> 8) | (word_out << 8);
+                       e1000_shift_out_ee_bits(hw, word_out, 16);
+                       widx++;
 
-            /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
-             * operation, while the smaller eeproms are capable of an 8-byte
-             * PAGE WRITE operation.  Break the inner loop to pass new address
-             */
-            if ((((offset + widx)*2) % eeprom->page_size) == 0) {
-                e1000_standby_eeprom(hw);
-                break;
-            }
-        }
-    }
+                       /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
+                        * operation, while the smaller eeproms are capable of an 8-byte
+                        * PAGE WRITE operation.  Break the inner loop to pass new address
+                        */
+                       if ((((offset + widx) * 2) % eeprom->page_size) == 0) {
+                               e1000_standby_eeprom(hw);
+                               break;
+                       }
+               }
+       }
 
-    return E1000_SUCCESS;
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Writes a 16 bit word to a given offset in a Microwire EEPROM.
- *
- * hw - Struct containing variables accessed by shared code
- * offset - offset within the EEPROM to be written to
- * words - number of words to write
- * data - pointer to array of 16 bit words to be written to the EEPROM
- *
- *****************************************************************************/
+/**
+ * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM.
+ * @hw: Struct containing variables accessed by shared code
+ * @offset: offset within the EEPROM to be written to
+ * @words: number of words to write
+ * @data: pointer to array of 8 bit words to be written to the EEPROM
+ */
 static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
                                        u16 words, u16 *data)
 {
-    struct e1000_eeprom_info *eeprom = &hw->eeprom;
-    u32 eecd;
-    u16 words_written = 0;
-    u16 i = 0;
-
-    DEBUGFUNC("e1000_write_eeprom_microwire");
-
-    /* Send the write enable command to the EEPROM (3-bit opcode plus
-     * 6/8-bit dummy address beginning with 11).  It's less work to include
-     * the 11 of the dummy address as part of the opcode than it is to shift
-     * it over the correct number of bits for the address.  This puts the
-     * EEPROM into write/erase mode.
-     */
-    e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
-                            (u16)(eeprom->opcode_bits + 2));
-
-    e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
-
-    /* Prepare the EEPROM */
-    e1000_standby_eeprom(hw);
-
-    while (words_written < words) {
-        /* Send the Write command (3-bit opcode + addr) */
-        e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
-                                eeprom->opcode_bits);
-
-        e1000_shift_out_ee_bits(hw, (u16)(offset + words_written),
-                                eeprom->address_bits);
-
-        /* Send the data */
-        e1000_shift_out_ee_bits(hw, data[words_written], 16);
-
-        /* Toggle the CS line.  This in effect tells the EEPROM to execute
-         * the previous command.
-         */
-        e1000_standby_eeprom(hw);
-
-        /* Read DO repeatedly until it is high (equal to '1').  The EEPROM will
-         * signal that the command has been completed by raising the DO signal.
-         * If DO does not go high in 10 milliseconds, then error out.
-         */
-        for (i = 0; i < 200; i++) {
-            eecd = er32(EECD);
-            if (eecd & E1000_EECD_DO) break;
-            udelay(50);
-        }
-        if (i == 200) {
-            DEBUGOUT("EEPROM Write did not complete\n");
-            return -E1000_ERR_EEPROM;
-        }
-
-        /* Recover from write */
-        e1000_standby_eeprom(hw);
-
-        words_written++;
-    }
-
-    /* Send the write disable command to the EEPROM (3-bit opcode plus
-     * 6/8-bit dummy address beginning with 10).  It's less work to include
-     * the 10 of the dummy address as part of the opcode than it is to shift
-     * it over the correct number of bits for the address.  This takes the
-     * EEPROM out of write/erase mode.
-     */
-    e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
-                            (u16)(eeprom->opcode_bits + 2));
-
-    e1000_shift_out_ee_bits(hw, 0, (u16)(eeprom->address_bits - 2));
-
-    return E1000_SUCCESS;
+       struct e1000_eeprom_info *eeprom = &hw->eeprom;
+       u32 eecd;
+       u16 words_written = 0;
+       u16 i = 0;
+
+       DEBUGFUNC("e1000_write_eeprom_microwire");
+
+       /* Send the write enable command to the EEPROM (3-bit opcode plus
+        * 6/8-bit dummy address beginning with 11).  It's less work to include
+        * the 11 of the dummy address as part of the opcode than it is to shift
+        * it over the correct number of bits for the address.  This puts the
+        * EEPROM into write/erase mode.
+        */
+       e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
+                               (u16) (eeprom->opcode_bits + 2));
+
+       e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
+
+       /* Prepare the EEPROM */
+       e1000_standby_eeprom(hw);
+
+       while (words_written < words) {
+               /* Send the Write command (3-bit opcode + addr) */
+               e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
+                                       eeprom->opcode_bits);
+
+               e1000_shift_out_ee_bits(hw, (u16) (offset + words_written),
+                                       eeprom->address_bits);
+
+               /* Send the data */
+               e1000_shift_out_ee_bits(hw, data[words_written], 16);
+
+               /* Toggle the CS line.  This in effect tells the EEPROM to execute
+                * the previous command.
+                */
+               e1000_standby_eeprom(hw);
+
+               /* Read DO repeatedly until it is high (equal to '1').  The EEPROM will
+                * signal that the command has been completed by raising the DO signal.
+                * If DO does not go high in 10 milliseconds, then error out.
+                */
+               for (i = 0; i < 200; i++) {
+                       eecd = er32(EECD);
+                       if (eecd & E1000_EECD_DO)
+                               break;
+                       udelay(50);
+               }
+               if (i == 200) {
+                       DEBUGOUT("EEPROM Write did not complete\n");
+                       return -E1000_ERR_EEPROM;
+               }
+
+               /* Recover from write */
+               e1000_standby_eeprom(hw);
+
+               words_written++;
+       }
+
+       /* Send the write disable command to the EEPROM (3-bit opcode plus
+        * 6/8-bit dummy address beginning with 10).  It's less work to include
+        * the 10 of the dummy address as part of the opcode than it is to shift
+        * it over the correct number of bits for the address.  This takes the
+        * EEPROM out of write/erase mode.
+        */
+       e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
+                               (u16) (eeprom->opcode_bits + 2));
+
+       e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
+
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
+/**
+ * e1000_read_mac_addr - read the adapters MAC from eeprom
+ * @hw: Struct containing variables accessed by shared code
+ *
  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
  * second function of dual function devices
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+ */
 s32 e1000_read_mac_addr(struct e1000_hw *hw)
 {
-    u16 offset;
-    u16 eeprom_data, i;
-
-    DEBUGFUNC("e1000_read_mac_addr");
-
-    for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
-        offset = i >> 1;
-        if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
-            DEBUGOUT("EEPROM Read Error\n");
-            return -E1000_ERR_EEPROM;
-        }
-        hw->perm_mac_addr[i] = (u8)(eeprom_data & 0x00FF);
-        hw->perm_mac_addr[i+1] = (u8)(eeprom_data >> 8);
-    }
-
-    switch (hw->mac_type) {
-    default:
-        break;
-    case e1000_82546:
-    case e1000_82546_rev_3:
-        if (er32(STATUS) & E1000_STATUS_FUNC_1)
-            hw->perm_mac_addr[5] ^= 0x01;
-        break;
-    }
-
-    for (i = 0; i < NODE_ADDRESS_SIZE; i++)
-        hw->mac_addr[i] = hw->perm_mac_addr[i];
-    return E1000_SUCCESS;
+       u16 offset;
+       u16 eeprom_data, i;
+
+       DEBUGFUNC("e1000_read_mac_addr");
+
+       for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
+               offset = i >> 1;
+               if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
+                       DEBUGOUT("EEPROM Read Error\n");
+                       return -E1000_ERR_EEPROM;
+               }
+               hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF);
+               hw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8);
+       }
+
+       switch (hw->mac_type) {
+       default:
+               break;
+       case e1000_82546:
+       case e1000_82546_rev_3:
+               if (er32(STATUS) & E1000_STATUS_FUNC_1)
+                       hw->perm_mac_addr[5] ^= 0x01;
+               break;
+       }
+
+       for (i = 0; i < NODE_ADDRESS_SIZE; i++)
+               hw->mac_addr[i] = hw->perm_mac_addr[i];
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Initializes receive address filters.
- *
- * hw - Struct containing variables accessed by shared code
+/**
+ * e1000_init_rx_addrs - Initializes receive address filters.
+ * @hw: Struct containing variables accessed by shared code
  *
  * Places the MAC address in receive address register 0 and clears the rest
- * of the receive addresss registers. Clears the multicast table. Assumes
+ * of the receive address registers. Clears the multicast table. Assumes
  * the receiver is in reset when the routine is called.
- *****************************************************************************/
+ */
 static void e1000_init_rx_addrs(struct e1000_hw *hw)
 {
-    u32 i;
-    u32 rar_num;
+       u32 i;
+       u32 rar_num;
 
-    DEBUGFUNC("e1000_init_rx_addrs");
+       DEBUGFUNC("e1000_init_rx_addrs");
 
-    /* Setup the receive address. */
-    DEBUGOUT("Programming MAC Address into RAR[0]\n");
+       /* Setup the receive address. */
+       DEBUGOUT("Programming MAC Address into RAR[0]\n");
 
-    e1000_rar_set(hw, hw->mac_addr, 0);
+       e1000_rar_set(hw, hw->mac_addr, 0);
 
-    rar_num = E1000_RAR_ENTRIES;
+       rar_num = E1000_RAR_ENTRIES;
 
-    /* Zero out the other 15 receive addresses. */
-    DEBUGOUT("Clearing RAR[1-15]\n");
-    for (i = 1; i < rar_num; i++) {
-        E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
-        E1000_WRITE_FLUSH();
-        E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
-        E1000_WRITE_FLUSH();
-    }
+       /* Zero out the other 15 receive addresses. */
+       DEBUGOUT("Clearing RAR[1-15]\n");
+       for (i = 1; i < rar_num; i++) {
+               E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
+               E1000_WRITE_FLUSH();
+               E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
+               E1000_WRITE_FLUSH();
+       }
 }
 
-/******************************************************************************
- * Hashes an address to determine its location in the multicast table
- *
- * hw - Struct containing variables accessed by shared code
- * mc_addr - the multicast address to hash
- *****************************************************************************/
+/**
+ * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table
+ * @hw: Struct containing variables accessed by shared code
+ * @mc_addr: the multicast address to hash
+ */
 u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
 {
-    u32 hash_value = 0;
-
-    /* The portion of the address that is used for the hash table is
-     * determined by the mc_filter_type setting.
-     */
-    switch (hw->mc_filter_type) {
-    /* [0] [1] [2] [3] [4] [5]
-     * 01  AA  00  12  34  56
-     * LSB                 MSB
-     */
-    case 0:
-        /* [47:36] i.e. 0x563 for above example address */
-        hash_value = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
-        break;
-    case 1:
-        /* [46:35] i.e. 0xAC6 for above example address */
-        hash_value = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
-        break;
-    case 2:
-        /* [45:34] i.e. 0x5D8 for above example address */
-        hash_value = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
-        break;
-    case 3:
-        /* [43:32] i.e. 0x634 for above example address */
-        hash_value = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
-        break;
-    }
-
-    hash_value &= 0xFFF;
-    return hash_value;
+       u32 hash_value = 0;
+
+       /* The portion of the address that is used for the hash table is
+        * determined by the mc_filter_type setting.
+        */
+       switch (hw->mc_filter_type) {
+               /* [0] [1] [2] [3] [4] [5]
+                * 01  AA  00  12  34  56
+                * LSB                 MSB
+                */
+       case 0:
+               /* [47:36] i.e. 0x563 for above example address */
+               hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
+               break;
+       case 1:
+               /* [46:35] i.e. 0xAC6 for above example address */
+               hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
+               break;
+       case 2:
+               /* [45:34] i.e. 0x5D8 for above example address */
+               hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
+               break;
+       case 3:
+               /* [43:32] i.e. 0x634 for above example address */
+               hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
+               break;
+       }
+
+       hash_value &= 0xFFF;
+       return hash_value;
 }
 
-/******************************************************************************
- * Puts an ethernet address into a receive address register.
- *
- * hw - Struct containing variables accessed by shared code
- * addr - Address to put into receive address register
- * index - Receive address register to write
- *****************************************************************************/
+/**
+ * e1000_rar_set - Puts an ethernet address into a receive address register.
+ * @hw: Struct containing variables accessed by shared code
+ * @addr: Address to put into receive address register
+ * @index: Receive address register to write
+ */
 void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
 {
-    u32 rar_low, rar_high;
-
-    /* HW expects these in little endian so we reverse the byte order
-     * from network order (big endian) to little endian
-     */
-    rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
-               ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
-    rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
-
-    /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
-     * unit hang.
-     *
-     * Description:
-     * If there are any Rx frames queued up or otherwise present in the HW
-     * before RSS is enabled, and then we enable RSS, the HW Rx unit will
-     * hang.  To work around this issue, we have to disable receives and
-     * flush out all Rx frames before we enable RSS. To do so, we modify we
-     * redirect all Rx traffic to manageability and then reset the HW.
-     * This flushes away Rx frames, and (since the redirections to
-     * manageability persists across resets) keeps new ones from coming in
-     * while we work.  Then, we clear the Address Valid AV bit for all MAC
-     * addresses and undo the re-direction to manageability.
-     * Now, frames are coming in again, but the MAC won't accept them, so
-     * far so good.  We now proceed to initialize RSS (if necessary) and
-     * configure the Rx unit.  Last, we re-enable the AV bits and continue
-     * on our merry way.
-     */
-    switch (hw->mac_type) {
-    default:
-        /* Indicate to hardware the Address is Valid. */
-        rar_high |= E1000_RAH_AV;
-        break;
-    }
-
-    E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
-    E1000_WRITE_FLUSH();
-    E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
-    E1000_WRITE_FLUSH();
+       u32 rar_low, rar_high;
+
+       /* HW expects these in little endian so we reverse the byte order
+        * from network order (big endian) to little endian
+        */
+       rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
+                  ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
+       rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
+
+       /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
+        * unit hang.
+        *
+        * Description:
+        * If there are any Rx frames queued up or otherwise present in the HW
+        * before RSS is enabled, and then we enable RSS, the HW Rx unit will
+        * hang.  To work around this issue, we have to disable receives and
+        * flush out all Rx frames before we enable RSS. To do so, we modify we
+        * redirect all Rx traffic to manageability and then reset the HW.
+        * This flushes away Rx frames, and (since the redirections to
+        * manageability persists across resets) keeps new ones from coming in
+        * while we work.  Then, we clear the Address Valid AV bit for all MAC
+        * addresses and undo the re-direction to manageability.
+        * Now, frames are coming in again, but the MAC won't accept them, so
+        * far so good.  We now proceed to initialize RSS (if necessary) and
+        * configure the Rx unit.  Last, we re-enable the AV bits and continue
+        * on our merry way.
+        */
+       switch (hw->mac_type) {
+       default:
+               /* Indicate to hardware the Address is Valid. */
+               rar_high |= E1000_RAH_AV;
+               break;
+       }
+
+       E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
+       E1000_WRITE_FLUSH();
+       E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
+       E1000_WRITE_FLUSH();
 }
 
-/******************************************************************************
- * Writes a value to the specified offset in the VLAN filter table.
- *
- * hw - Struct containing variables accessed by shared code
- * offset - Offset in VLAN filer table to write
- * value - Value to write into VLAN filter table
- *****************************************************************************/
+/**
+ * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table.
+ * @hw: Struct containing variables accessed by shared code
+ * @offset: Offset in VLAN filer table to write
+ * @value: Value to write into VLAN filter table
+ */
 void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
 {
-    u32 temp;
-
-    if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
-        temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
-        E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
-        E1000_WRITE_FLUSH();
-        E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
-        E1000_WRITE_FLUSH();
-    } else {
-        E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
-        E1000_WRITE_FLUSH();
-    }
+       u32 temp;
+
+       if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
+               temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
+               E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
+               E1000_WRITE_FLUSH();
+               E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
+               E1000_WRITE_FLUSH();
+       } else {
+               E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
+               E1000_WRITE_FLUSH();
+       }
 }
 
-/******************************************************************************
- * Clears the VLAN filer table
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+/**
+ * e1000_clear_vfta - Clears the VLAN filer table
+ * @hw: Struct containing variables accessed by shared code
+ */
 static void e1000_clear_vfta(struct e1000_hw *hw)
 {
-    u32 offset;
-    u32 vfta_value = 0;
-    u32 vfta_offset = 0;
-    u32 vfta_bit_in_reg = 0;
-
-    for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
-        /* If the offset we want to clear is the same offset of the
-         * manageability VLAN ID, then clear all bits except that of the
-         * manageability unit */
-        vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
-        E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
-        E1000_WRITE_FLUSH();
-    }
+       u32 offset;
+       u32 vfta_value = 0;
+       u32 vfta_offset = 0;
+       u32 vfta_bit_in_reg = 0;
+
+       for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
+               /* If the offset we want to clear is the same offset of the
+                * manageability VLAN ID, then clear all bits except that of the
+                * manageability unit */
+               vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
+               E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
+               E1000_WRITE_FLUSH();
+       }
 }
 
 static s32 e1000_id_led_init(struct e1000_hw *hw)
 {
-    u32 ledctl;
-    const u32 ledctl_mask = 0x000000FF;
-    const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
-    const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
-    u16 eeprom_data, i, temp;
-    const u16 led_mask = 0x0F;
-
-    DEBUGFUNC("e1000_id_led_init");
-
-    if (hw->mac_type < e1000_82540) {
-        /* Nothing to do */
-        return E1000_SUCCESS;
-    }
-
-    ledctl = er32(LEDCTL);
-    hw->ledctl_default = ledctl;
-    hw->ledctl_mode1 = hw->ledctl_default;
-    hw->ledctl_mode2 = hw->ledctl_default;
-
-    if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
-        DEBUGOUT("EEPROM Read Error\n");
-        return -E1000_ERR_EEPROM;
-    }
-
-    if ((eeprom_data == ID_LED_RESERVED_0000) ||
-            (eeprom_data == ID_LED_RESERVED_FFFF)) {
-            eeprom_data = ID_LED_DEFAULT;
-    }
-
-    for (i = 0; i < 4; i++) {
-        temp = (eeprom_data >> (i << 2)) & led_mask;
-        switch (temp) {
-        case ID_LED_ON1_DEF2:
-        case ID_LED_ON1_ON2:
-        case ID_LED_ON1_OFF2:
-            hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
-            hw->ledctl_mode1 |= ledctl_on << (i << 3);
-            break;
-        case ID_LED_OFF1_DEF2:
-        case ID_LED_OFF1_ON2:
-        case ID_LED_OFF1_OFF2:
-            hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
-            hw->ledctl_mode1 |= ledctl_off << (i << 3);
-            break;
-        default:
-            /* Do nothing */
-            break;
-        }
-        switch (temp) {
-        case ID_LED_DEF1_ON2:
-        case ID_LED_ON1_ON2:
-        case ID_LED_OFF1_ON2:
-            hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
-            hw->ledctl_mode2 |= ledctl_on << (i << 3);
-            break;
-        case ID_LED_DEF1_OFF2:
-        case ID_LED_ON1_OFF2:
-        case ID_LED_OFF1_OFF2:
-            hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
-            hw->ledctl_mode2 |= ledctl_off << (i << 3);
-            break;
-        default:
-            /* Do nothing */
-            break;
-        }
-    }
-    return E1000_SUCCESS;
+       u32 ledctl;
+       const u32 ledctl_mask = 0x000000FF;
+       const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
+       const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
+       u16 eeprom_data, i, temp;
+       const u16 led_mask = 0x0F;
+
+       DEBUGFUNC("e1000_id_led_init");
+
+       if (hw->mac_type < e1000_82540) {
+               /* Nothing to do */
+               return E1000_SUCCESS;
+       }
+
+       ledctl = er32(LEDCTL);
+       hw->ledctl_default = ledctl;
+       hw->ledctl_mode1 = hw->ledctl_default;
+       hw->ledctl_mode2 = hw->ledctl_default;
+
+       if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
+               DEBUGOUT("EEPROM Read Error\n");
+               return -E1000_ERR_EEPROM;
+       }
+
+       if ((eeprom_data == ID_LED_RESERVED_0000) ||
+           (eeprom_data == ID_LED_RESERVED_FFFF)) {
+               eeprom_data = ID_LED_DEFAULT;
+       }
+
+       for (i = 0; i < 4; i++) {
+               temp = (eeprom_data >> (i << 2)) & led_mask;
+               switch (temp) {
+               case ID_LED_ON1_DEF2:
+               case ID_LED_ON1_ON2:
+               case ID_LED_ON1_OFF2:
+                       hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
+                       hw->ledctl_mode1 |= ledctl_on << (i << 3);
+                       break;
+               case ID_LED_OFF1_DEF2:
+               case ID_LED_OFF1_ON2:
+               case ID_LED_OFF1_OFF2:
+                       hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
+                       hw->ledctl_mode1 |= ledctl_off << (i << 3);
+                       break;
+               default:
+                       /* Do nothing */
+                       break;
+               }
+               switch (temp) {
+               case ID_LED_DEF1_ON2:
+               case ID_LED_ON1_ON2:
+               case ID_LED_OFF1_ON2:
+                       hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
+                       hw->ledctl_mode2 |= ledctl_on << (i << 3);
+                       break;
+               case ID_LED_DEF1_OFF2:
+               case ID_LED_ON1_OFF2:
+               case ID_LED_OFF1_OFF2:
+                       hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
+                       hw->ledctl_mode2 |= ledctl_off << (i << 3);
+                       break;
+               default:
+                       /* Do nothing */
+                       break;
+               }
+       }
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Prepares SW controlable LED for use and saves the current state of the LED.
+/**
+ * e1000_setup_led
+ * @hw: Struct containing variables accessed by shared code
  *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+ * Prepares SW controlable LED for use and saves the current state of the LED.
+ */
 s32 e1000_setup_led(struct e1000_hw *hw)
 {
-    u32 ledctl;
-    s32 ret_val = E1000_SUCCESS;
-
-    DEBUGFUNC("e1000_setup_led");
-
-    switch (hw->mac_type) {
-    case e1000_82542_rev2_0:
-    case e1000_82542_rev2_1:
-    case e1000_82543:
-    case e1000_82544:
-        /* No setup necessary */
-        break;
-    case e1000_82541:
-    case e1000_82547:
-    case e1000_82541_rev_2:
-    case e1000_82547_rev_2:
-        /* Turn off PHY Smart Power Down (if enabled) */
-        ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
-                                     &hw->phy_spd_default);
-        if (ret_val)
-            return ret_val;
-        ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
-                                      (u16)(hw->phy_spd_default &
-                                      ~IGP01E1000_GMII_SPD));
-        if (ret_val)
-            return ret_val;
-        /* Fall Through */
-    default:
-        if (hw->media_type == e1000_media_type_fiber) {
-            ledctl = er32(LEDCTL);
-            /* Save current LEDCTL settings */
-            hw->ledctl_default = ledctl;
-            /* Turn off LED0 */
-            ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
-                        E1000_LEDCTL_LED0_BLINK |
-                        E1000_LEDCTL_LED0_MODE_MASK);
-            ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
-                       E1000_LEDCTL_LED0_MODE_SHIFT);
-            ew32(LEDCTL, ledctl);
-        } else if (hw->media_type == e1000_media_type_copper)
-            ew32(LEDCTL, hw->ledctl_mode1);
-        break;
-    }
-
-    return E1000_SUCCESS;
+       u32 ledctl;
+       s32 ret_val = E1000_SUCCESS;
+
+       DEBUGFUNC("e1000_setup_led");
+
+       switch (hw->mac_type) {
+       case e1000_82542_rev2_0:
+       case e1000_82542_rev2_1:
+       case e1000_82543:
+       case e1000_82544:
+               /* No setup necessary */
+               break;
+       case e1000_82541:
+       case e1000_82547:
+       case e1000_82541_rev_2:
+       case e1000_82547_rev_2:
+               /* Turn off PHY Smart Power Down (if enabled) */
+               ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
+                                            &hw->phy_spd_default);
+               if (ret_val)
+                       return ret_val;
+               ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
+                                             (u16) (hw->phy_spd_default &
+                                                    ~IGP01E1000_GMII_SPD));
+               if (ret_val)
+                       return ret_val;
+               /* Fall Through */
+       default:
+               if (hw->media_type == e1000_media_type_fiber) {
+                       ledctl = er32(LEDCTL);
+                       /* Save current LEDCTL settings */
+                       hw->ledctl_default = ledctl;
+                       /* Turn off LED0 */
+                       ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
+                                   E1000_LEDCTL_LED0_BLINK |
+                                   E1000_LEDCTL_LED0_MODE_MASK);
+                       ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
+                                  E1000_LEDCTL_LED0_MODE_SHIFT);
+                       ew32(LEDCTL, ledctl);
+               } else if (hw->media_type == e1000_media_type_copper)
+                       ew32(LEDCTL, hw->ledctl_mode1);
+               break;
+       }
+
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Restores the saved state of the SW controlable LED.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+/**
+ * e1000_cleanup_led - Restores the saved state of the SW controlable LED.
+ * @hw: Struct containing variables accessed by shared code
+ */
 s32 e1000_cleanup_led(struct e1000_hw *hw)
 {
-    s32 ret_val = E1000_SUCCESS;
-
-    DEBUGFUNC("e1000_cleanup_led");
-
-    switch (hw->mac_type) {
-    case e1000_82542_rev2_0:
-    case e1000_82542_rev2_1:
-    case e1000_82543:
-    case e1000_82544:
-        /* No cleanup necessary */
-        break;
-    case e1000_82541:
-    case e1000_82547:
-    case e1000_82541_rev_2:
-    case e1000_82547_rev_2:
-        /* Turn on PHY Smart Power Down (if previously enabled) */
-        ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
-                                      hw->phy_spd_default);
-        if (ret_val)
-            return ret_val;
-        /* Fall Through */
-    default:
-        /* Restore LEDCTL settings */
-        ew32(LEDCTL, hw->ledctl_default);
-        break;
-    }
-
-    return E1000_SUCCESS;
+       s32 ret_val = E1000_SUCCESS;
+
+       DEBUGFUNC("e1000_cleanup_led");
+
+       switch (hw->mac_type) {
+       case e1000_82542_rev2_0:
+       case e1000_82542_rev2_1:
+       case e1000_82543:
+       case e1000_82544:
+               /* No cleanup necessary */
+               break;
+       case e1000_82541:
+       case e1000_82547:
+       case e1000_82541_rev_2:
+       case e1000_82547_rev_2:
+               /* Turn on PHY Smart Power Down (if previously enabled) */
+               ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
+                                             hw->phy_spd_default);
+               if (ret_val)
+                       return ret_val;
+               /* Fall Through */
+       default:
+               /* Restore LEDCTL settings */
+               ew32(LEDCTL, hw->ledctl_default);
+               break;
+       }
+
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Turns on the software controllable LED
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+/**
+ * e1000_led_on - Turns on the software controllable LED
+ * @hw: Struct containing variables accessed by shared code
+ */
 s32 e1000_led_on(struct e1000_hw *hw)
 {
-    u32 ctrl = er32(CTRL);
-
-    DEBUGFUNC("e1000_led_on");
-
-    switch (hw->mac_type) {
-    case e1000_82542_rev2_0:
-    case e1000_82542_rev2_1:
-    case e1000_82543:
-        /* Set SW Defineable Pin 0 to turn on the LED */
-        ctrl |= E1000_CTRL_SWDPIN0;
-        ctrl |= E1000_CTRL_SWDPIO0;
-        break;
-    case e1000_82544:
-        if (hw->media_type == e1000_media_type_fiber) {
-            /* Set SW Defineable Pin 0 to turn on the LED */
-            ctrl |= E1000_CTRL_SWDPIN0;
-            ctrl |= E1000_CTRL_SWDPIO0;
-        } else {
-            /* Clear SW Defineable Pin 0 to turn on the LED */
-            ctrl &= ~E1000_CTRL_SWDPIN0;
-            ctrl |= E1000_CTRL_SWDPIO0;
-        }
-        break;
-    default:
-        if (hw->media_type == e1000_media_type_fiber) {
-            /* Clear SW Defineable Pin 0 to turn on the LED */
-            ctrl &= ~E1000_CTRL_SWDPIN0;
-            ctrl |= E1000_CTRL_SWDPIO0;
-        } else if (hw->media_type == e1000_media_type_copper) {
-            ew32(LEDCTL, hw->ledctl_mode2);
-            return E1000_SUCCESS;
-        }
-        break;
-    }
-
-    ew32(CTRL, ctrl);
-
-    return E1000_SUCCESS;
+       u32 ctrl = er32(CTRL);
+
+       DEBUGFUNC("e1000_led_on");
+
+       switch (hw->mac_type) {
+       case e1000_82542_rev2_0:
+       case e1000_82542_rev2_1:
+       case e1000_82543:
+               /* Set SW Defineable Pin 0 to turn on the LED */
+               ctrl |= E1000_CTRL_SWDPIN0;
+               ctrl |= E1000_CTRL_SWDPIO0;
+               break;
+       case e1000_82544:
+               if (hw->media_type == e1000_media_type_fiber) {
+                       /* Set SW Defineable Pin 0 to turn on the LED */
+                       ctrl |= E1000_CTRL_SWDPIN0;
+                       ctrl |= E1000_CTRL_SWDPIO0;
+               } else {
+                       /* Clear SW Defineable Pin 0 to turn on the LED */
+                       ctrl &= ~E1000_CTRL_SWDPIN0;
+                       ctrl |= E1000_CTRL_SWDPIO0;
+               }
+               break;
+       default:
+               if (hw->media_type == e1000_media_type_fiber) {
+                       /* Clear SW Defineable Pin 0 to turn on the LED */
+                       ctrl &= ~E1000_CTRL_SWDPIN0;
+                       ctrl |= E1000_CTRL_SWDPIO0;
+               } else if (hw->media_type == e1000_media_type_copper) {
+                       ew32(LEDCTL, hw->ledctl_mode2);
+                       return E1000_SUCCESS;
+               }
+               break;
+       }
+
+       ew32(CTRL, ctrl);
+
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Turns off the software controllable LED
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+/**
+ * e1000_led_off - Turns off the software controllable LED
+ * @hw: Struct containing variables accessed by shared code
+ */
 s32 e1000_led_off(struct e1000_hw *hw)
 {
-    u32 ctrl = er32(CTRL);
-
-    DEBUGFUNC("e1000_led_off");
-
-    switch (hw->mac_type) {
-    case e1000_82542_rev2_0:
-    case e1000_82542_rev2_1:
-    case e1000_82543:
-        /* Clear SW Defineable Pin 0 to turn off the LED */
-        ctrl &= ~E1000_CTRL_SWDPIN0;
-        ctrl |= E1000_CTRL_SWDPIO0;
-        break;
-    case e1000_82544:
-        if (hw->media_type == e1000_media_type_fiber) {
-            /* Clear SW Defineable Pin 0 to turn off the LED */
-            ctrl &= ~E1000_CTRL_SWDPIN0;
-            ctrl |= E1000_CTRL_SWDPIO0;
-        } else {
-            /* Set SW Defineable Pin 0 to turn off the LED */
-            ctrl |= E1000_CTRL_SWDPIN0;
-            ctrl |= E1000_CTRL_SWDPIO0;
-        }
-        break;
-    default:
-        if (hw->media_type == e1000_media_type_fiber) {
-            /* Set SW Defineable Pin 0 to turn off the LED */
-            ctrl |= E1000_CTRL_SWDPIN0;
-            ctrl |= E1000_CTRL_SWDPIO0;
-        } else if (hw->media_type == e1000_media_type_copper) {
-            ew32(LEDCTL, hw->ledctl_mode1);
-            return E1000_SUCCESS;
-        }
-        break;
-    }
-
-    ew32(CTRL, ctrl);
-
-    return E1000_SUCCESS;
+       u32 ctrl = er32(CTRL);
+
+       DEBUGFUNC("e1000_led_off");
+
+       switch (hw->mac_type) {
+       case e1000_82542_rev2_0:
+       case e1000_82542_rev2_1:
+       case e1000_82543:
+               /* Clear SW Defineable Pin 0 to turn off the LED */
+               ctrl &= ~E1000_CTRL_SWDPIN0;
+               ctrl |= E1000_CTRL_SWDPIO0;
+               break;
+       case e1000_82544:
+               if (hw->media_type == e1000_media_type_fiber) {
+                       /* Clear SW Defineable Pin 0 to turn off the LED */
+                       ctrl &= ~E1000_CTRL_SWDPIN0;
+                       ctrl |= E1000_CTRL_SWDPIO0;
+               } else {
+                       /* Set SW Defineable Pin 0 to turn off the LED */
+                       ctrl |= E1000_CTRL_SWDPIN0;
+                       ctrl |= E1000_CTRL_SWDPIO0;
+               }
+               break;
+       default:
+               if (hw->media_type == e1000_media_type_fiber) {
+                       /* Set SW Defineable Pin 0 to turn off the LED */
+                       ctrl |= E1000_CTRL_SWDPIN0;
+                       ctrl |= E1000_CTRL_SWDPIO0;
+               } else if (hw->media_type == e1000_media_type_copper) {
+                       ew32(LEDCTL, hw->ledctl_mode1);
+                       return E1000_SUCCESS;
+               }
+               break;
+       }
+
+       ew32(CTRL, ctrl);
+
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Clears all hardware statistics counters.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+/**
+ * e1000_clear_hw_cntrs - Clears all hardware statistics counters.
+ * @hw: Struct containing variables accessed by shared code
+ */
 static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
 {
-    volatile u32 temp;
-
-    temp = er32(CRCERRS);
-    temp = er32(SYMERRS);
-    temp = er32(MPC);
-    temp = er32(SCC);
-    temp = er32(ECOL);
-    temp = er32(MCC);
-    temp = er32(LATECOL);
-    temp = er32(COLC);
-    temp = er32(DC);
-    temp = er32(SEC);
-    temp = er32(RLEC);
-    temp = er32(XONRXC);
-    temp = er32(XONTXC);
-    temp = er32(XOFFRXC);
-    temp = er32(XOFFTXC);
-    temp = er32(FCRUC);
-
-    temp = er32(PRC64);
-    temp = er32(PRC127);
-    temp = er32(PRC255);
-    temp = er32(PRC511);
-    temp = er32(PRC1023);
-    temp = er32(PRC1522);
-
-    temp = er32(GPRC);
-    temp = er32(BPRC);
-    temp = er32(MPRC);
-    temp = er32(GPTC);
-    temp = er32(GORCL);
-    temp = er32(GORCH);
-    temp = er32(GOTCL);
-    temp = er32(GOTCH);
-    temp = er32(RNBC);
-    temp = er32(RUC);
-    temp = er32(RFC);
-    temp = er32(ROC);
-    temp = er32(RJC);
-    temp = er32(TORL);
-    temp = er32(TORH);
-    temp = er32(TOTL);
-    temp = er32(TOTH);
-    temp = er32(TPR);
-    temp = er32(TPT);
-
-    temp = er32(PTC64);
-    temp = er32(PTC127);
-    temp = er32(PTC255);
-    temp = er32(PTC511);
-    temp = er32(PTC1023);
-    temp = er32(PTC1522);
-
-    temp = er32(MPTC);
-    temp = er32(BPTC);
-
-    if (hw->mac_type < e1000_82543) return;
-
-    temp = er32(ALGNERRC);
-    temp = er32(RXERRC);
-    temp = er32(TNCRS);
-    temp = er32(CEXTERR);
-    temp = er32(TSCTC);
-    temp = er32(TSCTFC);
-
-    if (hw->mac_type <= e1000_82544) return;
-
-    temp = er32(MGTPRC);
-    temp = er32(MGTPDC);
-    temp = er32(MGTPTC);
+       volatile u32 temp;
+
+       temp = er32(CRCERRS);
+       temp = er32(SYMERRS);
+       temp = er32(MPC);
+       temp = er32(SCC);
+       temp = er32(ECOL);
+       temp = er32(MCC);
+       temp = er32(LATECOL);
+       temp = er32(COLC);
+       temp = er32(DC);
+       temp = er32(SEC);
+       temp = er32(RLEC);
+       temp = er32(XONRXC);
+       temp = er32(XONTXC);
+       temp = er32(XOFFRXC);
+       temp = er32(XOFFTXC);
+       temp = er32(FCRUC);
+
+       temp = er32(PRC64);
+       temp = er32(PRC127);
+       temp = er32(PRC255);
+       temp = er32(PRC511);
+       temp = er32(PRC1023);
+       temp = er32(PRC1522);
+
+       temp = er32(GPRC);
+       temp = er32(BPRC);
+       temp = er32(MPRC);
+       temp = er32(GPTC);
+       temp = er32(GORCL);
+       temp = er32(GORCH);
+       temp = er32(GOTCL);
+       temp = er32(GOTCH);
+       temp = er32(RNBC);
+       temp = er32(RUC);
+       temp = er32(RFC);
+       temp = er32(ROC);
+       temp = er32(RJC);
+       temp = er32(TORL);
+       temp = er32(TORH);
+       temp = er32(TOTL);
+       temp = er32(TOTH);
+       temp = er32(TPR);
+       temp = er32(TPT);
+
+       temp = er32(PTC64);
+       temp = er32(PTC127);
+       temp = er32(PTC255);
+       temp = er32(PTC511);
+       temp = er32(PTC1023);
+       temp = er32(PTC1522);
+
+       temp = er32(MPTC);
+       temp = er32(BPTC);
+
+       if (hw->mac_type < e1000_82543)
+               return;
+
+       temp = er32(ALGNERRC);
+       temp = er32(RXERRC);
+       temp = er32(TNCRS);
+       temp = er32(CEXTERR);
+       temp = er32(TSCTC);
+       temp = er32(TSCTFC);
+
+       if (hw->mac_type <= e1000_82544)
+               return;
+
+       temp = er32(MGTPRC);
+       temp = er32(MGTPDC);
+       temp = er32(MGTPTC);
 }
 
-/******************************************************************************
- * Resets Adaptive IFS to its default state.
- *
- * hw - Struct containing variables accessed by shared code
+/**
+ * e1000_reset_adaptive - Resets Adaptive IFS to its default state.
+ * @hw: Struct containing variables accessed by shared code
  *
  * Call this after e1000_init_hw. You may override the IFS defaults by setting
  * hw->ifs_params_forced to true. However, you must initialize hw->
  * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
  * before calling this function.
- *****************************************************************************/
+ */
 void e1000_reset_adaptive(struct e1000_hw *hw)
 {
-    DEBUGFUNC("e1000_reset_adaptive");
-
-    if (hw->adaptive_ifs) {
-        if (!hw->ifs_params_forced) {
-            hw->current_ifs_val = 0;
-            hw->ifs_min_val = IFS_MIN;
-            hw->ifs_max_val = IFS_MAX;
-            hw->ifs_step_size = IFS_STEP;
-            hw->ifs_ratio = IFS_RATIO;
-        }
-        hw->in_ifs_mode = false;
-        ew32(AIT, 0);
-    } else {
-        DEBUGOUT("Not in Adaptive IFS mode!\n");
-    }
+       DEBUGFUNC("e1000_reset_adaptive");
+
+       if (hw->adaptive_ifs) {
+               if (!hw->ifs_params_forced) {
+                       hw->current_ifs_val = 0;
+                       hw->ifs_min_val = IFS_MIN;
+                       hw->ifs_max_val = IFS_MAX;
+                       hw->ifs_step_size = IFS_STEP;
+                       hw->ifs_ratio = IFS_RATIO;
+               }
+               hw->in_ifs_mode = false;
+               ew32(AIT, 0);
+       } else {
+               DEBUGOUT("Not in Adaptive IFS mode!\n");
+       }
 }
 
-/******************************************************************************
+/**
+ * e1000_update_adaptive - update adaptive IFS
+ * @hw: Struct containing variables accessed by shared code
+ * @tx_packets: Number of transmits since last callback
+ * @total_collisions: Number of collisions since last callback
+ *
  * Called during the callback/watchdog routine to update IFS value based on
  * the ratio of transmits to collisions.
- *
- * hw - Struct containing variables accessed by shared code
- * tx_packets - Number of transmits since last callback
- * total_collisions - Number of collisions since last callback
- *****************************************************************************/
+ */
 void e1000_update_adaptive(struct e1000_hw *hw)
 {
-    DEBUGFUNC("e1000_update_adaptive");
-
-    if (hw->adaptive_ifs) {
-        if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
-            if (hw->tx_packet_delta > MIN_NUM_XMITS) {
-                hw->in_ifs_mode = true;
-                if (hw->current_ifs_val < hw->ifs_max_val) {
-                    if (hw->current_ifs_val == 0)
-                        hw->current_ifs_val = hw->ifs_min_val;
-                    else
-                        hw->current_ifs_val += hw->ifs_step_size;
-                    ew32(AIT, hw->current_ifs_val);
-                }
-            }
-        } else {
-            if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
-                hw->current_ifs_val = 0;
-                hw->in_ifs_mode = false;
-                ew32(AIT, 0);
-            }
-        }
-    } else {
-        DEBUGOUT("Not in Adaptive IFS mode!\n");
-    }
+       DEBUGFUNC("e1000_update_adaptive");
+
+       if (hw->adaptive_ifs) {
+               if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) {
+                       if (hw->tx_packet_delta > MIN_NUM_XMITS) {
+                               hw->in_ifs_mode = true;
+                               if (hw->current_ifs_val < hw->ifs_max_val) {
+                                       if (hw->current_ifs_val == 0)
+                                               hw->current_ifs_val =
+                                                   hw->ifs_min_val;
+                                       else
+                                               hw->current_ifs_val +=
+                                                   hw->ifs_step_size;
+                                       ew32(AIT, hw->current_ifs_val);
+                               }
+                       }
+               } else {
+                       if (hw->in_ifs_mode
+                           && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
+                               hw->current_ifs_val = 0;
+                               hw->in_ifs_mode = false;
+                               ew32(AIT, 0);
+                       }
+               }
+       } else {
+               DEBUGOUT("Not in Adaptive IFS mode!\n");
+       }
 }
 
-/******************************************************************************
- * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
+/**
+ * e1000_tbi_adjust_stats
+ * @hw: Struct containing variables accessed by shared code
+ * @frame_len: The length of the frame in question
+ * @mac_addr: The Ethernet destination address of the frame in question
  *
- * hw - Struct containing variables accessed by shared code
- * frame_len - The length of the frame in question
- * mac_addr - The Ethernet destination address of the frame in question
- *****************************************************************************/
+ * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
+ */
 void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
                            u32 frame_len, u8 *mac_addr)
 {
-    u64 carry_bit;
-
-    /* First adjust the frame length. */
-    frame_len--;
-    /* We need to adjust the statistics counters, since the hardware
-     * counters overcount this packet as a CRC error and undercount
-     * the packet as a good packet
-     */
-    /* This packet should not be counted as a CRC error.    */
-    stats->crcerrs--;
-    /* This packet does count as a Good Packet Received.    */
-    stats->gprc++;
-
-    /* Adjust the Good Octets received counters             */
-    carry_bit = 0x80000000 & stats->gorcl;
-    stats->gorcl += frame_len;
-    /* If the high bit of Gorcl (the low 32 bits of the Good Octets
-     * Received Count) was one before the addition,
-     * AND it is zero after, then we lost the carry out,
-     * need to add one to Gorch (Good Octets Received Count High).
-     * This could be simplified if all environments supported
-     * 64-bit integers.
-     */
-    if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
-        stats->gorch++;
-    /* Is this a broadcast or multicast?  Check broadcast first,
-     * since the test for a multicast frame will test positive on
-     * a broadcast frame.
-     */
-    if ((mac_addr[0] == (u8)0xff) && (mac_addr[1] == (u8)0xff))
-        /* Broadcast packet */
-        stats->bprc++;
-    else if (*mac_addr & 0x01)
-        /* Multicast packet */
-        stats->mprc++;
-
-    if (frame_len == hw->max_frame_size) {
-        /* In this case, the hardware has overcounted the number of
-         * oversize frames.
-         */
-        if (stats->roc > 0)
-            stats->roc--;
-    }
-
-    /* Adjust the bin counters when the extra byte put the frame in the
-     * wrong bin. Remember that the frame_len was adjusted above.
-     */
-    if (frame_len == 64) {
-        stats->prc64++;
-        stats->prc127--;
-    } else if (frame_len == 127) {
-        stats->prc127++;
-        stats->prc255--;
-    } else if (frame_len == 255) {
-        stats->prc255++;
-        stats->prc511--;
-    } else if (frame_len == 511) {
-        stats->prc511++;
-        stats->prc1023--;
-    } else if (frame_len == 1023) {
-        stats->prc1023++;
-        stats->prc1522--;
-    } else if (frame_len == 1522) {
-        stats->prc1522++;
-    }
+       u64 carry_bit;
+
+       /* First adjust the frame length. */
+       frame_len--;
+       /* We need to adjust the statistics counters, since the hardware
+        * counters overcount this packet as a CRC error and undercount
+        * the packet as a good packet
+        */
+       /* This packet should not be counted as a CRC error.    */
+       stats->crcerrs--;
+       /* This packet does count as a Good Packet Received.    */
+       stats->gprc++;
+
+       /* Adjust the Good Octets received counters             */
+       carry_bit = 0x80000000 & stats->gorcl;
+       stats->gorcl += frame_len;
+       /* If the high bit of Gorcl (the low 32 bits of the Good Octets
+        * Received Count) was one before the addition,
+        * AND it is zero after, then we lost the carry out,
+        * need to add one to Gorch (Good Octets Received Count High).
+        * This could be simplified if all environments supported
+        * 64-bit integers.
+        */
+       if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
+               stats->gorch++;
+       /* Is this a broadcast or multicast?  Check broadcast first,
+        * since the test for a multicast frame will test positive on
+        * a broadcast frame.
+        */
+       if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff))
+               /* Broadcast packet */
+               stats->bprc++;
+       else if (*mac_addr & 0x01)
+               /* Multicast packet */
+               stats->mprc++;
+
+       if (frame_len == hw->max_frame_size) {
+               /* In this case, the hardware has overcounted the number of
+                * oversize frames.
+                */
+               if (stats->roc > 0)
+                       stats->roc--;
+       }
+
+       /* Adjust the bin counters when the extra byte put the frame in the
+        * wrong bin. Remember that the frame_len was adjusted above.
+        */
+       if (frame_len == 64) {
+               stats->prc64++;
+               stats->prc127--;
+       } else if (frame_len == 127) {
+               stats->prc127++;
+               stats->prc255--;
+       } else if (frame_len == 255) {
+               stats->prc255++;
+               stats->prc511--;
+       } else if (frame_len == 511) {
+               stats->prc511++;
+               stats->prc1023--;
+       } else if (frame_len == 1023) {
+               stats->prc1023++;
+               stats->prc1522--;
+       } else if (frame_len == 1522) {
+               stats->prc1522++;
+       }
 }
 
-/******************************************************************************
- * Gets the current PCI bus type, speed, and width of the hardware
+/**
+ * e1000_get_bus_info
+ * @hw: Struct containing variables accessed by shared code
  *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+ * Gets the current PCI bus type, speed, and width of the hardware
+ */
 void e1000_get_bus_info(struct e1000_hw *hw)
 {
-    u32 status;
-
-    switch (hw->mac_type) {
-    case e1000_82542_rev2_0:
-    case e1000_82542_rev2_1:
-        hw->bus_type = e1000_bus_type_pci;
-        hw->bus_speed = e1000_bus_speed_unknown;
-        hw->bus_width = e1000_bus_width_unknown;
-        break;
-    default:
-        status = er32(STATUS);
-        hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
-                       e1000_bus_type_pcix : e1000_bus_type_pci;
-
-        if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
-            hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
-                            e1000_bus_speed_66 : e1000_bus_speed_120;
-        } else if (hw->bus_type == e1000_bus_type_pci) {
-            hw->bus_speed = (status & E1000_STATUS_PCI66) ?
-                            e1000_bus_speed_66 : e1000_bus_speed_33;
-        } else {
-            switch (status & E1000_STATUS_PCIX_SPEED) {
-            case E1000_STATUS_PCIX_SPEED_66:
-                hw->bus_speed = e1000_bus_speed_66;
-                break;
-            case E1000_STATUS_PCIX_SPEED_100:
-                hw->bus_speed = e1000_bus_speed_100;
-                break;
-            case E1000_STATUS_PCIX_SPEED_133:
-                hw->bus_speed = e1000_bus_speed_133;
-                break;
-            default:
-                hw->bus_speed = e1000_bus_speed_reserved;
-                break;
-            }
-        }
-        hw->bus_width = (status & E1000_STATUS_BUS64) ?
-                        e1000_bus_width_64 : e1000_bus_width_32;
-        break;
-    }
+       u32 status;
+
+       switch (hw->mac_type) {
+       case e1000_82542_rev2_0:
+       case e1000_82542_rev2_1:
+               hw->bus_type = e1000_bus_type_pci;
+               hw->bus_speed = e1000_bus_speed_unknown;
+               hw->bus_width = e1000_bus_width_unknown;
+               break;
+       default:
+               status = er32(STATUS);
+               hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
+                   e1000_bus_type_pcix : e1000_bus_type_pci;
+
+               if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
+                       hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
+                           e1000_bus_speed_66 : e1000_bus_speed_120;
+               } else if (hw->bus_type == e1000_bus_type_pci) {
+                       hw->bus_speed = (status & E1000_STATUS_PCI66) ?
+                           e1000_bus_speed_66 : e1000_bus_speed_33;
+               } else {
+                       switch (status & E1000_STATUS_PCIX_SPEED) {
+                       case E1000_STATUS_PCIX_SPEED_66:
+                               hw->bus_speed = e1000_bus_speed_66;
+                               break;
+                       case E1000_STATUS_PCIX_SPEED_100:
+                               hw->bus_speed = e1000_bus_speed_100;
+                               break;
+                       case E1000_STATUS_PCIX_SPEED_133:
+                               hw->bus_speed = e1000_bus_speed_133;
+                               break;
+                       default:
+                               hw->bus_speed = e1000_bus_speed_reserved;
+                               break;
+                       }
+               }
+               hw->bus_width = (status & E1000_STATUS_BUS64) ?
+                   e1000_bus_width_64 : e1000_bus_width_32;
+               break;
+       }
 }
 
-/******************************************************************************
+/**
+ * e1000_write_reg_io
+ * @hw: Struct containing variables accessed by shared code
+ * @offset: offset to write to
+ * @value: value to write
+ *
  * Writes a value to one of the devices registers using port I/O (as opposed to
  * memory mapped I/O). Only 82544 and newer devices support port I/O.
- *
- * hw - Struct containing variables accessed by shared code
- * offset - offset to write to
- * value - value to write
- *****************************************************************************/
+ */
 static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
 {
-    unsigned long io_addr = hw->io_base;
-    unsigned long io_data = hw->io_base + 4;
+       unsigned long io_addr = hw->io_base;
+       unsigned long io_data = hw->io_base + 4;
 
-    e1000_io_write(hw, io_addr, offset);
-    e1000_io_write(hw, io_data, value);
+       e1000_io_write(hw, io_addr, offset);
+       e1000_io_write(hw, io_data, value);
 }
 
-/******************************************************************************
- * Estimates the cable length.
- *
- * hw - Struct containing variables accessed by shared code
- * min_length - The estimated minimum length
- * max_length - The estimated maximum length
+/**
+ * e1000_get_cable_length - Estimates the cable length.
+ * @hw: Struct containing variables accessed by shared code
+ * @min_length: The estimated minimum length
+ * @max_length: The estimated maximum length
  *
  * returns: - E1000_ERR_XXX
  *            E1000_SUCCESS
@@ -4876,112 +4957,115 @@ static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
  * So for M88 phy's, this function interprets the one value returned from the
  * register to the minimum and maximum range.
  * For IGP phy's, the function calculates the range by the AGC registers.
- *****************************************************************************/
+ */
 static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
                                  u16 *max_length)
 {
-    s32 ret_val;
-    u16 agc_value = 0;
-    u16 i, phy_data;
-    u16 cable_length;
-
-    DEBUGFUNC("e1000_get_cable_length");
-
-    *min_length = *max_length = 0;
-
-    /* Use old method for Phy older than IGP */
-    if (hw->phy_type == e1000_phy_m88) {
-
-        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
-                                     &phy_data);
-        if (ret_val)
-            return ret_val;
-        cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
-                       M88E1000_PSSR_CABLE_LENGTH_SHIFT;
-
-        /* Convert the enum value to ranged values */
-        switch (cable_length) {
-        case e1000_cable_length_50:
-            *min_length = 0;
-            *max_length = e1000_igp_cable_length_50;
-            break;
-        case e1000_cable_length_50_80:
-            *min_length = e1000_igp_cable_length_50;
-            *max_length = e1000_igp_cable_length_80;
-            break;
-        case e1000_cable_length_80_110:
-            *min_length = e1000_igp_cable_length_80;
-            *max_length = e1000_igp_cable_length_110;
-            break;
-        case e1000_cable_length_110_140:
-            *min_length = e1000_igp_cable_length_110;
-            *max_length = e1000_igp_cable_length_140;
-            break;
-        case e1000_cable_length_140:
-            *min_length = e1000_igp_cable_length_140;
-            *max_length = e1000_igp_cable_length_170;
-            break;
-        default:
-            return -E1000_ERR_PHY;
-            break;
-        }
-    } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
-        u16 cur_agc_value;
-        u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
-        u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
-                                                         {IGP01E1000_PHY_AGC_A,
-                                                          IGP01E1000_PHY_AGC_B,
-                                                          IGP01E1000_PHY_AGC_C,
-                                                          IGP01E1000_PHY_AGC_D};
-        /* Read the AGC registers for all channels */
-        for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
-
-            ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
-            if (ret_val)
-                return ret_val;
-
-            cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
-
-            /* Value bound check. */
-            if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
-                (cur_agc_value == 0))
-                return -E1000_ERR_PHY;
-
-            agc_value += cur_agc_value;
-
-            /* Update minimal AGC value. */
-            if (min_agc_value > cur_agc_value)
-                min_agc_value = cur_agc_value;
-        }
-
-        /* Remove the minimal AGC result for length < 50m */
-        if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
-            agc_value -= min_agc_value;
-
-            /* Get the average length of the remaining 3 channels */
-            agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
-        } else {
-            /* Get the average length of all the 4 channels. */
-            agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
-        }
-
-        /* Set the range of the calculated length. */
-        *min_length = ((e1000_igp_cable_length_table[agc_value] -
-                       IGP01E1000_AGC_RANGE) > 0) ?
-                       (e1000_igp_cable_length_table[agc_value] -
-                       IGP01E1000_AGC_RANGE) : 0;
-        *max_length = e1000_igp_cable_length_table[agc_value] +
-                      IGP01E1000_AGC_RANGE;
-    }
-
-    return E1000_SUCCESS;
+       s32 ret_val;
+       u16 agc_value = 0;
+       u16 i, phy_data;
+       u16 cable_length;
+
+       DEBUGFUNC("e1000_get_cable_length");
+
+       *min_length = *max_length = 0;
+
+       /* Use old method for Phy older than IGP */
+       if (hw->phy_type == e1000_phy_m88) {
+
+               ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
+                                            &phy_data);
+               if (ret_val)
+                       return ret_val;
+               cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
+                   M88E1000_PSSR_CABLE_LENGTH_SHIFT;
+
+               /* Convert the enum value to ranged values */
+               switch (cable_length) {
+               case e1000_cable_length_50:
+                       *min_length = 0;
+                       *max_length = e1000_igp_cable_length_50;
+                       break;
+               case e1000_cable_length_50_80:
+                       *min_length = e1000_igp_cable_length_50;
+                       *max_length = e1000_igp_cable_length_80;
+                       break;
+               case e1000_cable_length_80_110:
+                       *min_length = e1000_igp_cable_length_80;
+                       *max_length = e1000_igp_cable_length_110;
+                       break;
+               case e1000_cable_length_110_140:
+                       *min_length = e1000_igp_cable_length_110;
+                       *max_length = e1000_igp_cable_length_140;
+                       break;
+               case e1000_cable_length_140:
+                       *min_length = e1000_igp_cable_length_140;
+                       *max_length = e1000_igp_cable_length_170;
+                       break;
+               default:
+                       return -E1000_ERR_PHY;
+                       break;
+               }
+       } else if (hw->phy_type == e1000_phy_igp) {     /* For IGP PHY */
+               u16 cur_agc_value;
+               u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
+               u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
+                   { IGP01E1000_PHY_AGC_A,
+                       IGP01E1000_PHY_AGC_B,
+                       IGP01E1000_PHY_AGC_C,
+                       IGP01E1000_PHY_AGC_D
+               };
+               /* Read the AGC registers for all channels */
+               for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
+
+                       ret_val =
+                           e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
+                       if (ret_val)
+                               return ret_val;
+
+                       cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
+
+                       /* Value bound check. */
+                       if ((cur_agc_value >=
+                            IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1)
+                           || (cur_agc_value == 0))
+                               return -E1000_ERR_PHY;
+
+                       agc_value += cur_agc_value;
+
+                       /* Update minimal AGC value. */
+                       if (min_agc_value > cur_agc_value)
+                               min_agc_value = cur_agc_value;
+               }
+
+               /* Remove the minimal AGC result for length < 50m */
+               if (agc_value <
+                   IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
+                       agc_value -= min_agc_value;
+
+                       /* Get the average length of the remaining 3 channels */
+                       agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
+               } else {
+                       /* Get the average length of all the 4 channels. */
+                       agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
+               }
+
+               /* Set the range of the calculated length. */
+               *min_length = ((e1000_igp_cable_length_table[agc_value] -
+                               IGP01E1000_AGC_RANGE) > 0) ?
+                   (e1000_igp_cable_length_table[agc_value] -
+                    IGP01E1000_AGC_RANGE) : 0;
+               *max_length = e1000_igp_cable_length_table[agc_value] +
+                   IGP01E1000_AGC_RANGE;
+       }
+
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Check the cable polarity
- *
- * hw - Struct containing variables accessed by shared code
- * polarity - output parameter : 0 - Polarity is not reversed
+/**
+ * e1000_check_polarity - Check the cable polarity
+ * @hw: Struct containing variables accessed by shared code
+ * @polarity: output parameter : 0 - Polarity is not reversed
  *                               1 - Polarity is reversed.
  *
  * returns: - E1000_ERR_XXX
@@ -4992,62 +5076,65 @@ static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
  * 10 Mbps.  If the link speed is 100 Mbps there is no polarity so this bit will
  * return 0.  If the link speed is 1000 Mbps the polarity status is in the
  * IGP01E1000_PHY_PCS_INIT_REG.
- *****************************************************************************/
+ */
 static s32 e1000_check_polarity(struct e1000_hw *hw,
                                e1000_rev_polarity *polarity)
 {
-    s32 ret_val;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_check_polarity");
-
-    if (hw->phy_type == e1000_phy_m88) {
-        /* return the Polarity bit in the Status register. */
-        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
-                                     &phy_data);
-        if (ret_val)
-            return ret_val;
-        *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
-                     M88E1000_PSSR_REV_POLARITY_SHIFT) ?
-                     e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
-
-    } else if (hw->phy_type == e1000_phy_igp) {
-        /* Read the Status register to check the speed */
-        ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
-                                     &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
-         * find the polarity status */
-        if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
-           IGP01E1000_PSSR_SPEED_1000MBPS) {
-
-            /* Read the GIG initialization PCS register (0x00B4) */
-            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
-                                         &phy_data);
-            if (ret_val)
-                return ret_val;
-
-            /* Check the polarity bits */
-            *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
-                         e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
-        } else {
-            /* For 10 Mbps, read the polarity bit in the status register. (for
-             * 100 Mbps this bit is always 0) */
-            *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
-                         e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
-        }
-    }
-    return E1000_SUCCESS;
+       s32 ret_val;
+       u16 phy_data;
+
+       DEBUGFUNC("e1000_check_polarity");
+
+       if (hw->phy_type == e1000_phy_m88) {
+               /* return the Polarity bit in the Status register. */
+               ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
+                                            &phy_data);
+               if (ret_val)
+                       return ret_val;
+               *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
+                            M88E1000_PSSR_REV_POLARITY_SHIFT) ?
+                   e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
+
+       } else if (hw->phy_type == e1000_phy_igp) {
+               /* Read the Status register to check the speed */
+               ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
+                                            &phy_data);
+               if (ret_val)
+                       return ret_val;
+
+               /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
+                * find the polarity status */
+               if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
+                   IGP01E1000_PSSR_SPEED_1000MBPS) {
+
+                       /* Read the GIG initialization PCS register (0x00B4) */
+                       ret_val =
+                           e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
+                                              &phy_data);
+                       if (ret_val)
+                               return ret_val;
+
+                       /* Check the polarity bits */
+                       *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
+                           e1000_rev_polarity_reversed :
+                           e1000_rev_polarity_normal;
+               } else {
+                       /* For 10 Mbps, read the polarity bit in the status register. (for
+                        * 100 Mbps this bit is always 0) */
+                       *polarity =
+                           (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
+                           e1000_rev_polarity_reversed :
+                           e1000_rev_polarity_normal;
+               }
+       }
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Check if Downshift occured
- *
- * hw - Struct containing variables accessed by shared code
- * downshift - output parameter : 0 - No Downshift ocured.
- *                                1 - Downshift ocured.
+/**
+ * e1000_check_downshift - Check if Downshift occurred
+ * @hw: Struct containing variables accessed by shared code
+ * @downshift: output parameter : 0 - No Downshift occurred.
+ *                                1 - Downshift occurred.
  *
  * returns: - E1000_ERR_XXX
  *            E1000_SUCCESS
@@ -5056,573 +5143,607 @@ static s32 e1000_check_polarity(struct e1000_hw *hw,
  * Specific Status register.  For IGP phy's, it reads the Downgrade bit in the
  * Link Health register.  In IGP this bit is latched high, so the driver must
  * read it immediately after link is established.
- *****************************************************************************/
+ */
 static s32 e1000_check_downshift(struct e1000_hw *hw)
 {
-    s32 ret_val;
-    u16 phy_data;
-
-    DEBUGFUNC("e1000_check_downshift");
-
-    if (hw->phy_type == e1000_phy_igp) {
-        ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
-                                     &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
-    } else if (hw->phy_type == e1000_phy_m88) {
-        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
-                                     &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
-                               M88E1000_PSSR_DOWNSHIFT_SHIFT;
-    }
+       s32 ret_val;
+       u16 phy_data;
+
+       DEBUGFUNC("e1000_check_downshift");
+
+       if (hw->phy_type == e1000_phy_igp) {
+               ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
+                                            &phy_data);
+               if (ret_val)
+                       return ret_val;
+
+               hw->speed_downgraded =
+                   (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
+       } else if (hw->phy_type == e1000_phy_m88) {
+               ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
+                                            &phy_data);
+               if (ret_val)
+                       return ret_val;
+
+               hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
+                   M88E1000_PSSR_DOWNSHIFT_SHIFT;
+       }
 
-    return E1000_SUCCESS;
+       return E1000_SUCCESS;
 }
 
-/*****************************************************************************
- *
- * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
- * gigabit link is achieved to improve link quality.
- *
- * hw: Struct containing variables accessed by shared code
+/**
+ * e1000_config_dsp_after_link_change
+ * @hw: Struct containing variables accessed by shared code
+ * @link_up: was link up at the time this was called
  *
  * returns: - E1000_ERR_PHY if fail to read/write the PHY
  *            E1000_SUCCESS at any other case.
  *
- ****************************************************************************/
+ * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
+ * gigabit link is achieved to improve link quality.
+ */
 
 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
 {
-    s32 ret_val;
-    u16 phy_data, phy_saved_data, speed, duplex, i;
-    u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
-                                        {IGP01E1000_PHY_AGC_PARAM_A,
-                                        IGP01E1000_PHY_AGC_PARAM_B,
-                                        IGP01E1000_PHY_AGC_PARAM_C,
-                                        IGP01E1000_PHY_AGC_PARAM_D};
-    u16 min_length, max_length;
-
-    DEBUGFUNC("e1000_config_dsp_after_link_change");
-
-    if (hw->phy_type != e1000_phy_igp)
-        return E1000_SUCCESS;
-
-    if (link_up) {
-        ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
-        if (ret_val) {
-            DEBUGOUT("Error getting link speed and duplex\n");
-            return ret_val;
-        }
-
-        if (speed == SPEED_1000) {
-
-            ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
-            if (ret_val)
-                return ret_val;
-
-            if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
-                min_length >= e1000_igp_cable_length_50) {
-
-                for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
-                    ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
-                                                 &phy_data);
-                    if (ret_val)
-                        return ret_val;
-
-                    phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
-
-                    ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
-                                                  phy_data);
-                    if (ret_val)
-                        return ret_val;
-                }
-                hw->dsp_config_state = e1000_dsp_config_activated;
-            }
-
-            if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
-               (min_length < e1000_igp_cable_length_50)) {
-
-                u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
-                u32 idle_errs = 0;
-
-                /* clear previous idle error counts */
-                ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
-                                             &phy_data);
-                if (ret_val)
-                    return ret_val;
-
-                for (i = 0; i < ffe_idle_err_timeout; i++) {
-                    udelay(1000);
-                    ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
-                                                 &phy_data);
-                    if (ret_val)
-                        return ret_val;
-
-                    idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
-                    if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
-                        hw->ffe_config_state = e1000_ffe_config_active;
-
-                        ret_val = e1000_write_phy_reg(hw,
-                                    IGP01E1000_PHY_DSP_FFE,
-                                    IGP01E1000_PHY_DSP_FFE_CM_CP);
-                        if (ret_val)
-                            return ret_val;
-                        break;
-                    }
-
-                    if (idle_errs)
-                        ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
-                }
-            }
-        }
-    } else {
-        if (hw->dsp_config_state == e1000_dsp_config_activated) {
-            /* Save off the current value of register 0x2F5B to be restored at
-             * the end of the routines. */
-            ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
-
-            if (ret_val)
-                return ret_val;
-
-            /* Disable the PHY transmitter */
-            ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
-
-            if (ret_val)
-                return ret_val;
-
-            mdelay(20);
-
-            ret_val = e1000_write_phy_reg(hw, 0x0000,
-                                          IGP01E1000_IEEE_FORCE_GIGA);
-            if (ret_val)
-                return ret_val;
-            for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
-                ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
-                if (ret_val)
-                    return ret_val;
-
-                phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
-                phy_data |=  IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
-
-                ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
-                if (ret_val)
-                    return ret_val;
-            }
-
-            ret_val = e1000_write_phy_reg(hw, 0x0000,
-                                          IGP01E1000_IEEE_RESTART_AUTONEG);
-            if (ret_val)
-                return ret_val;
-
-            mdelay(20);
-
-            /* Now enable the transmitter */
-            ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
-
-            if (ret_val)
-                return ret_val;
-
-            hw->dsp_config_state = e1000_dsp_config_enabled;
-        }
-
-        if (hw->ffe_config_state == e1000_ffe_config_active) {
-            /* Save off the current value of register 0x2F5B to be restored at
-             * the end of the routines. */
-            ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
-
-            if (ret_val)
-                return ret_val;
-
-            /* Disable the PHY transmitter */
-            ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
-
-            if (ret_val)
-                return ret_val;
-
-            mdelay(20);
-
-            ret_val = e1000_write_phy_reg(hw, 0x0000,
-                                          IGP01E1000_IEEE_FORCE_GIGA);
-            if (ret_val)
-                return ret_val;
-            ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
-                                          IGP01E1000_PHY_DSP_FFE_DEFAULT);
-            if (ret_val)
-                return ret_val;
-
-            ret_val = e1000_write_phy_reg(hw, 0x0000,
-                                          IGP01E1000_IEEE_RESTART_AUTONEG);
-            if (ret_val)
-                return ret_val;
-
-            mdelay(20);
-
-            /* Now enable the transmitter */
-            ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
-
-            if (ret_val)
-                return ret_val;
-
-            hw->ffe_config_state = e1000_ffe_config_enabled;
-        }
-    }
-    return E1000_SUCCESS;
+       s32 ret_val;
+       u16 phy_data, phy_saved_data, speed, duplex, i;
+       u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
+           { IGP01E1000_PHY_AGC_PARAM_A,
+               IGP01E1000_PHY_AGC_PARAM_B,
+               IGP01E1000_PHY_AGC_PARAM_C,
+               IGP01E1000_PHY_AGC_PARAM_D
+       };
+       u16 min_length, max_length;
+
+       DEBUGFUNC("e1000_config_dsp_after_link_change");
+
+       if (hw->phy_type != e1000_phy_igp)
+               return E1000_SUCCESS;
+
+       if (link_up) {
+               ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
+               if (ret_val) {
+                       DEBUGOUT("Error getting link speed and duplex\n");
+                       return ret_val;
+               }
+
+               if (speed == SPEED_1000) {
+
+                       ret_val =
+                           e1000_get_cable_length(hw, &min_length,
+                                                  &max_length);
+                       if (ret_val)
+                               return ret_val;
+
+                       if ((hw->dsp_config_state == e1000_dsp_config_enabled)
+                           && min_length >= e1000_igp_cable_length_50) {
+
+                               for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
+                                       ret_val =
+                                           e1000_read_phy_reg(hw,
+                                                              dsp_reg_array[i],
+                                                              &phy_data);
+                                       if (ret_val)
+                                               return ret_val;
+
+                                       phy_data &=
+                                           ~IGP01E1000_PHY_EDAC_MU_INDEX;
+
+                                       ret_val =
+                                           e1000_write_phy_reg(hw,
+                                                               dsp_reg_array
+                                                               [i], phy_data);
+                                       if (ret_val)
+                                               return ret_val;
+                               }
+                               hw->dsp_config_state =
+                                   e1000_dsp_config_activated;
+                       }
+
+                       if ((hw->ffe_config_state == e1000_ffe_config_enabled)
+                           && (min_length < e1000_igp_cable_length_50)) {
+
+                               u16 ffe_idle_err_timeout =
+                                   FFE_IDLE_ERR_COUNT_TIMEOUT_20;
+                               u32 idle_errs = 0;
+
+                               /* clear previous idle error counts */
+                               ret_val =
+                                   e1000_read_phy_reg(hw, PHY_1000T_STATUS,
+                                                      &phy_data);
+                               if (ret_val)
+                                       return ret_val;
+
+                               for (i = 0; i < ffe_idle_err_timeout; i++) {
+                                       udelay(1000);
+                                       ret_val =
+                                           e1000_read_phy_reg(hw,
+                                                              PHY_1000T_STATUS,
+                                                              &phy_data);
+                                       if (ret_val)
+                                               return ret_val;
+
+                                       idle_errs +=
+                                           (phy_data &
+                                            SR_1000T_IDLE_ERROR_CNT);
+                                       if (idle_errs >
+                                           SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT)
+                                       {
+                                               hw->ffe_config_state =
+                                                   e1000_ffe_config_active;
+
+                                               ret_val =
+                                                   e1000_write_phy_reg(hw,
+                                                                       IGP01E1000_PHY_DSP_FFE,
+                                                                       IGP01E1000_PHY_DSP_FFE_CM_CP);
+                                               if (ret_val)
+                                                       return ret_val;
+                                               break;
+                                       }
+
+                                       if (idle_errs)
+                                               ffe_idle_err_timeout =
+                                                   FFE_IDLE_ERR_COUNT_TIMEOUT_100;
+                               }
+                       }
+               }
+       } else {
+               if (hw->dsp_config_state == e1000_dsp_config_activated) {
+                       /* Save off the current value of register 0x2F5B to be restored at
+                        * the end of the routines. */
+                       ret_val =
+                           e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
+
+                       if (ret_val)
+                               return ret_val;
+
+                       /* Disable the PHY transmitter */
+                       ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
+
+                       if (ret_val)
+                               return ret_val;
+
+                       mdelay(20);
+
+                       ret_val = e1000_write_phy_reg(hw, 0x0000,
+                                                     IGP01E1000_IEEE_FORCE_GIGA);
+                       if (ret_val)
+                               return ret_val;
+                       for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
+                               ret_val =
+                                   e1000_read_phy_reg(hw, dsp_reg_array[i],
+                                                      &phy_data);
+                               if (ret_val)
+                                       return ret_val;
+
+                               phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
+                               phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
+
+                               ret_val =
+                                   e1000_write_phy_reg(hw, dsp_reg_array[i],
+                                                       phy_data);
+                               if (ret_val)
+                                       return ret_val;
+                       }
+
+                       ret_val = e1000_write_phy_reg(hw, 0x0000,
+                                                     IGP01E1000_IEEE_RESTART_AUTONEG);
+                       if (ret_val)
+                               return ret_val;
+
+                       mdelay(20);
+
+                       /* Now enable the transmitter */
+                       ret_val =
+                           e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
+
+                       if (ret_val)
+                               return ret_val;
+
+                       hw->dsp_config_state = e1000_dsp_config_enabled;
+               }
+
+               if (hw->ffe_config_state == e1000_ffe_config_active) {
+                       /* Save off the current value of register 0x2F5B to be restored at
+                        * the end of the routines. */
+                       ret_val =
+                           e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
+
+                       if (ret_val)
+                               return ret_val;
+
+                       /* Disable the PHY transmitter */
+                       ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
+
+                       if (ret_val)
+                               return ret_val;
+
+                       mdelay(20);
+
+                       ret_val = e1000_write_phy_reg(hw, 0x0000,
+                                                     IGP01E1000_IEEE_FORCE_GIGA);
+                       if (ret_val)
+                               return ret_val;
+                       ret_val =
+                           e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
+                                               IGP01E1000_PHY_DSP_FFE_DEFAULT);
+                       if (ret_val)
+                               return ret_val;
+
+                       ret_val = e1000_write_phy_reg(hw, 0x0000,
+                                                     IGP01E1000_IEEE_RESTART_AUTONEG);
+                       if (ret_val)
+                               return ret_val;
+
+                       mdelay(20);
+
+                       /* Now enable the transmitter */
+                       ret_val =
+                           e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
+
+                       if (ret_val)
+                               return ret_val;
+
+                       hw->ffe_config_state = e1000_ffe_config_enabled;
+               }
+       }
+       return E1000_SUCCESS;
 }
 
-/*****************************************************************************
- * Set PHY to class A mode
+/**
+ * e1000_set_phy_mode - Set PHY to class A mode
+ * @hw: Struct containing variables accessed by shared code
+ *
  * Assumes the following operations will follow to enable the new class mode.
  *  1. Do a PHY soft reset
  *  2. Restart auto-negotiation or force link.
- *
- * hw - Struct containing variables accessed by shared code
- ****************************************************************************/
+ */
 static s32 e1000_set_phy_mode(struct e1000_hw *hw)
 {
-    s32 ret_val;
-    u16 eeprom_data;
-
-    DEBUGFUNC("e1000_set_phy_mode");
-
-    if ((hw->mac_type == e1000_82545_rev_3) &&
-        (hw->media_type == e1000_media_type_copper)) {
-        ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
-        if (ret_val) {
-            return ret_val;
-        }
-
-        if ((eeprom_data != EEPROM_RESERVED_WORD) &&
-            (eeprom_data & EEPROM_PHY_CLASS_A)) {
-            ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
-            if (ret_val)
-                return ret_val;
-            ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
-            if (ret_val)
-                return ret_val;
-
-            hw->phy_reset_disable = false;
-        }
-    }
-
-    return E1000_SUCCESS;
+       s32 ret_val;
+       u16 eeprom_data;
+
+       DEBUGFUNC("e1000_set_phy_mode");
+
+       if ((hw->mac_type == e1000_82545_rev_3) &&
+           (hw->media_type == e1000_media_type_copper)) {
+               ret_val =
+                   e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,
+                                     &eeprom_data);
+               if (ret_val) {
+                       return ret_val;
+               }
+
+               if ((eeprom_data != EEPROM_RESERVED_WORD) &&
+                   (eeprom_data & EEPROM_PHY_CLASS_A)) {
+                       ret_val =
+                           e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
+                                               0x000B);
+                       if (ret_val)
+                               return ret_val;
+                       ret_val =
+                           e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
+                                               0x8104);
+                       if (ret_val)
+                               return ret_val;
+
+                       hw->phy_reset_disable = false;
+               }
+       }
+
+       return E1000_SUCCESS;
 }
 
-/*****************************************************************************
+/**
+ * e1000_set_d3_lplu_state - set d3 link power state
+ * @hw: Struct containing variables accessed by shared code
+ * @active: true to enable lplu false to disable lplu.
  *
  * This function sets the lplu state according to the active flag.  When
  * activating lplu this function also disables smart speed and vise versa.
- * lplu will not be activated unless the device autonegotiation advertisment
+ * lplu will not be activated unless the device autonegotiation advertisement
  * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
- * hw: Struct containing variables accessed by shared code
- * active - true to enable lplu false to disable lplu.
  *
  * returns: - E1000_ERR_PHY if fail to read/write the PHY
  *            E1000_SUCCESS at any other case.
- *
- ****************************************************************************/
-
+ */
 static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
 {
-    s32 ret_val;
-    u16 phy_data;
-    DEBUGFUNC("e1000_set_d3_lplu_state");
-
-    if (hw->phy_type != e1000_phy_igp)
-        return E1000_SUCCESS;
-
-    /* During driver activity LPLU should not be used or it will attain link
-     * from the lowest speeds starting from 10Mbps. The capability is used for
-     * Dx transitions and states */
-    if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
-        ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
-        if (ret_val)
-            return ret_val;
-    } else {
-        ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
-        if (ret_val)
-            return ret_val;
-    }
-
-    if (!active) {
-        if (hw->mac_type == e1000_82541_rev_2 ||
-            hw->mac_type == e1000_82547_rev_2) {
-            phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
-            ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
-            if (ret_val)
-                return ret_val;
-        } else {
-            phy_data &= ~IGP02E1000_PM_D3_LPLU;
-            ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
-                                          phy_data);
-            if (ret_val)
-                return ret_val;
-        }
-
-        /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
-         * Dx states where the power conservation is most important.  During
-         * driver activity we should enable SmartSpeed, so performance is
-         * maintained. */
-        if (hw->smart_speed == e1000_smart_speed_on) {
-            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-                                         &phy_data);
-            if (ret_val)
-                return ret_val;
-
-            phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
-            ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-                                          phy_data);
-            if (ret_val)
-                return ret_val;
-        } else if (hw->smart_speed == e1000_smart_speed_off) {
-            ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-                                         &phy_data);
-            if (ret_val)
-                return ret_val;
-
-            phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
-            ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-                                          phy_data);
-            if (ret_val)
-                return ret_val;
-        }
-
-    } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
-               (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
-               (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
-
-        if (hw->mac_type == e1000_82541_rev_2 ||
-            hw->mac_type == e1000_82547_rev_2) {
-            phy_data |= IGP01E1000_GMII_FLEX_SPD;
-            ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
-            if (ret_val)
-                return ret_val;
-        } else {
-            phy_data |= IGP02E1000_PM_D3_LPLU;
-            ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
-                                          phy_data);
-            if (ret_val)
-                return ret_val;
-        }
-
-        /* When LPLU is enabled we should disable SmartSpeed */
-        ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
-        if (ret_val)
-            return ret_val;
-
-        phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
-        ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
-        if (ret_val)
-            return ret_val;
-
-    }
-    return E1000_SUCCESS;
+       s32 ret_val;
+       u16 phy_data;
+       DEBUGFUNC("e1000_set_d3_lplu_state");
+
+       if (hw->phy_type != e1000_phy_igp)
+               return E1000_SUCCESS;
+
+       /* During driver activity LPLU should not be used or it will attain link
+        * from the lowest speeds starting from 10Mbps. The capability is used for
+        * Dx transitions and states */
+       if (hw->mac_type == e1000_82541_rev_2
+           || hw->mac_type == e1000_82547_rev_2) {
+               ret_val =
+                   e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
+               if (ret_val)
+                       return ret_val;
+       }
+
+       if (!active) {
+               if (hw->mac_type == e1000_82541_rev_2 ||
+                   hw->mac_type == e1000_82547_rev_2) {
+                       phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
+                       ret_val =
+                           e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
+                                               phy_data);
+                       if (ret_val)
+                               return ret_val;
+               }
+
+               /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used during
+                * Dx states where the power conservation is most important.  During
+                * driver activity we should enable SmartSpeed, so performance is
+                * maintained. */
+               if (hw->smart_speed == e1000_smart_speed_on) {
+                       ret_val =
+                           e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                              &phy_data);
+                       if (ret_val)
+                               return ret_val;
+
+                       phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
+                       ret_val =
+                           e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                               phy_data);
+                       if (ret_val)
+                               return ret_val;
+               } else if (hw->smart_speed == e1000_smart_speed_off) {
+                       ret_val =
+                           e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                              &phy_data);
+                       if (ret_val)
+                               return ret_val;
+
+                       phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+                       ret_val =
+                           e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                               phy_data);
+                       if (ret_val)
+                               return ret_val;
+               }
+       } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
+                  || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL)
+                  || (hw->autoneg_advertised ==
+                      AUTONEG_ADVERTISE_10_100_ALL)) {
+
+               if (hw->mac_type == e1000_82541_rev_2 ||
+                   hw->mac_type == e1000_82547_rev_2) {
+                       phy_data |= IGP01E1000_GMII_FLEX_SPD;
+                       ret_val =
+                           e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
+                                               phy_data);
+                       if (ret_val)
+                               return ret_val;
+               }
+
+               /* When LPLU is enabled we should disable SmartSpeed */
+               ret_val =
+                   e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                      &phy_data);
+               if (ret_val)
+                       return ret_val;
+
+               phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
+               ret_val =
+                   e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
+                                       phy_data);
+               if (ret_val)
+                       return ret_val;
+
+       }
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Change VCO speed register to improve Bit Error Rate performance of SERDES.
+/**
+ * e1000_set_vco_speed
+ * @hw: Struct containing variables accessed by shared code
  *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
+ * Change VCO speed register to improve Bit Error Rate performance of SERDES.
+ */
 static s32 e1000_set_vco_speed(struct e1000_hw *hw)
 {
-    s32  ret_val;
-    u16 default_page = 0;
-    u16 phy_data;
+       s32 ret_val;
+       u16 default_page = 0;
+       u16 phy_data;
 
-    DEBUGFUNC("e1000_set_vco_speed");
+       DEBUGFUNC("e1000_set_vco_speed");
 
-    switch (hw->mac_type) {
-    case e1000_82545_rev_3:
-    case e1000_82546_rev_3:
-       break;
-    default:
-        return E1000_SUCCESS;
-    }
+       switch (hw->mac_type) {
+       case e1000_82545_rev_3:
+       case e1000_82546_rev_3:
+               break;
+       default:
+               return E1000_SUCCESS;
+       }
 
-    /* Set PHY register 30, page 5, bit 8 to 0 */
+       /* Set PHY register 30, page 5, bit 8 to 0 */
 
-    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
-    if (ret_val)
-        return ret_val;
+       ret_val =
+           e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
+       if (ret_val)
+               return ret_val;
 
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
-    if (ret_val)
-        return ret_val;
+       ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
+       if (ret_val)
+               return ret_val;
 
-    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
-    if (ret_val)
-        return ret_val;
+       ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
+       if (ret_val)
+               return ret_val;
 
-    phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
-    if (ret_val)
-        return ret_val;
+       phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
+       ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
+       if (ret_val)
+               return ret_val;
 
-    /* Set PHY register 30, page 4, bit 11 to 1 */
+       /* Set PHY register 30, page 4, bit 11 to 1 */
 
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
-    if (ret_val)
-        return ret_val;
+       ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
+       if (ret_val)
+               return ret_val;
 
-    ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
-    if (ret_val)
-        return ret_val;
+       ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
+       if (ret_val)
+               return ret_val;
 
-    phy_data |= M88E1000_PHY_VCO_REG_BIT11;
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
-    if (ret_val)
-        return ret_val;
+       phy_data |= M88E1000_PHY_VCO_REG_BIT11;
+       ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
+       if (ret_val)
+               return ret_val;
 
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
-    if (ret_val)
-        return ret_val;
+       ret_val =
+           e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
+       if (ret_val)
+               return ret_val;
 
-    return E1000_SUCCESS;
+       return E1000_SUCCESS;
 }
 
 
-/******************************************************************************
- * Verifies the hardware needs to allow ARPs to be processed by the host
- *
- * hw - Struct containing variables accessed by shared code
+/**
+ * e1000_enable_mng_pass_thru - check for bmc pass through
+ * @hw: Struct containing variables accessed by shared code
  *
+ * Verifies the hardware needs to allow ARPs to be processed by the host
  * returns: - true/false
- *
- *****************************************************************************/
+ */
 u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
 {
-    u32 manc;
-
-    if (hw->asf_firmware_present) {
-        manc = er32(MANC);
-
-        if (!(manc & E1000_MANC_RCV_TCO_EN) ||
-            !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
-            return false;
-        if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
-            return true;
-    }
-    return false;
+       u32 manc;
+
+       if (hw->asf_firmware_present) {
+               manc = er32(MANC);
+
+               if (!(manc & E1000_MANC_RCV_TCO_EN) ||
+                   !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
+                       return false;
+               if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
+                       return true;
+       }
+       return false;
 }
 
 static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
 {
-    s32 ret_val;
-    u16 mii_status_reg;
-    u16 i;
-
-    /* Polarity reversal workaround for forced 10F/10H links. */
-
-    /* Disable the transmitter on the PHY */
-
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
-    if (ret_val)
-        return ret_val;
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
-    if (ret_val)
-        return ret_val;
-
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
-    if (ret_val)
-        return ret_val;
-
-    /* This loop will early-out if the NO link condition has been met. */
-    for (i = PHY_FORCE_TIME; i > 0; i--) {
-        /* Read the MII Status Register and wait for Link Status bit
-         * to be clear.
-         */
-
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-        if (ret_val)
-            return ret_val;
-
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-        if (ret_val)
-            return ret_val;
-
-        if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
-        mdelay(100);
-    }
-
-    /* Recommended delay time after link has been lost */
-    mdelay(1000);
-
-    /* Now we will re-enable th transmitter on the PHY */
-
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
-    if (ret_val)
-        return ret_val;
-    mdelay(50);
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
-    if (ret_val)
-        return ret_val;
-    mdelay(50);
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
-    if (ret_val)
-        return ret_val;
-    mdelay(50);
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
-    if (ret_val)
-        return ret_val;
-
-    ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
-    if (ret_val)
-        return ret_val;
-
-    /* This loop will early-out if the link condition has been met. */
-    for (i = PHY_FORCE_TIME; i > 0; i--) {
-        /* Read the MII Status Register and wait for Link Status bit
-         * to be set.
-         */
-
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-        if (ret_val)
-            return ret_val;
-
-        ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
-        if (ret_val)
-            return ret_val;
-
-        if (mii_status_reg & MII_SR_LINK_STATUS) break;
-        mdelay(100);
-    }
-    return E1000_SUCCESS;
+       s32 ret_val;
+       u16 mii_status_reg;
+       u16 i;
+
+       /* Polarity reversal workaround for forced 10F/10H links. */
+
+       /* Disable the transmitter on the PHY */
+
+       ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
+       if (ret_val)
+               return ret_val;
+       ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
+       if (ret_val)
+               return ret_val;
+
+       ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
+       if (ret_val)
+               return ret_val;
+
+       /* This loop will early-out if the NO link condition has been met. */
+       for (i = PHY_FORCE_TIME; i > 0; i--) {
+               /* Read the MII Status Register and wait for Link Status bit
+                * to be clear.
+                */
+
+               ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+               if (ret_val)
+                       return ret_val;
+
+               ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+               if (ret_val)
+                       return ret_val;
+
+               if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
+                       break;
+               mdelay(100);
+       }
+
+       /* Recommended delay time after link has been lost */
+       mdelay(1000);
+
+       /* Now we will re-enable th transmitter on the PHY */
+
+       ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
+       if (ret_val)
+               return ret_val;
+       mdelay(50);
+       ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
+       if (ret_val)
+               return ret_val;
+       mdelay(50);
+       ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
+       if (ret_val)
+               return ret_val;
+       mdelay(50);
+       ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
+       if (ret_val)
+               return ret_val;
+
+       ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
+       if (ret_val)
+               return ret_val;
+
+       /* This loop will early-out if the link condition has been met. */
+       for (i = PHY_FORCE_TIME; i > 0; i--) {
+               /* Read the MII Status Register and wait for Link Status bit
+                * to be set.
+                */
+
+               ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+               if (ret_val)
+                       return ret_val;
+
+               ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
+               if (ret_val)
+                       return ret_val;
+
+               if (mii_status_reg & MII_SR_LINK_STATUS)
+                       break;
+               mdelay(100);
+       }
+       return E1000_SUCCESS;
 }
 
-/*******************************************************************************
+/**
+ * e1000_get_auto_rd_done
+ * @hw: Struct containing variables accessed by shared code
  *
  * Check for EEPROM Auto Read bit done.
- *
- * hw: Struct containing variables accessed by shared code
- *
  * returns: - E1000_ERR_RESET if fail to reset MAC
  *            E1000_SUCCESS at any other case.
- *
- ******************************************************************************/
+ */
 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
 {
-    DEBUGFUNC("e1000_get_auto_rd_done");
-    msleep(5);
-    return E1000_SUCCESS;
+       DEBUGFUNC("e1000_get_auto_rd_done");
+       msleep(5);
+       return E1000_SUCCESS;
 }
 
-/***************************************************************************
- * Checks if the PHY configuration is done
- *
- * hw: Struct containing variables accessed by shared code
+/**
+ * e1000_get_phy_cfg_done
+ * @hw: Struct containing variables accessed by shared code
  *
+ * Checks if the PHY configuration is done
  * returns: - E1000_ERR_RESET if fail to reset MAC
  *            E1000_SUCCESS at any other case.
- *
- ***************************************************************************/
+ */
 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
 {
-    DEBUGFUNC("e1000_get_phy_cfg_done");
-    mdelay(10);
-    return E1000_SUCCESS;
+       DEBUGFUNC("e1000_get_phy_cfg_done");
+       mdelay(10);
+       return E1000_SUCCESS;
 }
index 1c782d2ff04e916eea58d41a03b31050e7baf1d0..4bfdf323b589af74c90ab1009d55f349ed870b1a 100644 (file)
@@ -35,7 +35,6 @@
 
 #include "e1000_osdep.h"
 
-
 /* Forward declarations of structures used by the shared code */
 struct e1000_hw;
 struct e1000_hw_stats;
@@ -43,169 +42,169 @@ struct e1000_hw_stats;
 /* Enumerated types specific to the e1000 hardware */
 /* Media Access Controlers */
 typedef enum {
-    e1000_undefined = 0,
-    e1000_82542_rev2_0,
-    e1000_82542_rev2_1,
-    e1000_82543,
-    e1000_82544,
-    e1000_82540,
-    e1000_82545,
-    e1000_82545_rev_3,
-    e1000_82546,
-    e1000_82546_rev_3,
-    e1000_82541,
-    e1000_82541_rev_2,
-    e1000_82547,
-    e1000_82547_rev_2,
-    e1000_num_macs
+       e1000_undefined = 0,
+       e1000_82542_rev2_0,
+       e1000_82542_rev2_1,
+       e1000_82543,
+       e1000_82544,
+       e1000_82540,
+       e1000_82545,
+       e1000_82545_rev_3,
+       e1000_82546,
+       e1000_82546_rev_3,
+       e1000_82541,
+       e1000_82541_rev_2,
+       e1000_82547,
+       e1000_82547_rev_2,
+       e1000_num_macs
 } e1000_mac_type;
 
 typedef enum {
-    e1000_eeprom_uninitialized = 0,
-    e1000_eeprom_spi,
-    e1000_eeprom_microwire,
-    e1000_eeprom_flash,
-    e1000_eeprom_none, /* No NVM support */
-    e1000_num_eeprom_types
+       e1000_eeprom_uninitialized = 0,
+       e1000_eeprom_spi,
+       e1000_eeprom_microwire,
+       e1000_eeprom_flash,
+       e1000_eeprom_none,      /* No NVM support */
+       e1000_num_eeprom_types
 } e1000_eeprom_type;
 
 /* Media Types */
 typedef enum {
-    e1000_media_type_copper = 0,
-    e1000_media_type_fiber = 1,
-    e1000_media_type_internal_serdes = 2,
-    e1000_num_media_types
+       e1000_media_type_copper = 0,
+       e1000_media_type_fiber = 1,
+       e1000_media_type_internal_serdes = 2,
+       e1000_num_media_types
 } e1000_media_type;
 
 typedef enum {
-    e1000_10_half = 0,
-    e1000_10_full = 1,
-    e1000_100_half = 2,
-    e1000_100_full = 3
+       e1000_10_half = 0,
+       e1000_10_full = 1,
+       e1000_100_half = 2,
+       e1000_100_full = 3
 } e1000_speed_duplex_type;
 
 /* Flow Control Settings */
 typedef enum {
-    E1000_FC_NONE = 0,
-    E1000_FC_RX_PAUSE = 1,
-    E1000_FC_TX_PAUSE = 2,
-    E1000_FC_FULL = 3,
-    E1000_FC_DEFAULT = 0xFF
+       E1000_FC_NONE = 0,
+       E1000_FC_RX_PAUSE = 1,
+       E1000_FC_TX_PAUSE = 2,
+       E1000_FC_FULL = 3,
+       E1000_FC_DEFAULT = 0xFF
 } e1000_fc_type;
 
 struct e1000_shadow_ram {
-    u16 eeprom_word;
-    bool modified;
+       u16 eeprom_word;
+       bool modified;
 };
 
 /* PCI bus types */
 typedef enum {
-    e1000_bus_type_unknown = 0,
-    e1000_bus_type_pci,
-    e1000_bus_type_pcix,
-    e1000_bus_type_reserved
+       e1000_bus_type_unknown = 0,
+       e1000_bus_type_pci,
+       e1000_bus_type_pcix,
+       e1000_bus_type_reserved
 } e1000_bus_type;
 
 /* PCI bus speeds */
 typedef enum {
-    e1000_bus_speed_unknown = 0,
-    e1000_bus_speed_33,
-    e1000_bus_speed_66,
-    e1000_bus_speed_100,
-    e1000_bus_speed_120,
-    e1000_bus_speed_133,
-    e1000_bus_speed_reserved
+       e1000_bus_speed_unknown = 0,
+       e1000_bus_speed_33,
+       e1000_bus_speed_66,
+       e1000_bus_speed_100,
+       e1000_bus_speed_120,
+       e1000_bus_speed_133,
+       e1000_bus_speed_reserved
 } e1000_bus_speed;
 
 /* PCI bus widths */
 typedef enum {
-    e1000_bus_width_unknown = 0,
-    e1000_bus_width_32,
-    e1000_bus_width_64,
-    e1000_bus_width_reserved
+       e1000_bus_width_unknown = 0,
+       e1000_bus_width_32,
+       e1000_bus_width_64,
+       e1000_bus_width_reserved
 } e1000_bus_width;
 
 /* PHY status info structure and supporting enums */
 typedef enum {
-    e1000_cable_length_50 = 0,
-    e1000_cable_length_50_80,
-    e1000_cable_length_80_110,
-    e1000_cable_length_110_140,
-    e1000_cable_length_140,
-    e1000_cable_length_undefined = 0xFF
+       e1000_cable_length_50 = 0,
+       e1000_cable_length_50_80,
+       e1000_cable_length_80_110,
+       e1000_cable_length_110_140,
+       e1000_cable_length_140,
+       e1000_cable_length_undefined = 0xFF
 } e1000_cable_length;
 
 typedef enum {
-    e1000_gg_cable_length_60 = 0,
-    e1000_gg_cable_length_60_115 = 1,
-    e1000_gg_cable_length_115_150 = 2,
-    e1000_gg_cable_length_150 = 4
+       e1000_gg_cable_length_60 = 0,
+       e1000_gg_cable_length_60_115 = 1,
+       e1000_gg_cable_length_115_150 = 2,
+       e1000_gg_cable_length_150 = 4
 } e1000_gg_cable_length;
 
 typedef enum {
-    e1000_igp_cable_length_10  = 10,
-    e1000_igp_cable_length_20  = 20,
-    e1000_igp_cable_length_30  = 30,
-    e1000_igp_cable_length_40  = 40,
-    e1000_igp_cable_length_50  = 50,
-    e1000_igp_cable_length_60  = 60,
-    e1000_igp_cable_length_70  = 70,
-    e1000_igp_cable_length_80  = 80,
-    e1000_igp_cable_length_90  = 90,
-    e1000_igp_cable_length_100 = 100,
-    e1000_igp_cable_length_110 = 110,
-    e1000_igp_cable_length_115 = 115,
-    e1000_igp_cable_length_120 = 120,
-    e1000_igp_cable_length_130 = 130,
-    e1000_igp_cable_length_140 = 140,
-    e1000_igp_cable_length_150 = 150,
-    e1000_igp_cable_length_160 = 160,
-    e1000_igp_cable_length_170 = 170,
-    e1000_igp_cable_length_180 = 180
+       e1000_igp_cable_length_10 = 10,
+       e1000_igp_cable_length_20 = 20,
+       e1000_igp_cable_length_30 = 30,
+       e1000_igp_cable_length_40 = 40,
+       e1000_igp_cable_length_50 = 50,
+       e1000_igp_cable_length_60 = 60,
+       e1000_igp_cable_length_70 = 70,
+       e1000_igp_cable_length_80 = 80,
+       e1000_igp_cable_length_90 = 90,
+       e1000_igp_cable_length_100 = 100,
+       e1000_igp_cable_length_110 = 110,
+       e1000_igp_cable_length_115 = 115,
+       e1000_igp_cable_length_120 = 120,
+       e1000_igp_cable_length_130 = 130,
+       e1000_igp_cable_length_140 = 140,
+       e1000_igp_cable_length_150 = 150,
+       e1000_igp_cable_length_160 = 160,
+       e1000_igp_cable_length_170 = 170,
+       e1000_igp_cable_length_180 = 180
 } e1000_igp_cable_length;
 
 typedef enum {
-    e1000_10bt_ext_dist_enable_normal = 0,
-    e1000_10bt_ext_dist_enable_lower,
-    e1000_10bt_ext_dist_enable_undefined = 0xFF
+       e1000_10bt_ext_dist_enable_normal = 0,
+       e1000_10bt_ext_dist_enable_lower,
+       e1000_10bt_ext_dist_enable_undefined = 0xFF
 } e1000_10bt_ext_dist_enable;
 
 typedef enum {
-    e1000_rev_polarity_normal = 0,
-    e1000_rev_polarity_reversed,
-    e1000_rev_polarity_undefined = 0xFF
+       e1000_rev_polarity_normal = 0,
+       e1000_rev_polarity_reversed,
+       e1000_rev_polarity_undefined = 0xFF
 } e1000_rev_polarity;
 
 typedef enum {
-    e1000_downshift_normal = 0,
-    e1000_downshift_activated,
-    e1000_downshift_undefined = 0xFF
+       e1000_downshift_normal = 0,
+       e1000_downshift_activated,
+       e1000_downshift_undefined = 0xFF
 } e1000_downshift;
 
 typedef enum {
-    e1000_smart_speed_default = 0,
-    e1000_smart_speed_on,
-    e1000_smart_speed_off
+       e1000_smart_speed_default = 0,
+       e1000_smart_speed_on,
+       e1000_smart_speed_off
 } e1000_smart_speed;
 
 typedef enum {
-    e1000_polarity_reversal_enabled = 0,
-    e1000_polarity_reversal_disabled,
-    e1000_polarity_reversal_undefined = 0xFF
+       e1000_polarity_reversal_enabled = 0,
+       e1000_polarity_reversal_disabled,
+       e1000_polarity_reversal_undefined = 0xFF
 } e1000_polarity_reversal;
 
 typedef enum {
-    e1000_auto_x_mode_manual_mdi = 0,
-    e1000_auto_x_mode_manual_mdix,
-    e1000_auto_x_mode_auto1,
-    e1000_auto_x_mode_auto2,
-    e1000_auto_x_mode_undefined = 0xFF
+       e1000_auto_x_mode_manual_mdi = 0,
+       e1000_auto_x_mode_manual_mdix,
+       e1000_auto_x_mode_auto1,
+       e1000_auto_x_mode_auto2,
+       e1000_auto_x_mode_undefined = 0xFF
 } e1000_auto_x_mode;
 
 typedef enum {
-    e1000_1000t_rx_status_not_ok = 0,
-    e1000_1000t_rx_status_ok,
-    e1000_1000t_rx_status_undefined = 0xFF
+       e1000_1000t_rx_status_not_ok = 0,
+       e1000_1000t_rx_status_ok,
+       e1000_1000t_rx_status_undefined = 0xFF
 } e1000_1000t_rx_status;
 
 typedef enum {
@@ -215,63 +214,61 @@ typedef enum {
 } e1000_phy_type;
 
 typedef enum {
-    e1000_ms_hw_default = 0,
-    e1000_ms_force_master,
-    e1000_ms_force_slave,
-    e1000_ms_auto
+       e1000_ms_hw_default = 0,
+       e1000_ms_force_master,
+       e1000_ms_force_slave,
+       e1000_ms_auto
 } e1000_ms_type;
 
 typedef enum {
-    e1000_ffe_config_enabled = 0,
-    e1000_ffe_config_active,
-    e1000_ffe_config_blocked
+       e1000_ffe_config_enabled = 0,
+       e1000_ffe_config_active,
+       e1000_ffe_config_blocked
 } e1000_ffe_config;
 
 typedef enum {
-    e1000_dsp_config_disabled = 0,
-    e1000_dsp_config_enabled,
-    e1000_dsp_config_activated,
-    e1000_dsp_config_undefined = 0xFF
+       e1000_dsp_config_disabled = 0,
+       e1000_dsp_config_enabled,
+       e1000_dsp_config_activated,
+       e1000_dsp_config_undefined = 0xFF
 } e1000_dsp_config;
 
 struct e1000_phy_info {
-    e1000_cable_length cable_length;
-    e1000_10bt_ext_dist_enable extended_10bt_distance;
-    e1000_rev_polarity cable_polarity;
-    e1000_downshift downshift;
-    e1000_polarity_reversal polarity_correction;
-    e1000_auto_x_mode mdix_mode;
-    e1000_1000t_rx_status local_rx;
-    e1000_1000t_rx_status remote_rx;
+       e1000_cable_length cable_length;
+       e1000_10bt_ext_dist_enable extended_10bt_distance;
+       e1000_rev_polarity cable_polarity;
+       e1000_downshift downshift;
+       e1000_polarity_reversal polarity_correction;
+       e1000_auto_x_mode mdix_mode;
+       e1000_1000t_rx_status local_rx;
+       e1000_1000t_rx_status remote_rx;
 };
 
 struct e1000_phy_stats {
-    u32 idle_errors;
-    u32 receive_errors;
+       u32 idle_errors;
+       u32 receive_errors;
 };
 
 struct e1000_eeprom_info {
-    e1000_eeprom_type type;
-    u16 word_size;
-    u16 opcode_bits;
-    u16 address_bits;
-    u16 delay_usec;
-    u16 page_size;
-    bool use_eerd;
-    bool use_eewr;
+       e1000_eeprom_type type;
+       u16 word_size;
+       u16 opcode_bits;
+       u16 address_bits;
+       u16 delay_usec;
+       u16 page_size;
+       bool use_eerd;
+       bool use_eewr;
 };
 
 /* Flex ASF Information */
 #define E1000_HOST_IF_MAX_SIZE  2048
 
 typedef enum {
-    e1000_byte_align = 0,
-    e1000_word_align = 1,
-    e1000_dword_align = 2
+       e1000_byte_align = 0,
+       e1000_word_align = 1,
+       e1000_dword_align = 2
 } e1000_align_type;
 
-
-
 /* Error Codes */
 #define E1000_SUCCESS      0
 #define E1000_ERR_EEPROM   1
@@ -300,11 +297,11 @@ s32 e1000_setup_link(struct e1000_hw *hw);
 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
 void e1000_config_collision_dist(struct e1000_hw *hw);
 s32 e1000_check_for_link(struct e1000_hw *hw);
-s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex);
+s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 * speed, u16 * duplex);
 s32 e1000_force_mac_fc(struct e1000_hw *hw);
 
 /* PHY */
-s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data);
+s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 * phy_data);
 s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);
 s32 e1000_phy_hw_reset(struct e1000_hw *hw);
 s32 e1000_phy_reset(struct e1000_hw *hw);
@@ -318,64 +315,64 @@ s32 e1000_init_eeprom_params(struct e1000_hw *hw);
 u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw);
 
 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD   64
-#define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8   /* Host Interface data length */
+#define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8  /* Host Interface data length */
 
-#define E1000_MNG_DHCP_COMMAND_TIMEOUT  10      /* Time in ms to process MNG command */
-#define E1000_MNG_DHCP_COOKIE_OFFSET    0x6F0   /* Cookie offset */
-#define E1000_MNG_DHCP_COOKIE_LENGTH    0x10    /* Cookie length */
+#define E1000_MNG_DHCP_COMMAND_TIMEOUT  10     /* Time in ms to process MNG command */
+#define E1000_MNG_DHCP_COOKIE_OFFSET    0x6F0  /* Cookie offset */
+#define E1000_MNG_DHCP_COOKIE_LENGTH    0x10   /* Cookie length */
 #define E1000_MNG_IAMT_MODE             0x3
 #define E1000_MNG_ICH_IAMT_MODE         0x2
-#define E1000_IAMT_SIGNATURE            0x544D4149 /* Intel(R) Active Management Technology signature */
+#define E1000_IAMT_SIGNATURE            0x544D4149     /* Intel(R) Active Management Technology signature */
 
-#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */
-#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT    0x2 /* DHCP parsing enabled */
+#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1       /* DHCP parsing enabled */
+#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT    0x2       /* DHCP parsing enabled */
 #define E1000_VFTA_ENTRY_SHIFT                       0x5
 #define E1000_VFTA_ENTRY_MASK                        0x7F
 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK              0x1F
 
 struct e1000_host_mng_command_header {
-    u8 command_id;
-    u8 checksum;
-    u16 reserved1;
-    u16 reserved2;
-    u16 command_length;
+       u8 command_id;
+       u8 checksum;
+       u16 reserved1;
+       u16 reserved2;
+       u16 command_length;
 };
 
 struct e1000_host_mng_command_info {
-    struct e1000_host_mng_command_header command_header;  /* Command Head/Command Result Head has 4 bytes */
-    u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];   /* Command data can length 0..0x658*/
+       struct e1000_host_mng_command_header command_header;    /* Command Head/Command Result Head has 4 bytes */
+       u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];  /* Command data can length 0..0x658 */
 };
 #ifdef __BIG_ENDIAN
-struct e1000_host_mng_dhcp_cookie{
-    u32 signature;
-    u16 vlan_id;
-    u8 reserved0;
-    u8 status;
-    u32 reserved1;
-    u8 checksum;
-    u8 reserved3;
-    u16 reserved2;
+struct e1000_host_mng_dhcp_cookie {
+       u32 signature;
+       u16 vlan_id;
+       u8 reserved0;
+       u8 status;
+       u32 reserved1;
+       u8 checksum;
+       u8 reserved3;
+       u16 reserved2;
 };
 #else
-struct e1000_host_mng_dhcp_cookie{
-    u32 signature;
-    u8 status;
-    u8 reserved0;
-    u16 vlan_id;
-    u32 reserved1;
-    u16 reserved2;
-    u8 reserved3;
-    u8 checksum;
+struct e1000_host_mng_dhcp_cookie {
+       u32 signature;
+       u8 status;
+       u8 reserved0;
+       u16 vlan_id;
+       u32 reserved1;
+       u16 reserved2;
+       u8 reserved3;
+       u8 checksum;
 };
 #endif
 
 bool e1000_check_mng_mode(struct e1000_hw *hw);
 bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);
-s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 *data);
+s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data);
 s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw);
 s32 e1000_update_eeprom_checksum(struct e1000_hw *hw);
-s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 *data);
-s32 e1000_read_mac_addr(struct e1000_hw * hw);
+s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data);
+s32 e1000_read_mac_addr(struct e1000_hw *hw);
 
 /* Filters (multicast, vlan, receive) */
 u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 * mc_addr);
@@ -395,7 +392,8 @@ s32 e1000_blink_led_start(struct e1000_hw *hw);
 /* Everything else */
 void e1000_reset_adaptive(struct e1000_hw *hw);
 void e1000_update_adaptive(struct e1000_hw *hw);
-void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, u32 frame_len, u8 * mac_addr);
+void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
+                           u32 frame_len, u8 * mac_addr);
 void e1000_get_bus_info(struct e1000_hw *hw);
 void e1000_pci_set_mwi(struct e1000_hw *hw);
 void e1000_pci_clear_mwi(struct e1000_hw *hw);
@@ -404,7 +402,6 @@ int e1000_pcix_get_mmrbc(struct e1000_hw *hw);
 /* Port I/O is only supported on 82544 and newer */
 void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);
 
-
 #define E1000_READ_REG_IO(a, reg) \
     e1000_read_reg_io((a), E1000_##reg)
 #define E1000_WRITE_REG_IO(a, reg, val) \
@@ -469,21 +466,20 @@ void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);
 
 /* The sizes (in bytes) of a ethernet packet */
 #define ENET_HEADER_SIZE             14
-#define MINIMUM_ETHERNET_FRAME_SIZE  64   /* With FCS */
+#define MINIMUM_ETHERNET_FRAME_SIZE  64        /* With FCS */
 #define ETHERNET_FCS_SIZE            4
 #define MINIMUM_ETHERNET_PACKET_SIZE \
     (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
 #define CRC_LENGTH                   ETHERNET_FCS_SIZE
 #define MAX_JUMBO_FRAME_SIZE         0x3F00
 
-
 /* 802.1q VLAN Packet Sizes */
-#define VLAN_TAG_SIZE  4     /* 802.3ac tag (not DMAed) */
+#define VLAN_TAG_SIZE  4       /* 802.3ac tag (not DMAed) */
 
 /* Ethertype field values */
-#define ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.3ac packet */
-#define ETHERNET_IP_TYPE        0x0800  /* IP packets */
-#define ETHERNET_ARP_TYPE       0x0806  /* Address Resolution Protocol (ARP) */
+#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
+#define ETHERNET_IP_TYPE        0x0800 /* IP packets */
+#define ETHERNET_ARP_TYPE       0x0806 /* Address Resolution Protocol (ARP) */
 
 /* Packet Header defines */
 #define IP_PROTOCOL_TCP    6
@@ -525,93 +521,93 @@ void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);
 
 /* Receive Descriptor */
 struct e1000_rx_desc {
-    __le64 buffer_addr; /* Address of the descriptor's data buffer */
-    __le16 length;     /* Length of data DMAed into data buffer */
-    __le16 csum;       /* Packet checksum */
-    u8 status;      /* Descriptor status */
-    u8 errors;      /* Descriptor Errors */
-    __le16 special;
+       __le64 buffer_addr;     /* Address of the descriptor's data buffer */
+       __le16 length;          /* Length of data DMAed into data buffer */
+       __le16 csum;            /* Packet checksum */
+       u8 status;              /* Descriptor status */
+       u8 errors;              /* Descriptor Errors */
+       __le16 special;
 };
 
 /* Receive Descriptor - Extended */
 union e1000_rx_desc_extended {
-    struct {
-        __le64 buffer_addr;
-        __le64 reserved;
-    } read;
-    struct {
-        struct {
-            __le32 mrq;              /* Multiple Rx Queues */
-            union {
-                __le32 rss;          /* RSS Hash */
-                struct {
-                    __le16 ip_id;    /* IP id */
-                    __le16 csum;     /* Packet Checksum */
-                } csum_ip;
-            } hi_dword;
-        } lower;
-        struct {
-            __le32 status_error;     /* ext status/error */
-            __le16 length;
-            __le16 vlan;             /* VLAN tag */
-        } upper;
-    } wb;  /* writeback */
+       struct {
+               __le64 buffer_addr;
+               __le64 reserved;
+       } read;
+       struct {
+               struct {
+                       __le32 mrq;     /* Multiple Rx Queues */
+                       union {
+                               __le32 rss;     /* RSS Hash */
+                               struct {
+                                       __le16 ip_id;   /* IP id */
+                                       __le16 csum;    /* Packet Checksum */
+                               } csum_ip;
+                       } hi_dword;
+               } lower;
+               struct {
+                       __le32 status_error;    /* ext status/error */
+                       __le16 length;
+                       __le16 vlan;    /* VLAN tag */
+               } upper;
+       } wb;                   /* writeback */
 };
 
 #define MAX_PS_BUFFERS 4
 /* Receive Descriptor - Packet Split */
 union e1000_rx_desc_packet_split {
-    struct {
-        /* one buffer for protocol header(s), three data buffers */
-        __le64 buffer_addr[MAX_PS_BUFFERS];
-    } read;
-    struct {
-        struct {
-            __le32 mrq;              /* Multiple Rx Queues */
-            union {
-                __le32 rss;          /* RSS Hash */
-                struct {
-                    __le16 ip_id;    /* IP id */
-                    __le16 csum;     /* Packet Checksum */
-                } csum_ip;
-            } hi_dword;
-        } lower;
-        struct {
-            __le32 status_error;     /* ext status/error */
-            __le16 length0;          /* length of buffer 0 */
-            __le16 vlan;             /* VLAN tag */
-        } middle;
-        struct {
-            __le16 header_status;
-            __le16 length[3];        /* length of buffers 1-3 */
-        } upper;
-        __le64 reserved;
-    } wb; /* writeback */
+       struct {
+               /* one buffer for protocol header(s), three data buffers */
+               __le64 buffer_addr[MAX_PS_BUFFERS];
+       } read;
+       struct {
+               struct {
+                       __le32 mrq;     /* Multiple Rx Queues */
+                       union {
+                               __le32 rss;     /* RSS Hash */
+                               struct {
+                                       __le16 ip_id;   /* IP id */
+                                       __le16 csum;    /* Packet Checksum */
+                               } csum_ip;
+                       } hi_dword;
+               } lower;
+               struct {
+                       __le32 status_error;    /* ext status/error */
+                       __le16 length0; /* length of buffer 0 */
+                       __le16 vlan;    /* VLAN tag */
+               } middle;
+               struct {
+                       __le16 header_status;
+                       __le16 length[3];       /* length of buffers 1-3 */
+               } upper;
+               __le64 reserved;
+       } wb;                   /* writeback */
 };
 
-/* Receive Decriptor bit definitions */
-#define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
-#define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
-#define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
-#define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
-#define E1000_RXD_STAT_UDPCS    0x10    /* UDP xsum caculated */
-#define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
-#define E1000_RXD_STAT_IPCS     0x40    /* IP xsum calculated */
-#define E1000_RXD_STAT_PIF      0x80    /* passed in-exact filter */
-#define E1000_RXD_STAT_IPIDV    0x200   /* IP identification valid */
-#define E1000_RXD_STAT_UDPV     0x400   /* Valid UDP checksum */
-#define E1000_RXD_STAT_ACK      0x8000  /* ACK Packet indication */
-#define E1000_RXD_ERR_CE        0x01    /* CRC Error */
-#define E1000_RXD_ERR_SE        0x02    /* Symbol Error */
-#define E1000_RXD_ERR_SEQ       0x04    /* Sequence Error */
-#define E1000_RXD_ERR_CXE       0x10    /* Carrier Extension Error */
-#define E1000_RXD_ERR_TCPE      0x20    /* TCP/UDP Checksum Error */
-#define E1000_RXD_ERR_IPE       0x40    /* IP Checksum Error */
-#define E1000_RXD_ERR_RXE       0x80    /* Rx Data Error */
-#define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */
-#define E1000_RXD_SPC_PRI_MASK  0xE000  /* Priority is in upper 3 bits */
+/* Receive Descriptor bit definitions */
+#define E1000_RXD_STAT_DD       0x01   /* Descriptor Done */
+#define E1000_RXD_STAT_EOP      0x02   /* End of Packet */
+#define E1000_RXD_STAT_IXSM     0x04   /* Ignore checksum */
+#define E1000_RXD_STAT_VP       0x08   /* IEEE VLAN Packet */
+#define E1000_RXD_STAT_UDPCS    0x10   /* UDP xsum calculated */
+#define E1000_RXD_STAT_TCPCS    0x20   /* TCP xsum calculated */
+#define E1000_RXD_STAT_IPCS     0x40   /* IP xsum calculated */
+#define E1000_RXD_STAT_PIF      0x80   /* passed in-exact filter */
+#define E1000_RXD_STAT_IPIDV    0x200  /* IP identification valid */
+#define E1000_RXD_STAT_UDPV     0x400  /* Valid UDP checksum */
+#define E1000_RXD_STAT_ACK      0x8000 /* ACK Packet indication */
+#define E1000_RXD_ERR_CE        0x01   /* CRC Error */
+#define E1000_RXD_ERR_SE        0x02   /* Symbol Error */
+#define E1000_RXD_ERR_SEQ       0x04   /* Sequence Error */
+#define E1000_RXD_ERR_CXE       0x10   /* Carrier Extension Error */
+#define E1000_RXD_ERR_TCPE      0x20   /* TCP/UDP Checksum Error */
+#define E1000_RXD_ERR_IPE       0x40   /* IP Checksum Error */
+#define E1000_RXD_ERR_RXE       0x80   /* Rx Data Error */
+#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
+#define E1000_RXD_SPC_PRI_MASK  0xE000 /* Priority is in upper 3 bits */
 #define E1000_RXD_SPC_PRI_SHIFT 13
-#define E1000_RXD_SPC_CFI_MASK  0x1000  /* CFI is bit 12 */
+#define E1000_RXD_SPC_CFI_MASK  0x1000 /* CFI is bit 12 */
 #define E1000_RXD_SPC_CFI_SHIFT 12
 
 #define E1000_RXDEXT_STATERR_CE    0x01000000
@@ -633,7 +629,6 @@ union e1000_rx_desc_packet_split {
     E1000_RXD_ERR_CXE |                \
     E1000_RXD_ERR_RXE)
 
-
 /* Same mask, but for extended and packet split descriptors */
 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
     E1000_RXDEXT_STATERR_CE  |            \
@@ -642,109 +637,108 @@ union e1000_rx_desc_packet_split {
     E1000_RXDEXT_STATERR_CXE |            \
     E1000_RXDEXT_STATERR_RXE)
 
-
 /* Transmit Descriptor */
 struct e1000_tx_desc {
-    __le64 buffer_addr;       /* Address of the descriptor's data buffer */
-    union {
-        __le32 data;
-        struct {
-            __le16 length;    /* Data buffer length */
-            u8 cso;        /* Checksum offset */
-            u8 cmd;        /* Descriptor control */
-        } flags;
-    } lower;
-    union {
-        __le32 data;
-        struct {
-            u8 status;     /* Descriptor status */
-            u8 css;        /* Checksum start */
-            __le16 special;
-        } fields;
-    } upper;
+       __le64 buffer_addr;     /* Address of the descriptor's data buffer */
+       union {
+               __le32 data;
+               struct {
+                       __le16 length;  /* Data buffer length */
+                       u8 cso; /* Checksum offset */
+                       u8 cmd; /* Descriptor control */
+               } flags;
+       } lower;
+       union {
+               __le32 data;
+               struct {
+                       u8 status;      /* Descriptor status */
+                       u8 css; /* Checksum start */
+                       __le16 special;
+               } fields;
+       } upper;
 };
 
 /* Transmit Descriptor bit definitions */
-#define E1000_TXD_DTYP_D     0x00100000 /* Data Descriptor */
-#define E1000_TXD_DTYP_C     0x00000000 /* Context Descriptor */
-#define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
-#define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
-#define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
-#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
-#define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */
-#define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
-#define E1000_TXD_CMD_RPS    0x10000000 /* Report Packet Sent */
-#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
-#define E1000_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
-#define E1000_TXD_CMD_IDE    0x80000000 /* Enable Tidv register */
-#define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
-#define E1000_TXD_STAT_EC    0x00000002 /* Excess Collisions */
-#define E1000_TXD_STAT_LC    0x00000004 /* Late Collisions */
-#define E1000_TXD_STAT_TU    0x00000008 /* Transmit underrun */
-#define E1000_TXD_CMD_TCP    0x01000000 /* TCP packet */
-#define E1000_TXD_CMD_IP     0x02000000 /* IP packet */
-#define E1000_TXD_CMD_TSE    0x04000000 /* TCP Seg enable */
-#define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */
+#define E1000_TXD_DTYP_D     0x00100000        /* Data Descriptor */
+#define E1000_TXD_DTYP_C     0x00000000        /* Context Descriptor */
+#define E1000_TXD_POPTS_IXSM 0x01      /* Insert IP checksum */
+#define E1000_TXD_POPTS_TXSM 0x02      /* Insert TCP/UDP checksum */
+#define E1000_TXD_CMD_EOP    0x01000000        /* End of Packet */
+#define E1000_TXD_CMD_IFCS   0x02000000        /* Insert FCS (Ethernet CRC) */
+#define E1000_TXD_CMD_IC     0x04000000        /* Insert Checksum */
+#define E1000_TXD_CMD_RS     0x08000000        /* Report Status */
+#define E1000_TXD_CMD_RPS    0x10000000        /* Report Packet Sent */
+#define E1000_TXD_CMD_DEXT   0x20000000        /* Descriptor extension (0 = legacy) */
+#define E1000_TXD_CMD_VLE    0x40000000        /* Add VLAN tag */
+#define E1000_TXD_CMD_IDE    0x80000000        /* Enable Tidv register */
+#define E1000_TXD_STAT_DD    0x00000001        /* Descriptor Done */
+#define E1000_TXD_STAT_EC    0x00000002        /* Excess Collisions */
+#define E1000_TXD_STAT_LC    0x00000004        /* Late Collisions */
+#define E1000_TXD_STAT_TU    0x00000008        /* Transmit underrun */
+#define E1000_TXD_CMD_TCP    0x01000000        /* TCP packet */
+#define E1000_TXD_CMD_IP     0x02000000        /* IP packet */
+#define E1000_TXD_CMD_TSE    0x04000000        /* TCP Seg enable */
+#define E1000_TXD_STAT_TC    0x00000004        /* Tx Underrun */
 
 /* Offload Context Descriptor */
 struct e1000_context_desc {
-    union {
-        __le32 ip_config;
-        struct {
-            u8 ipcss;      /* IP checksum start */
-            u8 ipcso;      /* IP checksum offset */
-            __le16 ipcse;     /* IP checksum end */
-        } ip_fields;
-    } lower_setup;
-    union {
-        __le32 tcp_config;
-        struct {
-            u8 tucss;      /* TCP checksum start */
-            u8 tucso;      /* TCP checksum offset */
-            __le16 tucse;     /* TCP checksum end */
-        } tcp_fields;
-    } upper_setup;
-    __le32 cmd_and_length;    /* */
-    union {
-        __le32 data;
-        struct {
-            u8 status;     /* Descriptor status */
-            u8 hdr_len;    /* Header length */
-            __le16 mss;       /* Maximum segment size */
-        } fields;
-    } tcp_seg_setup;
+       union {
+               __le32 ip_config;
+               struct {
+                       u8 ipcss;       /* IP checksum start */
+                       u8 ipcso;       /* IP checksum offset */
+                       __le16 ipcse;   /* IP checksum end */
+               } ip_fields;
+       } lower_setup;
+       union {
+               __le32 tcp_config;
+               struct {
+                       u8 tucss;       /* TCP checksum start */
+                       u8 tucso;       /* TCP checksum offset */
+                       __le16 tucse;   /* TCP checksum end */
+               } tcp_fields;
+       } upper_setup;
+       __le32 cmd_and_length;  /* */
+       union {
+               __le32 data;
+               struct {
+                       u8 status;      /* Descriptor status */
+                       u8 hdr_len;     /* Header length */
+                       __le16 mss;     /* Maximum segment size */
+               } fields;
+       } tcp_seg_setup;
 };
 
 /* Offload data descriptor */
 struct e1000_data_desc {
-    __le64 buffer_addr;       /* Address of the descriptor's buffer address */
-    union {
-        __le32 data;
-        struct {
-            __le16 length;    /* Data buffer length */
-            u8 typ_len_ext;        /* */
-            u8 cmd;        /* */
-        } flags;
-    } lower;
-    union {
-        __le32 data;
-        struct {
-            u8 status;     /* Descriptor status */
-            u8 popts;      /* Packet Options */
-            __le16 special;   /* */
-        } fields;
-    } upper;
+       __le64 buffer_addr;     /* Address of the descriptor's buffer address */
+       union {
+               __le32 data;
+               struct {
+                       __le16 length;  /* Data buffer length */
+                       u8 typ_len_ext; /* */
+                       u8 cmd; /* */
+               } flags;
+       } lower;
+       union {
+               __le32 data;
+               struct {
+                       u8 status;      /* Descriptor status */
+                       u8 popts;       /* Packet Options */
+                       __le16 special; /* */
+               } fields;
+       } upper;
 };
 
 /* Filters */
-#define E1000_NUM_UNICAST          16   /* Unicast filter entries */
-#define E1000_MC_TBL_SIZE          128  /* Multicast Filter Table (4096 bits) */
-#define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
+#define E1000_NUM_UNICAST          16  /* Unicast filter entries */
+#define E1000_MC_TBL_SIZE          128 /* Multicast Filter Table (4096 bits) */
+#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
 
 /* Receive Address Register */
 struct e1000_rar {
-    volatile __le32 low;      /* receive address low */
-    volatile __le32 high;     /* receive address high */
+       volatile __le32 low;    /* receive address low */
+       volatile __le32 high;   /* receive address high */
 };
 
 /* Number of entries in the Multicast Table Array (MTA). */
@@ -752,8 +746,8 @@ struct e1000_rar {
 
 /* IPv4 Address Table Entry */
 struct e1000_ipv4_at_entry {
-    volatile u32 ipv4_addr;        /* IP Address (RW) */
-    volatile u32 reserved;
+       volatile u32 ipv4_addr; /* IP Address (RW) */
+       volatile u32 reserved;
 };
 
 /* Four wakeup IP addresses are supported */
@@ -763,25 +757,25 @@ struct e1000_ipv4_at_entry {
 
 /* IPv6 Address Table Entry */
 struct e1000_ipv6_at_entry {
-    volatile u8 ipv6_addr[16];
+       volatile u8 ipv6_addr[16];
 };
 
 /* Flexible Filter Length Table Entry */
 struct e1000_fflt_entry {
-    volatile u32 length;   /* Flexible Filter Length (RW) */
-    volatile u32 reserved;
+       volatile u32 length;    /* Flexible Filter Length (RW) */
+       volatile u32 reserved;
 };
 
 /* Flexible Filter Mask Table Entry */
 struct e1000_ffmt_entry {
-    volatile u32 mask;     /* Flexible Filter Mask (RW) */
-    volatile u32 reserved;
+       volatile u32 mask;      /* Flexible Filter Mask (RW) */
+       volatile u32 reserved;
 };
 
 /* Flexible Filter Value Table Entry */
 struct e1000_ffvt_entry {
-    volatile u32 value;    /* Flexible Filter Value (RW) */
-    volatile u32 reserved;
+       volatile u32 value;     /* Flexible Filter Value (RW) */
+       volatile u32 reserved;
 };
 
 /* Four Flexible Filters are supported */
@@ -808,210 +802,211 @@ struct e1000_ffvt_entry {
  * R/clr - register is read only and is cleared when read
  * A - register array
  */
-#define E1000_CTRL     0x00000  /* Device Control - RW */
-#define E1000_CTRL_DUP 0x00004  /* Device Control Duplicate (Shadow) - RW */
-#define E1000_STATUS   0x00008  /* Device Status - RO */
-#define E1000_EECD     0x00010  /* EEPROM/Flash Control - RW */
-#define E1000_EERD     0x00014  /* EEPROM Read - RW */
-#define E1000_CTRL_EXT 0x00018  /* Extended Device Control - RW */
-#define E1000_FLA      0x0001C  /* Flash Access - RW */
-#define E1000_MDIC     0x00020  /* MDI Control - RW */
-#define E1000_SCTL     0x00024  /* SerDes Control - RW */
-#define E1000_FEXTNVM  0x00028  /* Future Extended NVM register */
-#define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */
-#define E1000_FCAH     0x0002C  /* Flow Control Address High -RW */
-#define E1000_FCT      0x00030  /* Flow Control Type - RW */
-#define E1000_VET      0x00038  /* VLAN Ether Type - RW */
-#define E1000_ICR      0x000C0  /* Interrupt Cause Read - R/clr */
-#define E1000_ITR      0x000C4  /* Interrupt Throttling Rate - RW */
-#define E1000_ICS      0x000C8  /* Interrupt Cause Set - WO */
-#define E1000_IMS      0x000D0  /* Interrupt Mask Set - RW */
-#define E1000_IMC      0x000D8  /* Interrupt Mask Clear - WO */
-#define E1000_IAM      0x000E0  /* Interrupt Acknowledge Auto Mask */
-#define E1000_RCTL     0x00100  /* RX Control - RW */
-#define E1000_RDTR1    0x02820  /* RX Delay Timer (1) - RW */
-#define E1000_RDBAL1   0x02900  /* RX Descriptor Base Address Low (1) - RW */
-#define E1000_RDBAH1   0x02904  /* RX Descriptor Base Address High (1) - RW */
-#define E1000_RDLEN1   0x02908  /* RX Descriptor Length (1) - RW */
-#define E1000_RDH1     0x02910  /* RX Descriptor Head (1) - RW */
-#define E1000_RDT1     0x02918  /* RX Descriptor Tail (1) - RW */
-#define E1000_FCTTV    0x00170  /* Flow Control Transmit Timer Value - RW */
-#define E1000_TXCW     0x00178  /* TX Configuration Word - RW */
-#define E1000_RXCW     0x00180  /* RX Configuration Word - RO */
-#define E1000_TCTL     0x00400  /* TX Control - RW */
-#define E1000_TCTL_EXT 0x00404  /* Extended TX Control - RW */
-#define E1000_TIPG     0x00410  /* TX Inter-packet gap -RW */
-#define E1000_TBT      0x00448  /* TX Burst Timer - RW */
-#define E1000_AIT      0x00458  /* Adaptive Interframe Spacing Throttle - RW */
-#define E1000_LEDCTL   0x00E00  /* LED Control - RW */
-#define E1000_EXTCNF_CTRL  0x00F00  /* Extended Configuration Control */
-#define E1000_EXTCNF_SIZE  0x00F08  /* Extended Configuration Size */
-#define E1000_PHY_CTRL     0x00F10  /* PHY Control Register in CSR */
+#define E1000_CTRL     0x00000 /* Device Control - RW */
+#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
+#define E1000_STATUS   0x00008 /* Device Status - RO */
+#define E1000_EECD     0x00010 /* EEPROM/Flash Control - RW */
+#define E1000_EERD     0x00014 /* EEPROM Read - RW */
+#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
+#define E1000_FLA      0x0001C /* Flash Access - RW */
+#define E1000_MDIC     0x00020 /* MDI Control - RW */
+#define E1000_SCTL     0x00024 /* SerDes Control - RW */
+#define E1000_FEXTNVM  0x00028 /* Future Extended NVM register */
+#define E1000_FCAL     0x00028 /* Flow Control Address Low - RW */
+#define E1000_FCAH     0x0002C /* Flow Control Address High -RW */
+#define E1000_FCT      0x00030 /* Flow Control Type - RW */
+#define E1000_VET      0x00038 /* VLAN Ether Type - RW */
+#define E1000_ICR      0x000C0 /* Interrupt Cause Read - R/clr */
+#define E1000_ITR      0x000C4 /* Interrupt Throttling Rate - RW */
+#define E1000_ICS      0x000C8 /* Interrupt Cause Set - WO */
+#define E1000_IMS      0x000D0 /* Interrupt Mask Set - RW */
+#define E1000_IMC      0x000D8 /* Interrupt Mask Clear - WO */
+#define E1000_IAM      0x000E0 /* Interrupt Acknowledge Auto Mask */
+#define E1000_RCTL     0x00100 /* RX Control - RW */
+#define E1000_RDTR1    0x02820 /* RX Delay Timer (1) - RW */
+#define E1000_RDBAL1   0x02900 /* RX Descriptor Base Address Low (1) - RW */
+#define E1000_RDBAH1   0x02904 /* RX Descriptor Base Address High (1) - RW */
+#define E1000_RDLEN1   0x02908 /* RX Descriptor Length (1) - RW */
+#define E1000_RDH1     0x02910 /* RX Descriptor Head (1) - RW */
+#define E1000_RDT1     0x02918 /* RX Descriptor Tail (1) - RW */
+#define E1000_FCTTV    0x00170 /* Flow Control Transmit Timer Value - RW */
+#define E1000_TXCW     0x00178 /* TX Configuration Word - RW */
+#define E1000_RXCW     0x00180 /* RX Configuration Word - RO */
+#define E1000_TCTL     0x00400 /* TX Control - RW */
+#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
+#define E1000_TIPG     0x00410 /* TX Inter-packet gap -RW */
+#define E1000_TBT      0x00448 /* TX Burst Timer - RW */
+#define E1000_AIT      0x00458 /* Adaptive Interframe Spacing Throttle - RW */
+#define E1000_LEDCTL   0x00E00 /* LED Control - RW */
+#define E1000_EXTCNF_CTRL  0x00F00     /* Extended Configuration Control */
+#define E1000_EXTCNF_SIZE  0x00F08     /* Extended Configuration Size */
+#define E1000_PHY_CTRL     0x00F10     /* PHY Control Register in CSR */
 #define FEXTNVM_SW_CONFIG  0x0001
-#define E1000_PBA      0x01000  /* Packet Buffer Allocation - RW */
-#define E1000_PBS      0x01008  /* Packet Buffer Size */
-#define E1000_EEMNGCTL 0x01010  /* MNG EEprom Control */
+#define E1000_PBA      0x01000 /* Packet Buffer Allocation - RW */
+#define E1000_PBS      0x01008 /* Packet Buffer Size */
+#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
 #define E1000_FLASH_UPDATES 1000
-#define E1000_EEARBC   0x01024  /* EEPROM Auto Read Bus Control */
-#define E1000_FLASHT   0x01028  /* FLASH Timer Register */
-#define E1000_EEWR     0x0102C  /* EEPROM Write Register - RW */
-#define E1000_FLSWCTL  0x01030  /* FLASH control register */
-#define E1000_FLSWDATA 0x01034  /* FLASH data register */
-#define E1000_FLSWCNT  0x01038  /* FLASH Access Counter */
-#define E1000_FLOP     0x0103C  /* FLASH Opcode Register */
-#define E1000_ERT      0x02008  /* Early Rx Threshold - RW */
-#define E1000_FCRTL    0x02160  /* Flow Control Receive Threshold Low - RW */
-#define E1000_FCRTH    0x02168  /* Flow Control Receive Threshold High - RW */
-#define E1000_PSRCTL   0x02170  /* Packet Split Receive Control - RW */
-#define E1000_RDBAL    0x02800  /* RX Descriptor Base Address Low - RW */
-#define E1000_RDBAH    0x02804  /* RX Descriptor Base Address High - RW */
-#define E1000_RDLEN    0x02808  /* RX Descriptor Length - RW */
-#define E1000_RDH      0x02810  /* RX Descriptor Head - RW */
-#define E1000_RDT      0x02818  /* RX Descriptor Tail - RW */
-#define E1000_RDTR     0x02820  /* RX Delay Timer - RW */
-#define E1000_RDBAL0   E1000_RDBAL /* RX Desc Base Address Low (0) - RW */
-#define E1000_RDBAH0   E1000_RDBAH /* RX Desc Base Address High (0) - RW */
-#define E1000_RDLEN0   E1000_RDLEN /* RX Desc Length (0) - RW */
-#define E1000_RDH0     E1000_RDH   /* RX Desc Head (0) - RW */
-#define E1000_RDT0     E1000_RDT   /* RX Desc Tail (0) - RW */
-#define E1000_RDTR0    E1000_RDTR  /* RX Delay Timer (0) - RW */
-#define E1000_RXDCTL   0x02828  /* RX Descriptor Control queue 0 - RW */
-#define E1000_RXDCTL1  0x02928  /* RX Descriptor Control queue 1 - RW */
-#define E1000_RADV     0x0282C  /* RX Interrupt Absolute Delay Timer - RW */
-#define E1000_RSRPD    0x02C00  /* RX Small Packet Detect - RW */
-#define E1000_RAID     0x02C08  /* Receive Ack Interrupt Delay - RW */
-#define E1000_TXDMAC   0x03000  /* TX DMA Control - RW */
-#define E1000_KABGTXD  0x03004  /* AFE Band Gap Transmit Ref Data */
-#define E1000_TDFH     0x03410  /* TX Data FIFO Head - RW */
-#define E1000_TDFT     0x03418  /* TX Data FIFO Tail - RW */
-#define E1000_TDFHS    0x03420  /* TX Data FIFO Head Saved - RW */
-#define E1000_TDFTS    0x03428  /* TX Data FIFO Tail Saved - RW */
-#define E1000_TDFPC    0x03430  /* TX Data FIFO Packet Count - RW */
-#define E1000_TDBAL    0x03800  /* TX Descriptor Base Address Low - RW */
-#define E1000_TDBAH    0x03804  /* TX Descriptor Base Address High - RW */
-#define E1000_TDLEN    0x03808  /* TX Descriptor Length - RW */
-#define E1000_TDH      0x03810  /* TX Descriptor Head - RW */
-#define E1000_TDT      0x03818  /* TX Descripotr Tail - RW */
-#define E1000_TIDV     0x03820  /* TX Interrupt Delay Value - RW */
-#define E1000_TXDCTL   0x03828  /* TX Descriptor Control - RW */
-#define E1000_TADV     0x0382C  /* TX Interrupt Absolute Delay Val - RW */
-#define E1000_TSPMT    0x03830  /* TCP Segmentation PAD & Min Threshold - RW */
-#define E1000_TARC0    0x03840  /* TX Arbitration Count (0) */
-#define E1000_TDBAL1   0x03900  /* TX Desc Base Address Low (1) - RW */
-#define E1000_TDBAH1   0x03904  /* TX Desc Base Address High (1) - RW */
-#define E1000_TDLEN1   0x03908  /* TX Desc Length (1) - RW */
-#define E1000_TDH1     0x03910  /* TX Desc Head (1) - RW */
-#define E1000_TDT1     0x03918  /* TX Desc Tail (1) - RW */
-#define E1000_TXDCTL1  0x03928  /* TX Descriptor Control (1) - RW */
-#define E1000_TARC1    0x03940  /* TX Arbitration Count (1) */
-#define E1000_CRCERRS  0x04000  /* CRC Error Count - R/clr */
-#define E1000_ALGNERRC 0x04004  /* Alignment Error Count - R/clr */
-#define E1000_SYMERRS  0x04008  /* Symbol Error Count - R/clr */
-#define E1000_RXERRC   0x0400C  /* Receive Error Count - R/clr */
-#define E1000_MPC      0x04010  /* Missed Packet Count - R/clr */
-#define E1000_SCC      0x04014  /* Single Collision Count - R/clr */
-#define E1000_ECOL     0x04018  /* Excessive Collision Count - R/clr */
-#define E1000_MCC      0x0401C  /* Multiple Collision Count - R/clr */
-#define E1000_LATECOL  0x04020  /* Late Collision Count - R/clr */
-#define E1000_COLC     0x04028  /* Collision Count - R/clr */
-#define E1000_DC       0x04030  /* Defer Count - R/clr */
-#define E1000_TNCRS    0x04034  /* TX-No CRS - R/clr */
-#define E1000_SEC      0x04038  /* Sequence Error Count - R/clr */
-#define E1000_CEXTERR  0x0403C  /* Carrier Extension Error Count - R/clr */
-#define E1000_RLEC     0x04040  /* Receive Length Error Count - R/clr */
-#define E1000_XONRXC   0x04048  /* XON RX Count - R/clr */
-#define E1000_XONTXC   0x0404C  /* XON TX Count - R/clr */
-#define E1000_XOFFRXC  0x04050  /* XOFF RX Count - R/clr */
-#define E1000_XOFFTXC  0x04054  /* XOFF TX Count - R/clr */
-#define E1000_FCRUC    0x04058  /* Flow Control RX Unsupported Count- R/clr */
-#define E1000_PRC64    0x0405C  /* Packets RX (64 bytes) - R/clr */
-#define E1000_PRC127   0x04060  /* Packets RX (65-127 bytes) - R/clr */
-#define E1000_PRC255   0x04064  /* Packets RX (128-255 bytes) - R/clr */
-#define E1000_PRC511   0x04068  /* Packets RX (255-511 bytes) - R/clr */
-#define E1000_PRC1023  0x0406C  /* Packets RX (512-1023 bytes) - R/clr */
-#define E1000_PRC1522  0x04070  /* Packets RX (1024-1522 bytes) - R/clr */
-#define E1000_GPRC     0x04074  /* Good Packets RX Count - R/clr */
-#define E1000_BPRC     0x04078  /* Broadcast Packets RX Count - R/clr */
-#define E1000_MPRC     0x0407C  /* Multicast Packets RX Count - R/clr */
-#define E1000_GPTC     0x04080  /* Good Packets TX Count - R/clr */
-#define E1000_GORCL    0x04088  /* Good Octets RX Count Low - R/clr */
-#define E1000_GORCH    0x0408C  /* Good Octets RX Count High - R/clr */
-#define E1000_GOTCL    0x04090  /* Good Octets TX Count Low - R/clr */
-#define E1000_GOTCH    0x04094  /* Good Octets TX Count High - R/clr */
-#define E1000_RNBC     0x040A0  /* RX No Buffers Count - R/clr */
-#define E1000_RUC      0x040A4  /* RX Undersize Count - R/clr */
-#define E1000_RFC      0x040A8  /* RX Fragment Count - R/clr */
-#define E1000_ROC      0x040AC  /* RX Oversize Count - R/clr */
-#define E1000_RJC      0x040B0  /* RX Jabber Count - R/clr */
-#define E1000_MGTPRC   0x040B4  /* Management Packets RX Count - R/clr */
-#define E1000_MGTPDC   0x040B8  /* Management Packets Dropped Count - R/clr */
-#define E1000_MGTPTC   0x040BC  /* Management Packets TX Count - R/clr */
-#define E1000_TORL     0x040C0  /* Total Octets RX Low - R/clr */
-#define E1000_TORH     0x040C4  /* Total Octets RX High - R/clr */
-#define E1000_TOTL     0x040C8  /* Total Octets TX Low - R/clr */
-#define E1000_TOTH     0x040CC  /* Total Octets TX High - R/clr */
-#define E1000_TPR      0x040D0  /* Total Packets RX - R/clr */
-#define E1000_TPT      0x040D4  /* Total Packets TX - R/clr */
-#define E1000_PTC64    0x040D8  /* Packets TX (64 bytes) - R/clr */
-#define E1000_PTC127   0x040DC  /* Packets TX (65-127 bytes) - R/clr */
-#define E1000_PTC255   0x040E0  /* Packets TX (128-255 bytes) - R/clr */
-#define E1000_PTC511   0x040E4  /* Packets TX (256-511 bytes) - R/clr */
-#define E1000_PTC1023  0x040E8  /* Packets TX (512-1023 bytes) - R/clr */
-#define E1000_PTC1522  0x040EC  /* Packets TX (1024-1522 Bytes) - R/clr */
-#define E1000_MPTC     0x040F0  /* Multicast Packets TX Count - R/clr */
-#define E1000_BPTC     0x040F4  /* Broadcast Packets TX Count - R/clr */
-#define E1000_TSCTC    0x040F8  /* TCP Segmentation Context TX - R/clr */
-#define E1000_TSCTFC   0x040FC  /* TCP Segmentation Context TX Fail - R/clr */
-#define E1000_IAC      0x04100  /* Interrupt Assertion Count */
-#define E1000_ICRXPTC  0x04104  /* Interrupt Cause Rx Packet Timer Expire Count */
-#define E1000_ICRXATC  0x04108  /* Interrupt Cause Rx Absolute Timer Expire Count */
-#define E1000_ICTXPTC  0x0410C  /* Interrupt Cause Tx Packet Timer Expire Count */
-#define E1000_ICTXATC  0x04110  /* Interrupt Cause Tx Absolute Timer Expire Count */
-#define E1000_ICTXQEC  0x04118  /* Interrupt Cause Tx Queue Empty Count */
-#define E1000_ICTXQMTC 0x0411C  /* Interrupt Cause Tx Queue Minimum Threshold Count */
-#define E1000_ICRXDMTC 0x04120  /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
-#define E1000_ICRXOC   0x04124  /* Interrupt Cause Receiver Overrun Count */
-#define E1000_RXCSUM   0x05000  /* RX Checksum Control - RW */
-#define E1000_RFCTL    0x05008  /* Receive Filter Control*/
-#define E1000_MTA      0x05200  /* Multicast Table Array - RW Array */
-#define E1000_RA       0x05400  /* Receive Address - RW Array */
-#define E1000_VFTA     0x05600  /* VLAN Filter Table Array - RW Array */
-#define E1000_WUC      0x05800  /* Wakeup Control - RW */
-#define E1000_WUFC     0x05808  /* Wakeup Filter Control - RW */
-#define E1000_WUS      0x05810  /* Wakeup Status - RO */
-#define E1000_MANC     0x05820  /* Management Control - RW */
-#define E1000_IPAV     0x05838  /* IP Address Valid - RW */
-#define E1000_IP4AT    0x05840  /* IPv4 Address Table - RW Array */
-#define E1000_IP6AT    0x05880  /* IPv6 Address Table - RW Array */
-#define E1000_WUPL     0x05900  /* Wakeup Packet Length - RW */
-#define E1000_WUPM     0x05A00  /* Wakeup Packet Memory - RO A */
-#define E1000_FFLT     0x05F00  /* Flexible Filter Length Table - RW Array */
-#define E1000_HOST_IF  0x08800  /* Host Interface */
-#define E1000_FFMT     0x09000  /* Flexible Filter Mask Table - RW Array */
-#define E1000_FFVT     0x09800  /* Flexible Filter Value Table - RW Array */
-
-#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
-#define E1000_MDPHYA     0x0003C  /* PHY address - RW */
-#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
-
-#define E1000_GCR       0x05B00 /* PCI-Ex Control */
-#define E1000_GSCL_1    0x05B10 /* PCI-Ex Statistic Control #1 */
-#define E1000_GSCL_2    0x05B14 /* PCI-Ex Statistic Control #2 */
-#define E1000_GSCL_3    0x05B18 /* PCI-Ex Statistic Control #3 */
-#define E1000_GSCL_4    0x05B1C /* PCI-Ex Statistic Control #4 */
-#define E1000_FACTPS    0x05B30 /* Function Active and Power State to MNG */
-#define E1000_SWSM      0x05B50 /* SW Semaphore */
-#define E1000_FWSM      0x05B54 /* FW Semaphore */
-#define E1000_FFLT_DBG  0x05F04 /* Debug Register */
-#define E1000_HICR      0x08F00 /* Host Inteface Control */
+#define E1000_EEARBC   0x01024 /* EEPROM Auto Read Bus Control */
+#define E1000_FLASHT   0x01028 /* FLASH Timer Register */
+#define E1000_EEWR     0x0102C /* EEPROM Write Register - RW */
+#define E1000_FLSWCTL  0x01030 /* FLASH control register */
+#define E1000_FLSWDATA 0x01034 /* FLASH data register */
+#define E1000_FLSWCNT  0x01038 /* FLASH Access Counter */
+#define E1000_FLOP     0x0103C /* FLASH Opcode Register */
+#define E1000_ERT      0x02008 /* Early Rx Threshold - RW */
+#define E1000_FCRTL    0x02160 /* Flow Control Receive Threshold Low - RW */
+#define E1000_FCRTH    0x02168 /* Flow Control Receive Threshold High - RW */
+#define E1000_PSRCTL   0x02170 /* Packet Split Receive Control - RW */
+#define E1000_RDBAL    0x02800 /* RX Descriptor Base Address Low - RW */
+#define E1000_RDBAH    0x02804 /* RX Descriptor Base Address High - RW */
+#define E1000_RDLEN    0x02808 /* RX Descriptor Length - RW */
+#define E1000_RDH      0x02810 /* RX Descriptor Head - RW */
+#define E1000_RDT      0x02818 /* RX Descriptor Tail - RW */
+#define E1000_RDTR     0x02820 /* RX Delay Timer - RW */
+#define E1000_RDBAL0   E1000_RDBAL     /* RX Desc Base Address Low (0) - RW */
+#define E1000_RDBAH0   E1000_RDBAH     /* RX Desc Base Address High (0) - RW */
+#define E1000_RDLEN0   E1000_RDLEN     /* RX Desc Length (0) - RW */
+#define E1000_RDH0     E1000_RDH       /* RX Desc Head (0) - RW */
+#define E1000_RDT0     E1000_RDT       /* RX Desc Tail (0) - RW */
+#define E1000_RDTR0    E1000_RDTR      /* RX Delay Timer (0) - RW */
+#define E1000_RXDCTL   0x02828 /* RX Descriptor Control queue 0 - RW */
+#define E1000_RXDCTL1  0x02928 /* RX Descriptor Control queue 1 - RW */
+#define E1000_RADV     0x0282C /* RX Interrupt Absolute Delay Timer - RW */
+#define E1000_RSRPD    0x02C00 /* RX Small Packet Detect - RW */
+#define E1000_RAID     0x02C08 /* Receive Ack Interrupt Delay - RW */
+#define E1000_TXDMAC   0x03000 /* TX DMA Control - RW */
+#define E1000_KABGTXD  0x03004 /* AFE Band Gap Transmit Ref Data */
+#define E1000_TDFH     0x03410 /* TX Data FIFO Head - RW */
+#define E1000_TDFT     0x03418 /* TX Data FIFO Tail - RW */
+#define E1000_TDFHS    0x03420 /* TX Data FIFO Head Saved - RW */
+#define E1000_TDFTS    0x03428 /* TX Data FIFO Tail Saved - RW */
+#define E1000_TDFPC    0x03430 /* TX Data FIFO Packet Count - RW */
+#define E1000_TDBAL    0x03800 /* TX Descriptor Base Address Low - RW */
+#define E1000_TDBAH    0x03804 /* TX Descriptor Base Address High - RW */
+#define E1000_TDLEN    0x03808 /* TX Descriptor Length - RW */
+#define E1000_TDH      0x03810 /* TX Descriptor Head - RW */
+#define E1000_TDT      0x03818 /* TX Descripotr Tail - RW */
+#define E1000_TIDV     0x03820 /* TX Interrupt Delay Value - RW */
+#define E1000_TXDCTL   0x03828 /* TX Descriptor Control - RW */
+#define E1000_TADV     0x0382C /* TX Interrupt Absolute Delay Val - RW */
+#define E1000_TSPMT    0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
+#define E1000_TARC0    0x03840 /* TX Arbitration Count (0) */
+#define E1000_TDBAL1   0x03900 /* TX Desc Base Address Low (1) - RW */
+#define E1000_TDBAH1   0x03904 /* TX Desc Base Address High (1) - RW */
+#define E1000_TDLEN1   0x03908 /* TX Desc Length (1) - RW */
+#define E1000_TDH1     0x03910 /* TX Desc Head (1) - RW */
+#define E1000_TDT1     0x03918 /* TX Desc Tail (1) - RW */
+#define E1000_TXDCTL1  0x03928 /* TX Descriptor Control (1) - RW */
+#define E1000_TARC1    0x03940 /* TX Arbitration Count (1) */
+#define E1000_CRCERRS  0x04000 /* CRC Error Count - R/clr */
+#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
+#define E1000_SYMERRS  0x04008 /* Symbol Error Count - R/clr */
+#define E1000_RXERRC   0x0400C /* Receive Error Count - R/clr */
+#define E1000_MPC      0x04010 /* Missed Packet Count - R/clr */
+#define E1000_SCC      0x04014 /* Single Collision Count - R/clr */
+#define E1000_ECOL     0x04018 /* Excessive Collision Count - R/clr */
+#define E1000_MCC      0x0401C /* Multiple Collision Count - R/clr */
+#define E1000_LATECOL  0x04020 /* Late Collision Count - R/clr */
+#define E1000_COLC     0x04028 /* Collision Count - R/clr */
+#define E1000_DC       0x04030 /* Defer Count - R/clr */
+#define E1000_TNCRS    0x04034 /* TX-No CRS - R/clr */
+#define E1000_SEC      0x04038 /* Sequence Error Count - R/clr */
+#define E1000_CEXTERR  0x0403C /* Carrier Extension Error Count - R/clr */
+#define E1000_RLEC     0x04040 /* Receive Length Error Count - R/clr */
+#define E1000_XONRXC   0x04048 /* XON RX Count - R/clr */
+#define E1000_XONTXC   0x0404C /* XON TX Count - R/clr */
+#define E1000_XOFFRXC  0x04050 /* XOFF RX Count - R/clr */
+#define E1000_XOFFTXC  0x04054 /* XOFF TX Count - R/clr */
+#define E1000_FCRUC    0x04058 /* Flow Control RX Unsupported Count- R/clr */
+#define E1000_PRC64    0x0405C /* Packets RX (64 bytes) - R/clr */
+#define E1000_PRC127   0x04060 /* Packets RX (65-127 bytes) - R/clr */
+#define E1000_PRC255   0x04064 /* Packets RX (128-255 bytes) - R/clr */
+#define E1000_PRC511   0x04068 /* Packets RX (255-511 bytes) - R/clr */
+#define E1000_PRC1023  0x0406C /* Packets RX (512-1023 bytes) - R/clr */
+#define E1000_PRC1522  0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
+#define E1000_GPRC     0x04074 /* Good Packets RX Count - R/clr */
+#define E1000_BPRC     0x04078 /* Broadcast Packets RX Count - R/clr */
+#define E1000_MPRC     0x0407C /* Multicast Packets RX Count - R/clr */
+#define E1000_GPTC     0x04080 /* Good Packets TX Count - R/clr */
+#define E1000_GORCL    0x04088 /* Good Octets RX Count Low - R/clr */
+#define E1000_GORCH    0x0408C /* Good Octets RX Count High - R/clr */
+#define E1000_GOTCL    0x04090 /* Good Octets TX Count Low - R/clr */
+#define E1000_GOTCH    0x04094 /* Good Octets TX Count High - R/clr */
+#define E1000_RNBC     0x040A0 /* RX No Buffers Count - R/clr */
+#define E1000_RUC      0x040A4 /* RX Undersize Count - R/clr */
+#define E1000_RFC      0x040A8 /* RX Fragment Count - R/clr */
+#define E1000_ROC      0x040AC /* RX Oversize Count - R/clr */
+#define E1000_RJC      0x040B0 /* RX Jabber Count - R/clr */
+#define E1000_MGTPRC   0x040B4 /* Management Packets RX Count - R/clr */
+#define E1000_MGTPDC   0x040B8 /* Management Packets Dropped Count - R/clr */
+#define E1000_MGTPTC   0x040BC /* Management Packets TX Count - R/clr */
+#define E1000_TORL     0x040C0 /* Total Octets RX Low - R/clr */
+#define E1000_TORH     0x040C4 /* Total Octets RX High - R/clr */
+#define E1000_TOTL     0x040C8 /* Total Octets TX Low - R/clr */
+#define E1000_TOTH     0x040CC /* Total Octets TX High - R/clr */
+#define E1000_TPR      0x040D0 /* Total Packets RX - R/clr */
+#define E1000_TPT      0x040D4 /* Total Packets TX - R/clr */
+#define E1000_PTC64    0x040D8 /* Packets TX (64 bytes) - R/clr */
+#define E1000_PTC127   0x040DC /* Packets TX (65-127 bytes) - R/clr */
+#define E1000_PTC255   0x040E0 /* Packets TX (128-255 bytes) - R/clr */
+#define E1000_PTC511   0x040E4 /* Packets TX (256-511 bytes) - R/clr */
+#define E1000_PTC1023  0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
+#define E1000_PTC1522  0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
+#define E1000_MPTC     0x040F0 /* Multicast Packets TX Count - R/clr */
+#define E1000_BPTC     0x040F4 /* Broadcast Packets TX Count - R/clr */
+#define E1000_TSCTC    0x040F8 /* TCP Segmentation Context TX - R/clr */
+#define E1000_TSCTFC   0x040FC /* TCP Segmentation Context TX Fail - R/clr */
+#define E1000_IAC      0x04100 /* Interrupt Assertion Count */
+#define E1000_ICRXPTC  0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */
+#define E1000_ICRXATC  0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */
+#define E1000_ICTXPTC  0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */
+#define E1000_ICTXATC  0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */
+#define E1000_ICTXQEC  0x04118 /* Interrupt Cause Tx Queue Empty Count */
+#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */
+#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
+#define E1000_ICRXOC   0x04124 /* Interrupt Cause Receiver Overrun Count */
+#define E1000_RXCSUM   0x05000 /* RX Checksum Control - RW */
+#define E1000_RFCTL    0x05008 /* Receive Filter Control */
+#define E1000_MTA      0x05200 /* Multicast Table Array - RW Array */
+#define E1000_RA       0x05400 /* Receive Address - RW Array */
+#define E1000_VFTA     0x05600 /* VLAN Filter Table Array - RW Array */
+#define E1000_WUC      0x05800 /* Wakeup Control - RW */
+#define E1000_WUFC     0x05808 /* Wakeup Filter Control - RW */
+#define E1000_WUS      0x05810 /* Wakeup Status - RO */
+#define E1000_MANC     0x05820 /* Management Control - RW */
+#define E1000_IPAV     0x05838 /* IP Address Valid - RW */
+#define E1000_IP4AT    0x05840 /* IPv4 Address Table - RW Array */
+#define E1000_IP6AT    0x05880 /* IPv6 Address Table - RW Array */
+#define E1000_WUPL     0x05900 /* Wakeup Packet Length - RW */
+#define E1000_WUPM     0x05A00 /* Wakeup Packet Memory - RO A */
+#define E1000_FFLT     0x05F00 /* Flexible Filter Length Table - RW Array */
+#define E1000_HOST_IF  0x08800 /* Host Interface */
+#define E1000_FFMT     0x09000 /* Flexible Filter Mask Table - RW Array */
+#define E1000_FFVT     0x09800 /* Flexible Filter Value Table - RW Array */
+
+#define E1000_KUMCTRLSTA 0x00034       /* MAC-PHY interface - RW */
+#define E1000_MDPHYA     0x0003C       /* PHY address - RW */
+#define E1000_MANC2H     0x05860       /* Managment Control To Host - RW */
+#define E1000_SW_FW_SYNC 0x05B5C       /* Software-Firmware Synchronization - RW */
+
+#define E1000_GCR       0x05B00        /* PCI-Ex Control */
+#define E1000_GSCL_1    0x05B10        /* PCI-Ex Statistic Control #1 */
+#define E1000_GSCL_2    0x05B14        /* PCI-Ex Statistic Control #2 */
+#define E1000_GSCL_3    0x05B18        /* PCI-Ex Statistic Control #3 */
+#define E1000_GSCL_4    0x05B1C        /* PCI-Ex Statistic Control #4 */
+#define E1000_FACTPS    0x05B30        /* Function Active and Power State to MNG */
+#define E1000_SWSM      0x05B50        /* SW Semaphore */
+#define E1000_FWSM      0x05B54        /* FW Semaphore */
+#define E1000_FFLT_DBG  0x05F04        /* Debug Register */
+#define E1000_HICR      0x08F00        /* Host Interface Control */
 
 /* RSS registers */
-#define E1000_CPUVEC    0x02C10 /* CPU Vector Register - RW */
-#define E1000_MRQC      0x05818 /* Multiple Receive Control - RW */
-#define E1000_RETA      0x05C00 /* Redirection Table - RW Array */
-#define E1000_RSSRK     0x05C80 /* RSS Random Key - RW Array */
-#define E1000_RSSIM     0x05864 /* RSS Interrupt Mask */
-#define E1000_RSSIR     0x05868 /* RSS Interrupt Request */
+#define E1000_CPUVEC    0x02C10        /* CPU Vector Register - RW */
+#define E1000_MRQC      0x05818        /* Multiple Receive Control - RW */
+#define E1000_RETA      0x05C00        /* Redirection Table - RW Array */
+#define E1000_RSSRK     0x05C80        /* RSS Random Key - RW Array */
+#define E1000_RSSIM     0x05864        /* RSS Interrupt Mask */
+#define E1000_RSSIR     0x05868        /* RSS Interrupt Request */
 /* Register Set (82542)
  *
  * Some of the 82542 registers are located at different offsets than they are
@@ -1051,19 +1046,19 @@ struct e1000_ffvt_entry {
 #define E1000_82542_RDLEN0   E1000_82542_RDLEN
 #define E1000_82542_RDH0     E1000_82542_RDH
 #define E1000_82542_RDT0     E1000_82542_RDT
-#define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication
-                                                       * RX Control - RW */
+#define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8))  /* Split and Replication
+                                                        * RX Control - RW */
 #define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8))
-#define E1000_82542_RDBAH3   0x02B04 /* RX Desc Base High Queue 3 - RW */
-#define E1000_82542_RDBAL3   0x02B00 /* RX Desc Low Queue 3 - RW */
-#define E1000_82542_RDLEN3   0x02B08 /* RX Desc Length Queue 3 - RW */
-#define E1000_82542_RDH3     0x02B10 /* RX Desc Head Queue 3 - RW */
-#define E1000_82542_RDT3     0x02B18 /* RX Desc Tail Queue 3 - RW */
-#define E1000_82542_RDBAL2   0x02A00 /* RX Desc Base Low Queue 2 - RW */
-#define E1000_82542_RDBAH2   0x02A04 /* RX Desc Base High Queue 2 - RW */
-#define E1000_82542_RDLEN2   0x02A08 /* RX Desc Length Queue 2 - RW */
-#define E1000_82542_RDH2     0x02A10 /* RX Desc Head Queue 2 - RW */
-#define E1000_82542_RDT2     0x02A18 /* RX Desc Tail Queue 2 - RW */
+#define E1000_82542_RDBAH3   0x02B04   /* RX Desc Base High Queue 3 - RW */
+#define E1000_82542_RDBAL3   0x02B00   /* RX Desc Low Queue 3 - RW */
+#define E1000_82542_RDLEN3   0x02B08   /* RX Desc Length Queue 3 - RW */
+#define E1000_82542_RDH3     0x02B10   /* RX Desc Head Queue 3 - RW */
+#define E1000_82542_RDT3     0x02B18   /* RX Desc Tail Queue 3 - RW */
+#define E1000_82542_RDBAL2   0x02A00   /* RX Desc Base Low Queue 2 - RW */
+#define E1000_82542_RDBAH2   0x02A04   /* RX Desc Base High Queue 2 - RW */
+#define E1000_82542_RDLEN2   0x02A08   /* RX Desc Length Queue 2 - RW */
+#define E1000_82542_RDH2     0x02A10   /* RX Desc Head Queue 2 - RW */
+#define E1000_82542_RDT2     0x02A18   /* RX Desc Tail Queue 2 - RW */
 #define E1000_82542_RDTR1    0x00130
 #define E1000_82542_RDBAL1   0x00138
 #define E1000_82542_RDBAH1   0x0013C
@@ -1233,279 +1228,278 @@ struct e1000_ffvt_entry {
 
 /* Statistics counters collected by the MAC */
 struct e1000_hw_stats {
-       u64             crcerrs;
-       u64             algnerrc;
-       u64             symerrs;
-       u64             rxerrc;
-       u64             txerrc;
-       u64             mpc;
-       u64             scc;
-       u64             ecol;
-       u64             mcc;
-       u64             latecol;
-       u64             colc;
-       u64             dc;
-       u64             tncrs;
-       u64             sec;
-       u64             cexterr;
-       u64             rlec;
-       u64             xonrxc;
-       u64             xontxc;
-       u64             xoffrxc;
-       u64             xofftxc;
-       u64             fcruc;
-       u64             prc64;
-       u64             prc127;
-       u64             prc255;
-       u64             prc511;
-       u64             prc1023;
-       u64             prc1522;
-       u64             gprc;
-       u64             bprc;
-       u64             mprc;
-       u64             gptc;
-       u64             gorcl;
-       u64             gorch;
-       u64             gotcl;
-       u64             gotch;
-       u64             rnbc;
-       u64             ruc;
-       u64             rfc;
-       u64             roc;
-       u64             rlerrc;
-       u64             rjc;
-       u64             mgprc;
-       u64             mgpdc;
-       u64             mgptc;
-       u64             torl;
-       u64             torh;
-       u64             totl;
-       u64             toth;
-       u64             tpr;
-       u64             tpt;
-       u64             ptc64;
-       u64             ptc127;
-       u64             ptc255;
-       u64             ptc511;
-       u64             ptc1023;
-       u64             ptc1522;
-       u64             mptc;
-       u64             bptc;
-       u64             tsctc;
-       u64             tsctfc;
-       u64             iac;
-       u64             icrxptc;
-       u64             icrxatc;
-       u64             ictxptc;
-       u64             ictxatc;
-       u64             ictxqec;
-       u64             ictxqmtc;
-       u64             icrxdmtc;
-       u64             icrxoc;
+       u64 crcerrs;
+       u64 algnerrc;
+       u64 symerrs;
+       u64 rxerrc;
+       u64 txerrc;
+       u64 mpc;
+       u64 scc;
+       u64 ecol;
+       u64 mcc;
+       u64 latecol;
+       u64 colc;
+       u64 dc;
+       u64 tncrs;
+       u64 sec;
+       u64 cexterr;
+       u64 rlec;
+       u64 xonrxc;
+       u64 xontxc;
+       u64 xoffrxc;
+       u64 xofftxc;
+       u64 fcruc;
+       u64 prc64;
+       u64 prc127;
+       u64 prc255;
+       u64 prc511;
+       u64 prc1023;
+       u64 prc1522;
+       u64 gprc;
+       u64 bprc;
+       u64 mprc;
+       u64 gptc;
+       u64 gorcl;
+       u64 gorch;
+       u64 gotcl;
+       u64 gotch;
+       u64 rnbc;
+       u64 ruc;
+       u64 rfc;
+       u64 roc;
+       u64 rlerrc;
+       u64 rjc;
+       u64 mgprc;
+       u64 mgpdc;
+       u64 mgptc;
+       u64 torl;
+       u64 torh;
+       u64 totl;
+       u64 toth;
+       u64 tpr;
+       u64 tpt;
+       u64 ptc64;
+       u64 ptc127;
+       u64 ptc255;
+       u64 ptc511;
+       u64 ptc1023;
+       u64 ptc1522;
+       u64 mptc;
+       u64 bptc;
+       u64 tsctc;
+       u64 tsctfc;
+       u64 iac;
+       u64 icrxptc;
+       u64 icrxatc;
+       u64 ictxptc;
+       u64 ictxatc;
+       u64 ictxqec;
+       u64 ictxqmtc;
+       u64 icrxdmtc;
+       u64 icrxoc;
 };
 
 /* Structure containing variables used by the shared code (e1000_hw.c) */
 struct e1000_hw {
-       u8 __iomem              *hw_addr;
-       u8 __iomem              *flash_address;
-       e1000_mac_type          mac_type;
-       e1000_phy_type          phy_type;
-       u32             phy_init_script;
-       e1000_media_type        media_type;
-       void                    *back;
-       struct e1000_shadow_ram *eeprom_shadow_ram;
-       u32             flash_bank_size;
-       u32             flash_base_addr;
-       e1000_fc_type           fc;
-       e1000_bus_speed         bus_speed;
-       e1000_bus_width         bus_width;
-       e1000_bus_type          bus_type;
+       u8 __iomem *hw_addr;
+       u8 __iomem *flash_address;
+       e1000_mac_type mac_type;
+       e1000_phy_type phy_type;
+       u32 phy_init_script;
+       e1000_media_type media_type;
+       void *back;
+       struct e1000_shadow_ram *eeprom_shadow_ram;
+       u32 flash_bank_size;
+       u32 flash_base_addr;
+       e1000_fc_type fc;
+       e1000_bus_speed bus_speed;
+       e1000_bus_width bus_width;
+       e1000_bus_type bus_type;
        struct e1000_eeprom_info eeprom;
-       e1000_ms_type           master_slave;
-       e1000_ms_type           original_master_slave;
-       e1000_ffe_config        ffe_config_state;
-       u32             asf_firmware_present;
-       u32             eeprom_semaphore_present;
-       unsigned long           io_base;
-       u32             phy_id;
-       u32             phy_revision;
-       u32             phy_addr;
-       u32             original_fc;
-       u32             txcw;
-       u32             autoneg_failed;
-       u32             max_frame_size;
-       u32             min_frame_size;
-       u32             mc_filter_type;
-       u32             num_mc_addrs;
-       u32             collision_delta;
-       u32             tx_packet_delta;
-       u32             ledctl_default;
-       u32             ledctl_mode1;
-       u32             ledctl_mode2;
-       bool                    tx_pkt_filtering;
+       e1000_ms_type master_slave;
+       e1000_ms_type original_master_slave;
+       e1000_ffe_config ffe_config_state;
+       u32 asf_firmware_present;
+       u32 eeprom_semaphore_present;
+       unsigned long io_base;
+       u32 phy_id;
+       u32 phy_revision;
+       u32 phy_addr;
+       u32 original_fc;
+       u32 txcw;
+       u32 autoneg_failed;
+       u32 max_frame_size;
+       u32 min_frame_size;
+       u32 mc_filter_type;
+       u32 num_mc_addrs;
+       u32 collision_delta;
+       u32 tx_packet_delta;
+       u32 ledctl_default;
+       u32 ledctl_mode1;
+       u32 ledctl_mode2;
+       bool tx_pkt_filtering;
        struct e1000_host_mng_dhcp_cookie mng_cookie;
-       u16             phy_spd_default;
-       u16             autoneg_advertised;
-       u16             pci_cmd_word;
-       u16             fc_high_water;
-       u16             fc_low_water;
-       u16             fc_pause_time;
-       u16             current_ifs_val;
-       u16             ifs_min_val;
-       u16             ifs_max_val;
-       u16             ifs_step_size;
-       u16             ifs_ratio;
-       u16             device_id;
-       u16             vendor_id;
-       u16             subsystem_id;
-       u16             subsystem_vendor_id;
-       u8                      revision_id;
-       u8                      autoneg;
-       u8                      mdix;
-       u8                      forced_speed_duplex;
-       u8                      wait_autoneg_complete;
-       u8                      dma_fairness;
-       u8                      mac_addr[NODE_ADDRESS_SIZE];
-       u8                      perm_mac_addr[NODE_ADDRESS_SIZE];
-       bool                    disable_polarity_correction;
-       bool                    speed_downgraded;
-       e1000_smart_speed       smart_speed;
-       e1000_dsp_config        dsp_config_state;
-       bool                    get_link_status;
-       bool                    serdes_has_link;
-       bool                    tbi_compatibility_en;
-       bool                    tbi_compatibility_on;
-       bool                    laa_is_present;
-       bool                    phy_reset_disable;
-       bool                    initialize_hw_bits_disable;
-       bool                    fc_send_xon;
-       bool                    fc_strict_ieee;
-       bool                    report_tx_early;
-       bool                    adaptive_ifs;
-       bool                    ifs_params_forced;
-       bool                    in_ifs_mode;
-       bool                    mng_reg_access_disabled;
-       bool                    leave_av_bit_off;
-       bool                    bad_tx_carr_stats_fd;
-       bool                    has_smbus;
+       u16 phy_spd_default;
+       u16 autoneg_advertised;
+       u16 pci_cmd_word;
+       u16 fc_high_water;
+       u16 fc_low_water;
+       u16 fc_pause_time;
+       u16 current_ifs_val;
+       u16 ifs_min_val;
+       u16 ifs_max_val;
+       u16 ifs_step_size;
+       u16 ifs_ratio;
+       u16 device_id;
+       u16 vendor_id;
+       u16 subsystem_id;
+       u16 subsystem_vendor_id;
+       u8 revision_id;
+       u8 autoneg;
+       u8 mdix;
+       u8 forced_speed_duplex;
+       u8 wait_autoneg_complete;
+       u8 dma_fairness;
+       u8 mac_addr[NODE_ADDRESS_SIZE];
+       u8 perm_mac_addr[NODE_ADDRESS_SIZE];
+       bool disable_polarity_correction;
+       bool speed_downgraded;
+       e1000_smart_speed smart_speed;
+       e1000_dsp_config dsp_config_state;
+       bool get_link_status;
+       bool serdes_has_link;
+       bool tbi_compatibility_en;
+       bool tbi_compatibility_on;
+       bool laa_is_present;
+       bool phy_reset_disable;
+       bool initialize_hw_bits_disable;
+       bool fc_send_xon;
+       bool fc_strict_ieee;
+       bool report_tx_early;
+       bool adaptive_ifs;
+       bool ifs_params_forced;
+       bool in_ifs_mode;
+       bool mng_reg_access_disabled;
+       bool leave_av_bit_off;
+       bool bad_tx_carr_stats_fd;
+       bool has_smbus;
 };
 
-
-#define E1000_EEPROM_SWDPIN0   0x0001   /* SWDPIN 0 EEPROM Value */
-#define E1000_EEPROM_LED_LOGIC 0x0020   /* Led Logic Word */
-#define E1000_EEPROM_RW_REG_DATA   16   /* Offset to data in EEPROM read/write registers */
-#define E1000_EEPROM_RW_REG_DONE   2    /* Offset to READ/WRITE done bit */
-#define E1000_EEPROM_RW_REG_START  1    /* First bit for telling part to start operation */
-#define E1000_EEPROM_RW_ADDR_SHIFT 2    /* Shift to the address bits */
-#define E1000_EEPROM_POLL_WRITE    1    /* Flag for polling for write complete */
-#define E1000_EEPROM_POLL_READ     0    /* Flag for polling for read complete */
+#define E1000_EEPROM_SWDPIN0   0x0001  /* SWDPIN 0 EEPROM Value */
+#define E1000_EEPROM_LED_LOGIC 0x0020  /* Led Logic Word */
+#define E1000_EEPROM_RW_REG_DATA   16  /* Offset to data in EEPROM read/write registers */
+#define E1000_EEPROM_RW_REG_DONE   2   /* Offset to READ/WRITE done bit */
+#define E1000_EEPROM_RW_REG_START  1   /* First bit for telling part to start operation */
+#define E1000_EEPROM_RW_ADDR_SHIFT 2   /* Shift to the address bits */
+#define E1000_EEPROM_POLL_WRITE    1   /* Flag for polling for write complete */
+#define E1000_EEPROM_POLL_READ     0   /* Flag for polling for read complete */
 /* Register Bit Masks */
 /* Device Control */
-#define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
-#define E1000_CTRL_BEM      0x00000002  /* Endian Mode.0=little,1=big */
-#define E1000_CTRL_PRIOR    0x00000004  /* Priority on PCI. 0=rx,1=fair */
-#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
-#define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */
-#define E1000_CTRL_TME      0x00000010  /* Test mode. 0=normal,1=test */
-#define E1000_CTRL_SLE      0x00000020  /* Serial Link on 0=dis,1=en */
-#define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
-#define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
-#define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
-#define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
-#define E1000_CTRL_SPD_10   0x00000000  /* Force 10Mb */
-#define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
-#define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
-#define E1000_CTRL_BEM32    0x00000400  /* Big Endian 32 mode */
-#define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
-#define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
-#define E1000_CTRL_D_UD_EN  0x00002000  /* Dock/Undock enable */
-#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */
-#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */
-#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */
-#define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
-#define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
-#define E1000_CTRL_SWDPIN2  0x00100000  /* SWDPIN 2 value */
-#define E1000_CTRL_SWDPIN3  0x00200000  /* SWDPIN 3 value */
-#define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */
-#define E1000_CTRL_SWDPIO1  0x00800000  /* SWDPIN 1 input or output */
-#define E1000_CTRL_SWDPIO2  0x01000000  /* SWDPIN 2 input or output */
-#define E1000_CTRL_SWDPIO3  0x02000000  /* SWDPIN 3 input or output */
-#define E1000_CTRL_RST      0x04000000  /* Global reset */
-#define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
-#define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
-#define E1000_CTRL_RTE      0x20000000  /* Routing tag enable */
-#define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
-#define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
-#define E1000_CTRL_SW2FW_INT 0x02000000  /* Initiate an interrupt to manageability engine */
+#define E1000_CTRL_FD       0x00000001 /* Full duplex.0=half; 1=full */
+#define E1000_CTRL_BEM      0x00000002 /* Endian Mode.0=little,1=big */
+#define E1000_CTRL_PRIOR    0x00000004 /* Priority on PCI. 0=rx,1=fair */
+#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004       /*Blocks new Master requests */
+#define E1000_CTRL_LRST     0x00000008 /* Link reset. 0=normal,1=reset */
+#define E1000_CTRL_TME      0x00000010 /* Test mode. 0=normal,1=test */
+#define E1000_CTRL_SLE      0x00000020 /* Serial Link on 0=dis,1=en */
+#define E1000_CTRL_ASDE     0x00000020 /* Auto-speed detect enable */
+#define E1000_CTRL_SLU      0x00000040 /* Set link up (Force Link) */
+#define E1000_CTRL_ILOS     0x00000080 /* Invert Loss-Of Signal */
+#define E1000_CTRL_SPD_SEL  0x00000300 /* Speed Select Mask */
+#define E1000_CTRL_SPD_10   0x00000000 /* Force 10Mb */
+#define E1000_CTRL_SPD_100  0x00000100 /* Force 100Mb */
+#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
+#define E1000_CTRL_BEM32    0x00000400 /* Big Endian 32 mode */
+#define E1000_CTRL_FRCSPD   0x00000800 /* Force Speed */
+#define E1000_CTRL_FRCDPX   0x00001000 /* Force Duplex */
+#define E1000_CTRL_D_UD_EN  0x00002000 /* Dock/Undock enable */
+#define E1000_CTRL_D_UD_POLARITY 0x00004000    /* Defined polarity of Dock/Undock indication in SDP[0] */
+#define E1000_CTRL_FORCE_PHY_RESET 0x00008000  /* Reset both PHY ports, through PHYRST_N pin */
+#define E1000_CTRL_EXT_LINK_EN 0x00010000      /* enable link status from external LINK_0 and LINK_1 pins */
+#define E1000_CTRL_SWDPIN0  0x00040000 /* SWDPIN 0 value */
+#define E1000_CTRL_SWDPIN1  0x00080000 /* SWDPIN 1 value */
+#define E1000_CTRL_SWDPIN2  0x00100000 /* SWDPIN 2 value */
+#define E1000_CTRL_SWDPIN3  0x00200000 /* SWDPIN 3 value */
+#define E1000_CTRL_SWDPIO0  0x00400000 /* SWDPIN 0 Input or output */
+#define E1000_CTRL_SWDPIO1  0x00800000 /* SWDPIN 1 input or output */
+#define E1000_CTRL_SWDPIO2  0x01000000 /* SWDPIN 2 input or output */
+#define E1000_CTRL_SWDPIO3  0x02000000 /* SWDPIN 3 input or output */
+#define E1000_CTRL_RST      0x04000000 /* Global reset */
+#define E1000_CTRL_RFCE     0x08000000 /* Receive Flow Control enable */
+#define E1000_CTRL_TFCE     0x10000000 /* Transmit flow control enable */
+#define E1000_CTRL_RTE      0x20000000 /* Routing tag enable */
+#define E1000_CTRL_VME      0x40000000 /* IEEE VLAN mode enable */
+#define E1000_CTRL_PHY_RST  0x80000000 /* PHY Reset */
+#define E1000_CTRL_SW2FW_INT 0x02000000        /* Initiate an interrupt to manageability engine */
 
 /* Device Status */
-#define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
-#define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
-#define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
+#define E1000_STATUS_FD         0x00000001     /* Full duplex.0=half,1=full */
+#define E1000_STATUS_LU         0x00000002     /* Link up.0=no,1=link */
+#define E1000_STATUS_FUNC_MASK  0x0000000C     /* PCI Function Mask */
 #define E1000_STATUS_FUNC_SHIFT 2
-#define E1000_STATUS_FUNC_0     0x00000000      /* Function 0 */
-#define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
-#define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
-#define E1000_STATUS_TBIMODE    0x00000020      /* TBI mode */
+#define E1000_STATUS_FUNC_0     0x00000000     /* Function 0 */
+#define E1000_STATUS_FUNC_1     0x00000004     /* Function 1 */
+#define E1000_STATUS_TXOFF      0x00000010     /* transmission paused */
+#define E1000_STATUS_TBIMODE    0x00000020     /* TBI mode */
 #define E1000_STATUS_SPEED_MASK 0x000000C0
-#define E1000_STATUS_SPEED_10   0x00000000      /* Speed 10Mb/s */
-#define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
-#define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
-#define E1000_STATUS_LAN_INIT_DONE 0x00000200   /* Lan Init Completion
-                                                   by EEPROM/Flash */
-#define E1000_STATUS_ASDV       0x00000300      /* Auto speed detect value */
-#define E1000_STATUS_DOCK_CI    0x00000800      /* Change in Dock/Undock state. Clear on write '0'. */
-#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
-#define E1000_STATUS_MTXCKOK    0x00000400      /* MTX clock running OK */
-#define E1000_STATUS_PCI66      0x00000800      /* In 66Mhz slot */
-#define E1000_STATUS_BUS64      0x00001000      /* In 64 bit slot */
-#define E1000_STATUS_PCIX_MODE  0x00002000      /* PCI-X mode */
-#define E1000_STATUS_PCIX_SPEED 0x0000C000      /* PCI-X bus speed */
-#define E1000_STATUS_BMC_SKU_0  0x00100000 /* BMC USB redirect disabled */
-#define E1000_STATUS_BMC_SKU_1  0x00200000 /* BMC SRAM disabled */
-#define E1000_STATUS_BMC_SKU_2  0x00400000 /* BMC SDRAM disabled */
-#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
-#define E1000_STATUS_BMC_LITE   0x01000000 /* BMC external code execution disabled */
-#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
+#define E1000_STATUS_SPEED_10   0x00000000     /* Speed 10Mb/s */
+#define E1000_STATUS_SPEED_100  0x00000040     /* Speed 100Mb/s */
+#define E1000_STATUS_SPEED_1000 0x00000080     /* Speed 1000Mb/s */
+#define E1000_STATUS_LAN_INIT_DONE 0x00000200  /* Lan Init Completion
+                                                  by EEPROM/Flash */
+#define E1000_STATUS_ASDV       0x00000300     /* Auto speed detect value */
+#define E1000_STATUS_DOCK_CI    0x00000800     /* Change in Dock/Undock state. Clear on write '0'. */
+#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000      /* Status of Master requests. */
+#define E1000_STATUS_MTXCKOK    0x00000400     /* MTX clock running OK */
+#define E1000_STATUS_PCI66      0x00000800     /* In 66Mhz slot */
+#define E1000_STATUS_BUS64      0x00001000     /* In 64 bit slot */
+#define E1000_STATUS_PCIX_MODE  0x00002000     /* PCI-X mode */
+#define E1000_STATUS_PCIX_SPEED 0x0000C000     /* PCI-X bus speed */
+#define E1000_STATUS_BMC_SKU_0  0x00100000     /* BMC USB redirect disabled */
+#define E1000_STATUS_BMC_SKU_1  0x00200000     /* BMC SRAM disabled */
+#define E1000_STATUS_BMC_SKU_2  0x00400000     /* BMC SDRAM disabled */
+#define E1000_STATUS_BMC_CRYPTO 0x00800000     /* BMC crypto disabled */
+#define E1000_STATUS_BMC_LITE   0x01000000     /* BMC external code execution disabled */
+#define E1000_STATUS_RGMII_ENABLE 0x02000000   /* RGMII disabled */
 #define E1000_STATUS_FUSE_8       0x04000000
 #define E1000_STATUS_FUSE_9       0x08000000
-#define E1000_STATUS_SERDES0_DIS  0x10000000 /* SERDES disabled on port 0 */
-#define E1000_STATUS_SERDES1_DIS  0x20000000 /* SERDES disabled on port 1 */
+#define E1000_STATUS_SERDES0_DIS  0x10000000   /* SERDES disabled on port 0 */
+#define E1000_STATUS_SERDES1_DIS  0x20000000   /* SERDES disabled on port 1 */
 
-/* Constants used to intrepret the masked PCI-X bus speed. */
-#define E1000_STATUS_PCIX_SPEED_66  0x00000000 /* PCI-X bus speed  50-66 MHz */
-#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed  66-100 MHz */
-#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
+/* Constants used to interpret the masked PCI-X bus speed. */
+#define E1000_STATUS_PCIX_SPEED_66  0x00000000 /* PCI-X bus speed  50-66 MHz */
+#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed  66-100 MHz */
+#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
 
 /* EEPROM/Flash Control */
-#define E1000_EECD_SK        0x00000001 /* EEPROM Clock */
-#define E1000_EECD_CS        0x00000002 /* EEPROM Chip Select */
-#define E1000_EECD_DI        0x00000004 /* EEPROM Data In */
-#define E1000_EECD_DO        0x00000008 /* EEPROM Data Out */
+#define E1000_EECD_SK        0x00000001        /* EEPROM Clock */
+#define E1000_EECD_CS        0x00000002        /* EEPROM Chip Select */
+#define E1000_EECD_DI        0x00000004        /* EEPROM Data In */
+#define E1000_EECD_DO        0x00000008        /* EEPROM Data Out */
 #define E1000_EECD_FWE_MASK  0x00000030
-#define E1000_EECD_FWE_DIS   0x00000010 /* Disable FLASH writes */
-#define E1000_EECD_FWE_EN    0x00000020 /* Enable FLASH writes */
+#define E1000_EECD_FWE_DIS   0x00000010        /* Disable FLASH writes */
+#define E1000_EECD_FWE_EN    0x00000020        /* Enable FLASH writes */
 #define E1000_EECD_FWE_SHIFT 4
-#define E1000_EECD_REQ       0x00000040 /* EEPROM Access Request */
-#define E1000_EECD_GNT       0x00000080 /* EEPROM Access Grant */
-#define E1000_EECD_PRES      0x00000100 /* EEPROM Present */
-#define E1000_EECD_SIZE      0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
-#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
-                                         * (0-small, 1-large) */
-#define E1000_EECD_TYPE      0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
+#define E1000_EECD_REQ       0x00000040        /* EEPROM Access Request */
+#define E1000_EECD_GNT       0x00000080        /* EEPROM Access Grant */
+#define E1000_EECD_PRES      0x00000100        /* EEPROM Present */
+#define E1000_EECD_SIZE      0x00000200        /* EEPROM Size (0=64 word 1=256 word) */
+#define E1000_EECD_ADDR_BITS 0x00000400        /* EEPROM Addressing bits based on type
+                                        * (0-small, 1-large) */
+#define E1000_EECD_TYPE      0x00002000        /* EEPROM Type (1-SPI, 0-Microwire) */
 #ifndef E1000_EEPROM_GRANT_ATTEMPTS
-#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
+#define E1000_EEPROM_GRANT_ATTEMPTS 1000       /* EEPROM # attempts to gain grant */
 #endif
-#define E1000_EECD_AUTO_RD          0x00000200  /* EEPROM Auto Read done */
-#define E1000_EECD_SIZE_EX_MASK     0x00007800  /* EEprom Size */
+#define E1000_EECD_AUTO_RD          0x00000200 /* EEPROM Auto Read done */
+#define E1000_EECD_SIZE_EX_MASK     0x00007800 /* EEprom Size */
 #define E1000_EECD_SIZE_EX_SHIFT    11
-#define E1000_EECD_NVADDS    0x00018000 /* NVM Address Size */
-#define E1000_EECD_SELSHAD   0x00020000 /* Select Shadow RAM */
-#define E1000_EECD_INITSRAM  0x00040000 /* Initialize Shadow RAM */
-#define E1000_EECD_FLUPD     0x00080000 /* Update FLASH */
-#define E1000_EECD_AUPDEN    0x00100000 /* Enable Autonomous FLASH update */
-#define E1000_EECD_SHADV     0x00200000 /* Shadow RAM Data Valid */
-#define E1000_EECD_SEC1VAL   0x00400000 /* Sector One Valid */
+#define E1000_EECD_NVADDS    0x00018000        /* NVM Address Size */
+#define E1000_EECD_SELSHAD   0x00020000        /* Select Shadow RAM */
+#define E1000_EECD_INITSRAM  0x00040000        /* Initialize Shadow RAM */
+#define E1000_EECD_FLUPD     0x00080000        /* Update FLASH */
+#define E1000_EECD_AUPDEN    0x00100000        /* Enable Autonomous FLASH update */
+#define E1000_EECD_SHADV     0x00200000        /* Shadow RAM Data Valid */
+#define E1000_EECD_SEC1VAL   0x00400000        /* Sector One Valid */
 #define E1000_EECD_SECVAL_SHIFT      22
 #define E1000_STM_OPCODE     0xDB00
 #define E1000_HICR_FW_RESET  0xC0
@@ -1515,12 +1509,12 @@ struct e1000_hw {
 #define E1000_ICH_NVM_SIG_MASK     0xC0
 
 /* EEPROM Read */
-#define E1000_EERD_START      0x00000001 /* Start Read */
-#define E1000_EERD_DONE       0x00000010 /* Read Done */
+#define E1000_EERD_START      0x00000001       /* Start Read */
+#define E1000_EERD_DONE       0x00000010       /* Read Done */
 #define E1000_EERD_ADDR_SHIFT 8
-#define E1000_EERD_ADDR_MASK  0x0000FF00 /* Read Address */
+#define E1000_EERD_ADDR_MASK  0x0000FF00       /* Read Address */
 #define E1000_EERD_DATA_SHIFT 16
-#define E1000_EERD_DATA_MASK  0xFFFF0000 /* Read Data */
+#define E1000_EERD_DATA_MASK  0xFFFF0000       /* Read Data */
 
 /* SPI EEPROM Status Register */
 #define EEPROM_STATUS_RDY_SPI  0x01
@@ -1530,25 +1524,25 @@ struct e1000_hw {
 #define EEPROM_STATUS_WPEN_SPI 0x80
 
 /* Extended Device Control */
-#define E1000_CTRL_EXT_GPI0_EN   0x00000001 /* Maps SDP4 to GPI0 */
-#define E1000_CTRL_EXT_GPI1_EN   0x00000002 /* Maps SDP5 to GPI1 */
+#define E1000_CTRL_EXT_GPI0_EN   0x00000001    /* Maps SDP4 to GPI0 */
+#define E1000_CTRL_EXT_GPI1_EN   0x00000002    /* Maps SDP5 to GPI1 */
 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
-#define E1000_CTRL_EXT_GPI2_EN   0x00000004 /* Maps SDP6 to GPI2 */
-#define E1000_CTRL_EXT_GPI3_EN   0x00000008 /* Maps SDP7 to GPI3 */
-#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
-#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
+#define E1000_CTRL_EXT_GPI2_EN   0x00000004    /* Maps SDP6 to GPI2 */
+#define E1000_CTRL_EXT_GPI3_EN   0x00000008    /* Maps SDP7 to GPI3 */
+#define E1000_CTRL_EXT_SDP4_DATA 0x00000010    /* Value of SW Defineable Pin 4 */
+#define E1000_CTRL_EXT_SDP5_DATA 0x00000020    /* Value of SW Defineable Pin 5 */
 #define E1000_CTRL_EXT_PHY_INT   E1000_CTRL_EXT_SDP5_DATA
-#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
-#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
-#define E1000_CTRL_EXT_SDP4_DIR  0x00000100 /* Direction of SDP4 0=in 1=out */
-#define E1000_CTRL_EXT_SDP5_DIR  0x00000200 /* Direction of SDP5 0=in 1=out */
-#define E1000_CTRL_EXT_SDP6_DIR  0x00000400 /* Direction of SDP6 0=in 1=out */
-#define E1000_CTRL_EXT_SDP7_DIR  0x00000800 /* Direction of SDP7 0=in 1=out */
-#define E1000_CTRL_EXT_ASDCHK    0x00001000 /* Initiate an ASD sequence */
-#define E1000_CTRL_EXT_EE_RST    0x00002000 /* Reinitialize from EEPROM */
-#define E1000_CTRL_EXT_IPS       0x00004000 /* Invert Power State */
-#define E1000_CTRL_EXT_SPD_BYPS  0x00008000 /* Speed Select Bypass */
-#define E1000_CTRL_EXT_RO_DIS    0x00020000 /* Relaxed Ordering disable */
+#define E1000_CTRL_EXT_SDP6_DATA 0x00000040    /* Value of SW Defineable Pin 6 */
+#define E1000_CTRL_EXT_SDP7_DATA 0x00000080    /* Value of SW Defineable Pin 7 */
+#define E1000_CTRL_EXT_SDP4_DIR  0x00000100    /* Direction of SDP4 0=in 1=out */
+#define E1000_CTRL_EXT_SDP5_DIR  0x00000200    /* Direction of SDP5 0=in 1=out */
+#define E1000_CTRL_EXT_SDP6_DIR  0x00000400    /* Direction of SDP6 0=in 1=out */
+#define E1000_CTRL_EXT_SDP7_DIR  0x00000800    /* Direction of SDP7 0=in 1=out */
+#define E1000_CTRL_EXT_ASDCHK    0x00001000    /* Initiate an ASD sequence */
+#define E1000_CTRL_EXT_EE_RST    0x00002000    /* Reinitialize from EEPROM */
+#define E1000_CTRL_EXT_IPS       0x00004000    /* Invert Power State */
+#define E1000_CTRL_EXT_SPD_BYPS  0x00008000    /* Speed Select Bypass */
+#define E1000_CTRL_EXT_RO_DIS    0x00020000    /* Relaxed Ordering disable */
 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
 #define E1000_CTRL_EXT_LINK_MODE_TBI  0x00C00000
@@ -1560,11 +1554,11 @@ struct e1000_hw {
 #define E1000_CTRL_EXT_WR_WMARK_320   0x01000000
 #define E1000_CTRL_EXT_WR_WMARK_384   0x02000000
 #define E1000_CTRL_EXT_WR_WMARK_448   0x03000000
-#define E1000_CTRL_EXT_DRV_LOAD       0x10000000 /* Driver loaded bit for FW */
-#define E1000_CTRL_EXT_IAME           0x08000000 /* Interrupt acknowledge Auto-mask */
-#define E1000_CTRL_EXT_INT_TIMER_CLR  0x20000000 /* Clear Interrupt timers after IMS clear */
-#define E1000_CRTL_EXT_PB_PAREN       0x01000000 /* packet buffer parity error detection enabled */
-#define E1000_CTRL_EXT_DF_PAREN       0x02000000 /* descriptor FIFO parity error detection enable */
+#define E1000_CTRL_EXT_DRV_LOAD       0x10000000       /* Driver loaded bit for FW */
+#define E1000_CTRL_EXT_IAME           0x08000000       /* Interrupt acknowledge Auto-mask */
+#define E1000_CTRL_EXT_INT_TIMER_CLR  0x20000000       /* Clear Interrupt timers after IMS clear */
+#define E1000_CRTL_EXT_PB_PAREN       0x01000000       /* packet buffer parity error detection enabled */
+#define E1000_CTRL_EXT_DF_PAREN       0x02000000       /* descriptor FIFO parity error detection enable */
 #define E1000_CTRL_EXT_GHOST_PAREN    0x40000000
 
 /* MDI Control */
@@ -1664,167 +1658,167 @@ struct e1000_hw {
 #define E1000_LEDCTL_MODE_LED_OFF       0xF
 
 /* Receive Address */
-#define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
+#define E1000_RAH_AV  0x80000000       /* Receive descriptor valid */
 
 /* Interrupt Cause Read */
-#define E1000_ICR_TXDW          0x00000001 /* Transmit desc written back */
-#define E1000_ICR_TXQE          0x00000002 /* Transmit Queue empty */
-#define E1000_ICR_LSC           0x00000004 /* Link Status Change */
-#define E1000_ICR_RXSEQ         0x00000008 /* rx sequence error */
-#define E1000_ICR_RXDMT0        0x00000010 /* rx desc min. threshold (0) */
-#define E1000_ICR_RXO           0x00000040 /* rx overrun */
-#define E1000_ICR_RXT0          0x00000080 /* rx timer intr (ring 0) */
-#define E1000_ICR_MDAC          0x00000200 /* MDIO access complete */
-#define E1000_ICR_RXCFG         0x00000400 /* RX /c/ ordered set */
-#define E1000_ICR_GPI_EN0       0x00000800 /* GP Int 0 */
-#define E1000_ICR_GPI_EN1       0x00001000 /* GP Int 1 */
-#define E1000_ICR_GPI_EN2       0x00002000 /* GP Int 2 */
-#define E1000_ICR_GPI_EN3       0x00004000 /* GP Int 3 */
+#define E1000_ICR_TXDW          0x00000001     /* Transmit desc written back */
+#define E1000_ICR_TXQE          0x00000002     /* Transmit Queue empty */
+#define E1000_ICR_LSC           0x00000004     /* Link Status Change */
+#define E1000_ICR_RXSEQ         0x00000008     /* rx sequence error */
+#define E1000_ICR_RXDMT0        0x00000010     /* rx desc min. threshold (0) */
+#define E1000_ICR_RXO           0x00000040     /* rx overrun */
+#define E1000_ICR_RXT0          0x00000080     /* rx timer intr (ring 0) */
+#define E1000_ICR_MDAC          0x00000200     /* MDIO access complete */
+#define E1000_ICR_RXCFG         0x00000400     /* RX /c/ ordered set */
+#define E1000_ICR_GPI_EN0       0x00000800     /* GP Int 0 */
+#define E1000_ICR_GPI_EN1       0x00001000     /* GP Int 1 */
+#define E1000_ICR_GPI_EN2       0x00002000     /* GP Int 2 */
+#define E1000_ICR_GPI_EN3       0x00004000     /* GP Int 3 */
 #define E1000_ICR_TXD_LOW       0x00008000
 #define E1000_ICR_SRPD          0x00010000
-#define E1000_ICR_ACK           0x00020000 /* Receive Ack frame */
-#define E1000_ICR_MNG           0x00040000 /* Manageability event */
-#define E1000_ICR_DOCK          0x00080000 /* Dock/Undock */
-#define E1000_ICR_INT_ASSERTED  0x80000000 /* If this bit asserted, the driver should claim the interrupt */
-#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */
-#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */
-#define E1000_ICR_HOST_ARB_PAR  0x00400000 /* host arb read buffer parity error */
-#define E1000_ICR_PB_PAR        0x00800000 /* packet buffer parity error */
-#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */
-#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */
-#define E1000_ICR_ALL_PARITY    0x03F00000 /* all parity error bits */
-#define E1000_ICR_DSW           0x00000020 /* FW changed the status of DISSW bit in the FWSM */
-#define E1000_ICR_PHYINT        0x00001000 /* LAN connected device generates an interrupt */
-#define E1000_ICR_EPRST         0x00100000 /* ME handware reset occurs */
+#define E1000_ICR_ACK           0x00020000     /* Receive Ack frame */
+#define E1000_ICR_MNG           0x00040000     /* Manageability event */
+#define E1000_ICR_DOCK          0x00080000     /* Dock/Undock */
+#define E1000_ICR_INT_ASSERTED  0x80000000     /* If this bit asserted, the driver should claim the interrupt */
+#define E1000_ICR_RXD_FIFO_PAR0 0x00100000     /* queue 0 Rx descriptor FIFO parity error */
+#define E1000_ICR_TXD_FIFO_PAR0 0x00200000     /* queue 0 Tx descriptor FIFO parity error */
+#define E1000_ICR_HOST_ARB_PAR  0x00400000     /* host arb read buffer parity error */
+#define E1000_ICR_PB_PAR        0x00800000     /* packet buffer parity error */
+#define E1000_ICR_RXD_FIFO_PAR1 0x01000000     /* queue 1 Rx descriptor FIFO parity error */
+#define E1000_ICR_TXD_FIFO_PAR1 0x02000000     /* queue 1 Tx descriptor FIFO parity error */
+#define E1000_ICR_ALL_PARITY    0x03F00000     /* all parity error bits */
+#define E1000_ICR_DSW           0x00000020     /* FW changed the status of DISSW bit in the FWSM */
+#define E1000_ICR_PHYINT        0x00001000     /* LAN connected device generates an interrupt */
+#define E1000_ICR_EPRST         0x00100000     /* ME hardware reset occurs */
 
 /* Interrupt Cause Set */
-#define E1000_ICS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
-#define E1000_ICS_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
-#define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */
-#define E1000_ICS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
-#define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
-#define E1000_ICS_RXO       E1000_ICR_RXO       /* rx overrun */
-#define E1000_ICS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
-#define E1000_ICS_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
-#define E1000_ICS_RXCFG     E1000_ICR_RXCFG     /* RX /c/ ordered set */
-#define E1000_ICS_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
-#define E1000_ICS_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
-#define E1000_ICS_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
-#define E1000_ICS_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
+#define E1000_ICS_TXDW      E1000_ICR_TXDW     /* Transmit desc written back */
+#define E1000_ICS_TXQE      E1000_ICR_TXQE     /* Transmit Queue empty */
+#define E1000_ICS_LSC       E1000_ICR_LSC      /* Link Status Change */
+#define E1000_ICS_RXSEQ     E1000_ICR_RXSEQ    /* rx sequence error */
+#define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0   /* rx desc min. threshold */
+#define E1000_ICS_RXO       E1000_ICR_RXO      /* rx overrun */
+#define E1000_ICS_RXT0      E1000_ICR_RXT0     /* rx timer intr */
+#define E1000_ICS_MDAC      E1000_ICR_MDAC     /* MDIO access complete */
+#define E1000_ICS_RXCFG     E1000_ICR_RXCFG    /* RX /c/ ordered set */
+#define E1000_ICS_GPI_EN0   E1000_ICR_GPI_EN0  /* GP Int 0 */
+#define E1000_ICS_GPI_EN1   E1000_ICR_GPI_EN1  /* GP Int 1 */
+#define E1000_ICS_GPI_EN2   E1000_ICR_GPI_EN2  /* GP Int 2 */
+#define E1000_ICS_GPI_EN3   E1000_ICR_GPI_EN3  /* GP Int 3 */
 #define E1000_ICS_TXD_LOW   E1000_ICR_TXD_LOW
 #define E1000_ICS_SRPD      E1000_ICR_SRPD
-#define E1000_ICS_ACK       E1000_ICR_ACK       /* Receive Ack frame */
-#define E1000_ICS_MNG       E1000_ICR_MNG       /* Manageability event */
-#define E1000_ICS_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
-#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
-#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
-#define E1000_ICS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer parity error */
-#define E1000_ICS_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity error */
-#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
-#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
+#define E1000_ICS_ACK       E1000_ICR_ACK      /* Receive Ack frame */
+#define E1000_ICS_MNG       E1000_ICR_MNG      /* Manageability event */
+#define E1000_ICS_DOCK      E1000_ICR_DOCK     /* Dock/Undock */
+#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0        /* queue 0 Rx descriptor FIFO parity error */
+#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0        /* queue 0 Tx descriptor FIFO parity error */
+#define E1000_ICS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
+#define E1000_ICS_PB_PAR        E1000_ICR_PB_PAR       /* packet buffer parity error */
+#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1        /* queue 1 Rx descriptor FIFO parity error */
+#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1        /* queue 1 Tx descriptor FIFO parity error */
 #define E1000_ICS_DSW       E1000_ICR_DSW
 #define E1000_ICS_PHYINT    E1000_ICR_PHYINT
 #define E1000_ICS_EPRST     E1000_ICR_EPRST
 
 /* Interrupt Mask Set */
-#define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
-#define E1000_IMS_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
-#define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */
-#define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
-#define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
-#define E1000_IMS_RXO       E1000_ICR_RXO       /* rx overrun */
-#define E1000_IMS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
-#define E1000_IMS_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
-#define E1000_IMS_RXCFG     E1000_ICR_RXCFG     /* RX /c/ ordered set */
-#define E1000_IMS_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
-#define E1000_IMS_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
-#define E1000_IMS_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
-#define E1000_IMS_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
+#define E1000_IMS_TXDW      E1000_ICR_TXDW     /* Transmit desc written back */
+#define E1000_IMS_TXQE      E1000_ICR_TXQE     /* Transmit Queue empty */
+#define E1000_IMS_LSC       E1000_ICR_LSC      /* Link Status Change */
+#define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ    /* rx sequence error */
+#define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0   /* rx desc min. threshold */
+#define E1000_IMS_RXO       E1000_ICR_RXO      /* rx overrun */
+#define E1000_IMS_RXT0      E1000_ICR_RXT0     /* rx timer intr */
+#define E1000_IMS_MDAC      E1000_ICR_MDAC     /* MDIO access complete */
+#define E1000_IMS_RXCFG     E1000_ICR_RXCFG    /* RX /c/ ordered set */
+#define E1000_IMS_GPI_EN0   E1000_ICR_GPI_EN0  /* GP Int 0 */
+#define E1000_IMS_GPI_EN1   E1000_ICR_GPI_EN1  /* GP Int 1 */
+#define E1000_IMS_GPI_EN2   E1000_ICR_GPI_EN2  /* GP Int 2 */
+#define E1000_IMS_GPI_EN3   E1000_ICR_GPI_EN3  /* GP Int 3 */
 #define E1000_IMS_TXD_LOW   E1000_ICR_TXD_LOW
 #define E1000_IMS_SRPD      E1000_ICR_SRPD
-#define E1000_IMS_ACK       E1000_ICR_ACK       /* Receive Ack frame */
-#define E1000_IMS_MNG       E1000_ICR_MNG       /* Manageability event */
-#define E1000_IMS_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
-#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
-#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
-#define E1000_IMS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer parity error */
-#define E1000_IMS_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity error */
-#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
-#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
+#define E1000_IMS_ACK       E1000_ICR_ACK      /* Receive Ack frame */
+#define E1000_IMS_MNG       E1000_ICR_MNG      /* Manageability event */
+#define E1000_IMS_DOCK      E1000_ICR_DOCK     /* Dock/Undock */
+#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0        /* queue 0 Rx descriptor FIFO parity error */
+#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0        /* queue 0 Tx descriptor FIFO parity error */
+#define E1000_IMS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
+#define E1000_IMS_PB_PAR        E1000_ICR_PB_PAR       /* packet buffer parity error */
+#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1        /* queue 1 Rx descriptor FIFO parity error */
+#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1        /* queue 1 Tx descriptor FIFO parity error */
 #define E1000_IMS_DSW       E1000_ICR_DSW
 #define E1000_IMS_PHYINT    E1000_ICR_PHYINT
 #define E1000_IMS_EPRST     E1000_ICR_EPRST
 
 /* Interrupt Mask Clear */
-#define E1000_IMC_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
-#define E1000_IMC_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
-#define E1000_IMC_LSC       E1000_ICR_LSC       /* Link Status Change */
-#define E1000_IMC_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
-#define E1000_IMC_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
-#define E1000_IMC_RXO       E1000_ICR_RXO       /* rx overrun */
-#define E1000_IMC_RXT0      E1000_ICR_RXT0      /* rx timer intr */
-#define E1000_IMC_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
-#define E1000_IMC_RXCFG     E1000_ICR_RXCFG     /* RX /c/ ordered set */
-#define E1000_IMC_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
-#define E1000_IMC_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
-#define E1000_IMC_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
-#define E1000_IMC_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
+#define E1000_IMC_TXDW      E1000_ICR_TXDW     /* Transmit desc written back */
+#define E1000_IMC_TXQE      E1000_ICR_TXQE     /* Transmit Queue empty */
+#define E1000_IMC_LSC       E1000_ICR_LSC      /* Link Status Change */
+#define E1000_IMC_RXSEQ     E1000_ICR_RXSEQ    /* rx sequence error */
+#define E1000_IMC_RXDMT0    E1000_ICR_RXDMT0   /* rx desc min. threshold */
+#define E1000_IMC_RXO       E1000_ICR_RXO      /* rx overrun */
+#define E1000_IMC_RXT0      E1000_ICR_RXT0     /* rx timer intr */
+#define E1000_IMC_MDAC      E1000_ICR_MDAC     /* MDIO access complete */
+#define E1000_IMC_RXCFG     E1000_ICR_RXCFG    /* RX /c/ ordered set */
+#define E1000_IMC_GPI_EN0   E1000_ICR_GPI_EN0  /* GP Int 0 */
+#define E1000_IMC_GPI_EN1   E1000_ICR_GPI_EN1  /* GP Int 1 */
+#define E1000_IMC_GPI_EN2   E1000_ICR_GPI_EN2  /* GP Int 2 */
+#define E1000_IMC_GPI_EN3   E1000_ICR_GPI_EN3  /* GP Int 3 */
 #define E1000_IMC_TXD_LOW   E1000_ICR_TXD_LOW
 #define E1000_IMC_SRPD      E1000_ICR_SRPD
-#define E1000_IMC_ACK       E1000_ICR_ACK       /* Receive Ack frame */
-#define E1000_IMC_MNG       E1000_ICR_MNG       /* Manageability event */
-#define E1000_IMC_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
-#define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
-#define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
-#define E1000_IMC_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer parity error */
-#define E1000_IMC_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity error */
-#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
-#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
+#define E1000_IMC_ACK       E1000_ICR_ACK      /* Receive Ack frame */
+#define E1000_IMC_MNG       E1000_ICR_MNG      /* Manageability event */
+#define E1000_IMC_DOCK      E1000_ICR_DOCK     /* Dock/Undock */
+#define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0        /* queue 0 Rx descriptor FIFO parity error */
+#define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0        /* queue 0 Tx descriptor FIFO parity error */
+#define E1000_IMC_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
+#define E1000_IMC_PB_PAR        E1000_ICR_PB_PAR       /* packet buffer parity error */
+#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1        /* queue 1 Rx descriptor FIFO parity error */
+#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1        /* queue 1 Tx descriptor FIFO parity error */
 #define E1000_IMC_DSW       E1000_ICR_DSW
 #define E1000_IMC_PHYINT    E1000_ICR_PHYINT
 #define E1000_IMC_EPRST     E1000_ICR_EPRST
 
 /* Receive Control */
-#define E1000_RCTL_RST            0x00000001    /* Software reset */
-#define E1000_RCTL_EN             0x00000002    /* enable */
-#define E1000_RCTL_SBP            0x00000004    /* store bad packet */
-#define E1000_RCTL_UPE            0x00000008    /* unicast promiscuous enable */
-#define E1000_RCTL_MPE            0x00000010    /* multicast promiscuous enab */
-#define E1000_RCTL_LPE            0x00000020    /* long packet enable */
-#define E1000_RCTL_LBM_NO         0x00000000    /* no loopback mode */
-#define E1000_RCTL_LBM_MAC        0x00000040    /* MAC loopback mode */
-#define E1000_RCTL_LBM_SLP        0x00000080    /* serial link loopback mode */
-#define E1000_RCTL_LBM_TCVR       0x000000C0    /* tcvr loopback mode */
-#define E1000_RCTL_DTYP_MASK      0x00000C00    /* Descriptor type mask */
-#define E1000_RCTL_DTYP_PS        0x00000400    /* Packet Split descriptor */
-#define E1000_RCTL_RDMTS_HALF     0x00000000    /* rx desc min threshold size */
-#define E1000_RCTL_RDMTS_QUAT     0x00000100    /* rx desc min threshold size */
-#define E1000_RCTL_RDMTS_EIGTH    0x00000200    /* rx desc min threshold size */
-#define E1000_RCTL_MO_SHIFT       12            /* multicast offset shift */
-#define E1000_RCTL_MO_0           0x00000000    /* multicast offset 11:0 */
-#define E1000_RCTL_MO_1           0x00001000    /* multicast offset 12:1 */
-#define E1000_RCTL_MO_2           0x00002000    /* multicast offset 13:2 */
-#define E1000_RCTL_MO_3           0x00003000    /* multicast offset 15:4 */
-#define E1000_RCTL_MDR            0x00004000    /* multicast desc ring 0 */
-#define E1000_RCTL_BAM            0x00008000    /* broadcast enable */
+#define E1000_RCTL_RST            0x00000001   /* Software reset */
+#define E1000_RCTL_EN             0x00000002   /* enable */
+#define E1000_RCTL_SBP            0x00000004   /* store bad packet */
+#define E1000_RCTL_UPE            0x00000008   /* unicast promiscuous enable */
+#define E1000_RCTL_MPE            0x00000010   /* multicast promiscuous enab */
+#define E1000_RCTL_LPE            0x00000020   /* long packet enable */
+#define E1000_RCTL_LBM_NO         0x00000000   /* no loopback mode */
+#define E1000_RCTL_LBM_MAC        0x00000040   /* MAC loopback mode */
+#define E1000_RCTL_LBM_SLP        0x00000080   /* serial link loopback mode */
+#define E1000_RCTL_LBM_TCVR       0x000000C0   /* tcvr loopback mode */
+#define E1000_RCTL_DTYP_MASK      0x00000C00   /* Descriptor type mask */
+#define E1000_RCTL_DTYP_PS        0x00000400   /* Packet Split descriptor */
+#define E1000_RCTL_RDMTS_HALF     0x00000000   /* rx desc min threshold size */
+#define E1000_RCTL_RDMTS_QUAT     0x00000100   /* rx desc min threshold size */
+#define E1000_RCTL_RDMTS_EIGTH    0x00000200   /* rx desc min threshold size */
+#define E1000_RCTL_MO_SHIFT       12   /* multicast offset shift */
+#define E1000_RCTL_MO_0           0x00000000   /* multicast offset 11:0 */
+#define E1000_RCTL_MO_1           0x00001000   /* multicast offset 12:1 */
+#define E1000_RCTL_MO_2           0x00002000   /* multicast offset 13:2 */
+#define E1000_RCTL_MO_3           0x00003000   /* multicast offset 15:4 */
+#define E1000_RCTL_MDR            0x00004000   /* multicast desc ring 0 */
+#define E1000_RCTL_BAM            0x00008000   /* broadcast enable */
 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
-#define E1000_RCTL_SZ_2048        0x00000000    /* rx buffer size 2048 */
-#define E1000_RCTL_SZ_1024        0x00010000    /* rx buffer size 1024 */
-#define E1000_RCTL_SZ_512         0x00020000    /* rx buffer size 512 */
-#define E1000_RCTL_SZ_256         0x00030000    /* rx buffer size 256 */
+#define E1000_RCTL_SZ_2048        0x00000000   /* rx buffer size 2048 */
+#define E1000_RCTL_SZ_1024        0x00010000   /* rx buffer size 1024 */
+#define E1000_RCTL_SZ_512         0x00020000   /* rx buffer size 512 */
+#define E1000_RCTL_SZ_256         0x00030000   /* rx buffer size 256 */
 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
-#define E1000_RCTL_SZ_16384       0x00010000    /* rx buffer size 16384 */
-#define E1000_RCTL_SZ_8192        0x00020000    /* rx buffer size 8192 */
-#define E1000_RCTL_SZ_4096        0x00030000    /* rx buffer size 4096 */
-#define E1000_RCTL_VFE            0x00040000    /* vlan filter enable */
-#define E1000_RCTL_CFIEN          0x00080000    /* canonical form enable */
-#define E1000_RCTL_CFI            0x00100000    /* canonical form indicator */
-#define E1000_RCTL_DPF            0x00400000    /* discard pause frames */
-#define E1000_RCTL_PMCF           0x00800000    /* pass MAC control frames */
-#define E1000_RCTL_BSEX           0x02000000    /* Buffer size extension */
-#define E1000_RCTL_SECRC          0x04000000    /* Strip Ethernet CRC */
-#define E1000_RCTL_FLXBUF_MASK    0x78000000    /* Flexible buffer size */
-#define E1000_RCTL_FLXBUF_SHIFT   27            /* Flexible buffer shift */
+#define E1000_RCTL_SZ_16384       0x00010000   /* rx buffer size 16384 */
+#define E1000_RCTL_SZ_8192        0x00020000   /* rx buffer size 8192 */
+#define E1000_RCTL_SZ_4096        0x00030000   /* rx buffer size 4096 */
+#define E1000_RCTL_VFE            0x00040000   /* vlan filter enable */
+#define E1000_RCTL_CFIEN          0x00080000   /* canonical form enable */
+#define E1000_RCTL_CFI            0x00100000   /* canonical form indicator */
+#define E1000_RCTL_DPF            0x00400000   /* discard pause frames */
+#define E1000_RCTL_PMCF           0x00800000   /* pass MAC control frames */
+#define E1000_RCTL_BSEX           0x02000000   /* Buffer size extension */
+#define E1000_RCTL_SECRC          0x04000000   /* Strip Ethernet CRC */
+#define E1000_RCTL_FLXBUF_MASK    0x78000000   /* Flexible buffer size */
+#define E1000_RCTL_FLXBUF_SHIFT   27   /* Flexible buffer shift */
 
 /* Use byte values for the following shift parameters
  * Usage:
@@ -1847,10 +1841,10 @@ struct e1000_hw {
 #define E1000_PSRCTL_BSIZE2_MASK   0x003F0000
 #define E1000_PSRCTL_BSIZE3_MASK   0x3F000000
 
-#define E1000_PSRCTL_BSIZE0_SHIFT  7            /* Shift _right_ 7 */
-#define E1000_PSRCTL_BSIZE1_SHIFT  2            /* Shift _right_ 2 */
-#define E1000_PSRCTL_BSIZE2_SHIFT  6            /* Shift _left_ 6 */
-#define E1000_PSRCTL_BSIZE3_SHIFT 14            /* Shift _left_ 14 */
+#define E1000_PSRCTL_BSIZE0_SHIFT  7   /* Shift _right_ 7 */
+#define E1000_PSRCTL_BSIZE1_SHIFT  2   /* Shift _right_ 2 */
+#define E1000_PSRCTL_BSIZE2_SHIFT  6   /* Shift _left_ 6 */
+#define E1000_PSRCTL_BSIZE3_SHIFT 14   /* Shift _left_ 14 */
 
 /* SW_W_SYNC definitions */
 #define E1000_SWFW_EEP_SM     0x0001
@@ -1859,17 +1853,17 @@ struct e1000_hw {
 #define E1000_SWFW_MAC_CSR_SM 0x0008
 
 /* Receive Descriptor */
-#define E1000_RDT_DELAY 0x0000ffff      /* Delay timer (1=1024us) */
-#define E1000_RDT_FPDB  0x80000000      /* Flush descriptor block */
-#define E1000_RDLEN_LEN 0x0007ff80      /* descriptor length */
-#define E1000_RDH_RDH   0x0000ffff      /* receive descriptor head */
-#define E1000_RDT_RDT   0x0000ffff      /* receive descriptor tail */
+#define E1000_RDT_DELAY 0x0000ffff     /* Delay timer (1=1024us) */
+#define E1000_RDT_FPDB  0x80000000     /* Flush descriptor block */
+#define E1000_RDLEN_LEN 0x0007ff80     /* descriptor length */
+#define E1000_RDH_RDH   0x0000ffff     /* receive descriptor head */
+#define E1000_RDT_RDT   0x0000ffff     /* receive descriptor tail */
 
 /* Flow Control */
-#define E1000_FCRTH_RTH  0x0000FFF8     /* Mask Bits[15:3] for RTH */
-#define E1000_FCRTH_XFCE 0x80000000     /* External Flow Control Enable */
-#define E1000_FCRTL_RTL  0x0000FFF8     /* Mask Bits[15:3] for RTL */
-#define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */
+#define E1000_FCRTH_RTH  0x0000FFF8    /* Mask Bits[15:3] for RTH */
+#define E1000_FCRTH_XFCE 0x80000000    /* External Flow Control Enable */
+#define E1000_FCRTL_RTL  0x0000FFF8    /* Mask Bits[15:3] for RTL */
+#define E1000_FCRTL_XONE 0x80000000    /* Enable XON frame transmission */
 
 /* Header split receive */
 #define E1000_RFCTL_ISCSI_DIS           0x00000001
@@ -1889,64 +1883,64 @@ struct e1000_hw {
 #define E1000_RFCTL_NEW_IPV6_EXT_DIS    0x00020000
 
 /* Receive Descriptor Control */
-#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
-#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
-#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
-#define E1000_RXDCTL_GRAN    0x01000000 /* RXDCTL Granularity */
+#define E1000_RXDCTL_PTHRESH 0x0000003F        /* RXDCTL Prefetch Threshold */
+#define E1000_RXDCTL_HTHRESH 0x00003F00        /* RXDCTL Host Threshold */
+#define E1000_RXDCTL_WTHRESH 0x003F0000        /* RXDCTL Writeback Threshold */
+#define E1000_RXDCTL_GRAN    0x01000000        /* RXDCTL Granularity */
 
 /* Transmit Descriptor Control */
-#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
-#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
-#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
-#define E1000_TXDCTL_GRAN    0x01000000 /* TXDCTL Granularity */
-#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
-#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
-#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
-                                              still to be processed. */
+#define E1000_TXDCTL_PTHRESH 0x0000003F        /* TXDCTL Prefetch Threshold */
+#define E1000_TXDCTL_HTHRESH 0x00003F00        /* TXDCTL Host Threshold */
+#define E1000_TXDCTL_WTHRESH 0x003F0000        /* TXDCTL Writeback Threshold */
+#define E1000_TXDCTL_GRAN    0x01000000        /* TXDCTL Granularity */
+#define E1000_TXDCTL_LWTHRESH 0xFE000000       /* TXDCTL Low Threshold */
+#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000        /* GRAN=1, WTHRESH=1 */
+#define E1000_TXDCTL_COUNT_DESC 0x00400000     /* Enable the counting of desc.
+                                                  still to be processed. */
 /* Transmit Configuration Word */
-#define E1000_TXCW_FD         0x00000020        /* TXCW full duplex */
-#define E1000_TXCW_HD         0x00000040        /* TXCW half duplex */
-#define E1000_TXCW_PAUSE      0x00000080        /* TXCW sym pause request */
-#define E1000_TXCW_ASM_DIR    0x00000100        /* TXCW astm pause direction */
-#define E1000_TXCW_PAUSE_MASK 0x00000180        /* TXCW pause request mask */
-#define E1000_TXCW_RF         0x00003000        /* TXCW remote fault */
-#define E1000_TXCW_NP         0x00008000        /* TXCW next page */
-#define E1000_TXCW_CW         0x0000ffff        /* TxConfigWord mask */
-#define E1000_TXCW_TXC        0x40000000        /* Transmit Config control */
-#define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
+#define E1000_TXCW_FD         0x00000020       /* TXCW full duplex */
+#define E1000_TXCW_HD         0x00000040       /* TXCW half duplex */
+#define E1000_TXCW_PAUSE      0x00000080       /* TXCW sym pause request */
+#define E1000_TXCW_ASM_DIR    0x00000100       /* TXCW astm pause direction */
+#define E1000_TXCW_PAUSE_MASK 0x00000180       /* TXCW pause request mask */
+#define E1000_TXCW_RF         0x00003000       /* TXCW remote fault */
+#define E1000_TXCW_NP         0x00008000       /* TXCW next page */
+#define E1000_TXCW_CW         0x0000ffff       /* TxConfigWord mask */
+#define E1000_TXCW_TXC        0x40000000       /* Transmit Config control */
+#define E1000_TXCW_ANE        0x80000000       /* Auto-neg enable */
 
 /* Receive Configuration Word */
-#define E1000_RXCW_CW    0x0000ffff     /* RxConfigWord mask */
-#define E1000_RXCW_NC    0x04000000     /* Receive config no carrier */
-#define E1000_RXCW_IV    0x08000000     /* Receive config invalid */
-#define E1000_RXCW_CC    0x10000000     /* Receive config change */
-#define E1000_RXCW_C     0x20000000     /* Receive config */
-#define E1000_RXCW_SYNCH 0x40000000     /* Receive config synch */
-#define E1000_RXCW_ANC   0x80000000     /* Auto-neg complete */
+#define E1000_RXCW_CW    0x0000ffff    /* RxConfigWord mask */
+#define E1000_RXCW_NC    0x04000000    /* Receive config no carrier */
+#define E1000_RXCW_IV    0x08000000    /* Receive config invalid */
+#define E1000_RXCW_CC    0x10000000    /* Receive config change */
+#define E1000_RXCW_C     0x20000000    /* Receive config */
+#define E1000_RXCW_SYNCH 0x40000000    /* Receive config synch */
+#define E1000_RXCW_ANC   0x80000000    /* Auto-neg complete */
 
 /* Transmit Control */
-#define E1000_TCTL_RST    0x00000001    /* software reset */
-#define E1000_TCTL_EN     0x00000002    /* enable tx */
-#define E1000_TCTL_BCE    0x00000004    /* busy check enable */
-#define E1000_TCTL_PSP    0x00000008    /* pad short packets */
-#define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
-#define E1000_TCTL_COLD   0x003ff000    /* collision distance */
-#define E1000_TCTL_SWXOFF 0x00400000    /* SW Xoff transmission */
-#define E1000_TCTL_PBE    0x00800000    /* Packet Burst Enable */
-#define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
-#define E1000_TCTL_NRTU   0x02000000    /* No Re-transmit on underrun */
-#define E1000_TCTL_MULR   0x10000000    /* Multiple request support */
+#define E1000_TCTL_RST    0x00000001   /* software reset */
+#define E1000_TCTL_EN     0x00000002   /* enable tx */
+#define E1000_TCTL_BCE    0x00000004   /* busy check enable */
+#define E1000_TCTL_PSP    0x00000008   /* pad short packets */
+#define E1000_TCTL_CT     0x00000ff0   /* collision threshold */
+#define E1000_TCTL_COLD   0x003ff000   /* collision distance */
+#define E1000_TCTL_SWXOFF 0x00400000   /* SW Xoff transmission */
+#define E1000_TCTL_PBE    0x00800000   /* Packet Burst Enable */
+#define E1000_TCTL_RTLC   0x01000000   /* Re-transmit on late collision */
+#define E1000_TCTL_NRTU   0x02000000   /* No Re-transmit on underrun */
+#define E1000_TCTL_MULR   0x10000000   /* Multiple request support */
 /* Extended Transmit Control */
-#define E1000_TCTL_EXT_BST_MASK  0x000003FF /* Backoff Slot Time */
-#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
+#define E1000_TCTL_EXT_BST_MASK  0x000003FF    /* Backoff Slot Time */
+#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00    /* Gigabit Carry Extend Padding */
 
 /* Receive Checksum Control */
-#define E1000_RXCSUM_PCSS_MASK 0x000000FF   /* Packet Checksum Start */
-#define E1000_RXCSUM_IPOFL     0x00000100   /* IPv4 checksum offload */
-#define E1000_RXCSUM_TUOFL     0x00000200   /* TCP / UDP checksum offload */
-#define E1000_RXCSUM_IPV6OFL   0x00000400   /* IPv6 checksum offload */
-#define E1000_RXCSUM_IPPCSE    0x00001000   /* IP payload checksum enable */
-#define E1000_RXCSUM_PCSD      0x00002000   /* packet checksum disabled */
+#define E1000_RXCSUM_PCSS_MASK 0x000000FF      /* Packet Checksum Start */
+#define E1000_RXCSUM_IPOFL     0x00000100      /* IPv4 checksum offload */
+#define E1000_RXCSUM_TUOFL     0x00000200      /* TCP / UDP checksum offload */
+#define E1000_RXCSUM_IPV6OFL   0x00000400      /* IPv6 checksum offload */
+#define E1000_RXCSUM_IPPCSE    0x00001000      /* IP payload checksum enable */
+#define E1000_RXCSUM_PCSD      0x00002000      /* packet checksum disabled */
 
 /* Multiple Receive Queue Control */
 #define E1000_MRQC_ENABLE_MASK              0x00000003
@@ -1962,141 +1956,141 @@ struct e1000_hw {
 
 /* Definitions for power management and wakeup registers */
 /* Wake Up Control */
-#define E1000_WUC_APME       0x00000001 /* APM Enable */
-#define E1000_WUC_PME_EN     0x00000002 /* PME Enable */
-#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
-#define E1000_WUC_APMPME     0x00000008 /* Assert PME on APM Wakeup */
-#define E1000_WUC_SPM        0x80000000 /* Enable SPM */
+#define E1000_WUC_APME       0x00000001        /* APM Enable */
+#define E1000_WUC_PME_EN     0x00000002        /* PME Enable */
+#define E1000_WUC_PME_STATUS 0x00000004        /* PME Status */
+#define E1000_WUC_APMPME     0x00000008        /* Assert PME on APM Wakeup */
+#define E1000_WUC_SPM        0x80000000        /* Enable SPM */
 
 /* Wake Up Filter Control */
-#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
-#define E1000_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
-#define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
-#define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
-#define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
-#define E1000_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
-#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
-#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
-#define E1000_WUFC_IGNORE_TCO      0x00008000 /* Ignore WakeOn TCO packets */
-#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
-#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
-#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
-#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
-#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
-#define E1000_WUFC_FLX_OFFSET 16       /* Offset to the Flexible Filters bits */
-#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
+#define E1000_WUFC_LNKC 0x00000001     /* Link Status Change Wakeup Enable */
+#define E1000_WUFC_MAG  0x00000002     /* Magic Packet Wakeup Enable */
+#define E1000_WUFC_EX   0x00000004     /* Directed Exact Wakeup Enable */
+#define E1000_WUFC_MC   0x00000008     /* Directed Multicast Wakeup Enable */
+#define E1000_WUFC_BC   0x00000010     /* Broadcast Wakeup Enable */
+#define E1000_WUFC_ARP  0x00000020     /* ARP Request Packet Wakeup Enable */
+#define E1000_WUFC_IPV4 0x00000040     /* Directed IPv4 Packet Wakeup Enable */
+#define E1000_WUFC_IPV6 0x00000080     /* Directed IPv6 Packet Wakeup Enable */
+#define E1000_WUFC_IGNORE_TCO      0x00008000  /* Ignore WakeOn TCO packets */
+#define E1000_WUFC_FLX0 0x00010000     /* Flexible Filter 0 Enable */
+#define E1000_WUFC_FLX1 0x00020000     /* Flexible Filter 1 Enable */
+#define E1000_WUFC_FLX2 0x00040000     /* Flexible Filter 2 Enable */
+#define E1000_WUFC_FLX3 0x00080000     /* Flexible Filter 3 Enable */
+#define E1000_WUFC_ALL_FILTERS 0x000F00FF      /* Mask for all wakeup filters */
+#define E1000_WUFC_FLX_OFFSET 16       /* Offset to the Flexible Filters bits */
+#define E1000_WUFC_FLX_FILTERS 0x000F0000      /* Mask for the 4 flexible filters */
 
 /* Wake Up Status */
-#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
-#define E1000_WUS_MAG  0x00000002 /* Magic Packet Received */
-#define E1000_WUS_EX   0x00000004 /* Directed Exact Received */
-#define E1000_WUS_MC   0x00000008 /* Directed Multicast Received */
-#define E1000_WUS_BC   0x00000010 /* Broadcast Received */
-#define E1000_WUS_ARP  0x00000020 /* ARP Request Packet Received */
-#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
-#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
-#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
-#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
-#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
-#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
-#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
+#define E1000_WUS_LNKC 0x00000001      /* Link Status Changed */
+#define E1000_WUS_MAG  0x00000002      /* Magic Packet Received */
+#define E1000_WUS_EX   0x00000004      /* Directed Exact Received */
+#define E1000_WUS_MC   0x00000008      /* Directed Multicast Received */
+#define E1000_WUS_BC   0x00000010      /* Broadcast Received */
+#define E1000_WUS_ARP  0x00000020      /* ARP Request Packet Received */
+#define E1000_WUS_IPV4 0x00000040      /* Directed IPv4 Packet Wakeup Received */
+#define E1000_WUS_IPV6 0x00000080      /* Directed IPv6 Packet Wakeup Received */
+#define E1000_WUS_FLX0 0x00010000      /* Flexible Filter 0 Match */
+#define E1000_WUS_FLX1 0x00020000      /* Flexible Filter 1 Match */
+#define E1000_WUS_FLX2 0x00040000      /* Flexible Filter 2 Match */
+#define E1000_WUS_FLX3 0x00080000      /* Flexible Filter 3 Match */
+#define E1000_WUS_FLX_FILTERS 0x000F0000       /* Mask for the 4 flexible filters */
 
 /* Management Control */
-#define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
-#define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
-#define E1000_MANC_R_ON_FORCE    0x00000004 /* Reset on Force TCO - RO */
-#define E1000_MANC_RMCP_EN       0x00000100 /* Enable RCMP 026Fh Filtering */
-#define E1000_MANC_0298_EN       0x00000200 /* Enable RCMP 0298h Filtering */
-#define E1000_MANC_IPV4_EN       0x00000400 /* Enable IPv4 */
-#define E1000_MANC_IPV6_EN       0x00000800 /* Enable IPv6 */
-#define E1000_MANC_SNAP_EN       0x00001000 /* Accept LLC/SNAP */
-#define E1000_MANC_ARP_EN        0x00002000 /* Enable ARP Request Filtering */
-#define E1000_MANC_NEIGHBOR_EN   0x00004000 /* Enable Neighbor Discovery
-                                             * Filtering */
-#define E1000_MANC_ARP_RES_EN    0x00008000 /* Enable ARP response Filtering */
-#define E1000_MANC_TCO_RESET     0x00010000 /* TCO Reset Occurred */
-#define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */
-#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
-#define E1000_MANC_RCV_ALL       0x00080000 /* Receive All Enabled */
-#define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */
-#define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000 /* Enable MAC address
-                                                    * filtering */
-#define E1000_MANC_EN_MNG2HOST   0x00200000 /* Enable MNG packets to host
-                                             * memory */
-#define E1000_MANC_EN_IP_ADDR_FILTER    0x00400000 /* Enable IP address
-                                                    * filtering */
-#define E1000_MANC_EN_XSUM_FILTER   0x00800000 /* Enable checksum filtering */
-#define E1000_MANC_BR_EN         0x01000000 /* Enable broadcast filtering */
-#define E1000_MANC_SMB_REQ       0x01000000 /* SMBus Request */
-#define E1000_MANC_SMB_GNT       0x02000000 /* SMBus Grant */
-#define E1000_MANC_SMB_CLK_IN    0x04000000 /* SMBus Clock In */
-#define E1000_MANC_SMB_DATA_IN   0x08000000 /* SMBus Data In */
-#define E1000_MANC_SMB_DATA_OUT  0x10000000 /* SMBus Data Out */
-#define E1000_MANC_SMB_CLK_OUT   0x20000000 /* SMBus Clock Out */
-
-#define E1000_MANC_SMB_DATA_OUT_SHIFT  28 /* SMBus Data Out Shift */
-#define E1000_MANC_SMB_CLK_OUT_SHIFT   29 /* SMBus Clock Out Shift */
+#define E1000_MANC_SMBUS_EN      0x00000001    /* SMBus Enabled - RO */
+#define E1000_MANC_ASF_EN        0x00000002    /* ASF Enabled - RO */
+#define E1000_MANC_R_ON_FORCE    0x00000004    /* Reset on Force TCO - RO */
+#define E1000_MANC_RMCP_EN       0x00000100    /* Enable RCMP 026Fh Filtering */
+#define E1000_MANC_0298_EN       0x00000200    /* Enable RCMP 0298h Filtering */
+#define E1000_MANC_IPV4_EN       0x00000400    /* Enable IPv4 */
+#define E1000_MANC_IPV6_EN       0x00000800    /* Enable IPv6 */
+#define E1000_MANC_SNAP_EN       0x00001000    /* Accept LLC/SNAP */
+#define E1000_MANC_ARP_EN        0x00002000    /* Enable ARP Request Filtering */
+#define E1000_MANC_NEIGHBOR_EN   0x00004000    /* Enable Neighbor Discovery
+                                                * Filtering */
+#define E1000_MANC_ARP_RES_EN    0x00008000    /* Enable ARP response Filtering */
+#define E1000_MANC_TCO_RESET     0x00010000    /* TCO Reset Occurred */
+#define E1000_MANC_RCV_TCO_EN    0x00020000    /* Receive TCO Packets Enabled */
+#define E1000_MANC_REPORT_STATUS 0x00040000    /* Status Reporting Enabled */
+#define E1000_MANC_RCV_ALL       0x00080000    /* Receive All Enabled */
+#define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000     /* Block phy resets */
+#define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000     /* Enable MAC address
+                                                        * filtering */
+#define E1000_MANC_EN_MNG2HOST   0x00200000    /* Enable MNG packets to host
+                                                * memory */
+#define E1000_MANC_EN_IP_ADDR_FILTER    0x00400000     /* Enable IP address
+                                                        * filtering */
+#define E1000_MANC_EN_XSUM_FILTER   0x00800000 /* Enable checksum filtering */
+#define E1000_MANC_BR_EN         0x01000000    /* Enable broadcast filtering */
+#define E1000_MANC_SMB_REQ       0x01000000    /* SMBus Request */
+#define E1000_MANC_SMB_GNT       0x02000000    /* SMBus Grant */
+#define E1000_MANC_SMB_CLK_IN    0x04000000    /* SMBus Clock In */
+#define E1000_MANC_SMB_DATA_IN   0x08000000    /* SMBus Data In */
+#define E1000_MANC_SMB_DATA_OUT  0x10000000    /* SMBus Data Out */
+#define E1000_MANC_SMB_CLK_OUT   0x20000000    /* SMBus Clock Out */
+
+#define E1000_MANC_SMB_DATA_OUT_SHIFT  28      /* SMBus Data Out Shift */
+#define E1000_MANC_SMB_CLK_OUT_SHIFT   29      /* SMBus Clock Out Shift */
 
 /* SW Semaphore Register */
-#define E1000_SWSM_SMBI         0x00000001 /* Driver Semaphore bit */
-#define E1000_SWSM_SWESMBI      0x00000002 /* FW Semaphore bit */
-#define E1000_SWSM_WMNG         0x00000004 /* Wake MNG Clock */
-#define E1000_SWSM_DRV_LOAD     0x00000008 /* Driver Loaded Bit */
+#define E1000_SWSM_SMBI         0x00000001     /* Driver Semaphore bit */
+#define E1000_SWSM_SWESMBI      0x00000002     /* FW Semaphore bit */
+#define E1000_SWSM_WMNG         0x00000004     /* Wake MNG Clock */
+#define E1000_SWSM_DRV_LOAD     0x00000008     /* Driver Loaded Bit */
 
 /* FW Semaphore Register */
-#define E1000_FWSM_MODE_MASK    0x0000000E /* FW mode */
+#define E1000_FWSM_MODE_MASK    0x0000000E     /* FW mode */
 #define E1000_FWSM_MODE_SHIFT            1
-#define E1000_FWSM_FW_VALID     0x00008000 /* FW established a valid mode */
+#define E1000_FWSM_FW_VALID     0x00008000     /* FW established a valid mode */
 
-#define E1000_FWSM_RSPCIPHY        0x00000040 /* Reset PHY on PCI reset */
-#define E1000_FWSM_DISSW           0x10000000 /* FW disable SW Write Access */
-#define E1000_FWSM_SKUSEL_MASK     0x60000000 /* LAN SKU select */
+#define E1000_FWSM_RSPCIPHY        0x00000040  /* Reset PHY on PCI reset */
+#define E1000_FWSM_DISSW           0x10000000  /* FW disable SW Write Access */
+#define E1000_FWSM_SKUSEL_MASK     0x60000000  /* LAN SKU select */
 #define E1000_FWSM_SKUEL_SHIFT     29
-#define E1000_FWSM_SKUSEL_EMB      0x0 /* Embedded SKU */
-#define E1000_FWSM_SKUSEL_CONS     0x1 /* Consumer SKU */
-#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */
-#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */
+#define E1000_FWSM_SKUSEL_EMB      0x0 /* Embedded SKU */
+#define E1000_FWSM_SKUSEL_CONS     0x1 /* Consumer SKU */
+#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */
+#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */
 
 /* FFLT Debug Register */
-#define E1000_FFLT_DBG_INVC     0x00100000 /* Invalid /C/ code handling */
+#define E1000_FFLT_DBG_INVC     0x00100000     /* Invalid /C/ code handling */
 
 typedef enum {
-    e1000_mng_mode_none     = 0,
-    e1000_mng_mode_asf,
-    e1000_mng_mode_pt,
-    e1000_mng_mode_ipmi,
-    e1000_mng_mode_host_interface_only
+       e1000_mng_mode_none = 0,
+       e1000_mng_mode_asf,
+       e1000_mng_mode_pt,
+       e1000_mng_mode_ipmi,
+       e1000_mng_mode_host_interface_only
 } e1000_mng_mode;
 
-/* Host Inteface Control Register */
-#define E1000_HICR_EN           0x00000001  /* Enable Bit - RO */
-#define E1000_HICR_C            0x00000002  /* Driver sets this bit when done
-                                             * to put command in RAM */
-#define E1000_HICR_SV           0x00000004  /* Status Validity */
-#define E1000_HICR_FWR          0x00000080  /* FW reset. Set by the Host */
+/* Host Interface Control Register */
+#define E1000_HICR_EN           0x00000001     /* Enable Bit - RO */
+#define E1000_HICR_C            0x00000002     /* Driver sets this bit when done
+                                                * to put command in RAM */
+#define E1000_HICR_SV           0x00000004     /* Status Validity */
+#define E1000_HICR_FWR          0x00000080     /* FW reset. Set by the Host */
 
 /* Host Interface Command Interface - Address range 0x8800-0x8EFF */
-#define E1000_HI_MAX_DATA_LENGTH         252 /* Host Interface data length */
-#define E1000_HI_MAX_BLOCK_BYTE_LENGTH  1792 /* Number of bytes in range */
-#define E1000_HI_MAX_BLOCK_DWORD_LENGTH  448 /* Number of dwords in range */
-#define E1000_HI_COMMAND_TIMEOUT         500 /* Time in ms to process HI command */
+#define E1000_HI_MAX_DATA_LENGTH         252   /* Host Interface data length */
+#define E1000_HI_MAX_BLOCK_BYTE_LENGTH  1792   /* Number of bytes in range */
+#define E1000_HI_MAX_BLOCK_DWORD_LENGTH  448   /* Number of dwords in range */
+#define E1000_HI_COMMAND_TIMEOUT         500   /* Time in ms to process HI command */
 
 struct e1000_host_command_header {
-    u8 command_id;
-    u8 command_length;
-    u8 command_options;   /* I/F bits for command, status for return */
-    u8 checksum;
+       u8 command_id;
+       u8 command_length;
+       u8 command_options;     /* I/F bits for command, status for return */
+       u8 checksum;
 };
 struct e1000_host_command_info {
-    struct e1000_host_command_header command_header;  /* Command Head/Command Result Head has 4 bytes */
-    u8 command_data[E1000_HI_MAX_DATA_LENGTH];   /* Command data can length 0..252 */
+       struct e1000_host_command_header command_header;        /* Command Head/Command Result Head has 4 bytes */
+       u8 command_data[E1000_HI_MAX_DATA_LENGTH];      /* Command data can length 0..252 */
 };
 
 /* Host SMB register #0 */
-#define E1000_HSMC0R_CLKIN      0x00000001  /* SMB Clock in */
-#define E1000_HSMC0R_DATAIN     0x00000002  /* SMB Data in */
-#define E1000_HSMC0R_DATAOUT    0x00000004  /* SMB Data out */
-#define E1000_HSMC0R_CLKOUT     0x00000008  /* SMB Clock out */
+#define E1000_HSMC0R_CLKIN      0x00000001     /* SMB Clock in */
+#define E1000_HSMC0R_DATAIN     0x00000002     /* SMB Data in */
+#define E1000_HSMC0R_DATAOUT    0x00000004     /* SMB Data out */
+#define E1000_HSMC0R_CLKOUT     0x00000008     /* SMB Clock out */
 
 /* Host SMB register #1 */
 #define E1000_HSMC1R_CLKIN      E1000_HSMC0R_CLKIN
@@ -2105,10 +2099,10 @@ struct e1000_host_command_info {
 #define E1000_HSMC1R_CLKOUT     E1000_HSMC0R_CLKOUT
 
 /* FW Status Register */
-#define E1000_FWSTS_FWS_MASK    0x000000FF  /* FW Status */
+#define E1000_FWSTS_FWS_MASK    0x000000FF     /* FW Status */
 
 /* Wake Up Packet Length */
-#define E1000_WUPL_LENGTH_MASK 0x0FFF   /* Only the lower 12 bits are valid */
+#define E1000_WUPL_LENGTH_MASK 0x0FFF  /* Only the lower 12 bits are valid */
 
 #define E1000_MDALIGN          4096
 
@@ -2162,24 +2156,24 @@ struct e1000_host_command_info {
 #define PCI_EX_LINK_WIDTH_SHIFT      4
 
 /* EEPROM Commands - Microwire */
-#define EEPROM_READ_OPCODE_MICROWIRE  0x6  /* EEPROM read opcode */
-#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5  /* EEPROM write opcode */
-#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7  /* EEPROM erase opcode */
-#define EEPROM_EWEN_OPCODE_MICROWIRE  0x13 /* EEPROM erase/write enable */
-#define EEPROM_EWDS_OPCODE_MICROWIRE  0x10 /* EEPROM erast/write disable */
+#define EEPROM_READ_OPCODE_MICROWIRE  0x6      /* EEPROM read opcode */
+#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5      /* EEPROM write opcode */
+#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7      /* EEPROM erase opcode */
+#define EEPROM_EWEN_OPCODE_MICROWIRE  0x13     /* EEPROM erase/write enable */
+#define EEPROM_EWDS_OPCODE_MICROWIRE  0x10     /* EEPROM erase/write disable */
 
 /* EEPROM Commands - SPI */
-#define EEPROM_MAX_RETRY_SPI        5000 /* Max wait of 5ms, for RDY signal */
-#define EEPROM_READ_OPCODE_SPI      0x03  /* EEPROM read opcode */
-#define EEPROM_WRITE_OPCODE_SPI     0x02  /* EEPROM write opcode */
-#define EEPROM_A8_OPCODE_SPI        0x08  /* opcode bit-3 = address bit-8 */
-#define EEPROM_WREN_OPCODE_SPI      0x06  /* EEPROM set Write Enable latch */
-#define EEPROM_WRDI_OPCODE_SPI      0x04  /* EEPROM reset Write Enable latch */
-#define EEPROM_RDSR_OPCODE_SPI      0x05  /* EEPROM read Status register */
-#define EEPROM_WRSR_OPCODE_SPI      0x01  /* EEPROM write Status register */
-#define EEPROM_ERASE4K_OPCODE_SPI   0x20  /* EEPROM ERASE 4KB */
-#define EEPROM_ERASE64K_OPCODE_SPI  0xD8  /* EEPROM ERASE 64KB */
-#define EEPROM_ERASE256_OPCODE_SPI  0xDB  /* EEPROM ERASE 256B */
+#define EEPROM_MAX_RETRY_SPI        5000       /* Max wait of 5ms, for RDY signal */
+#define EEPROM_READ_OPCODE_SPI      0x03       /* EEPROM read opcode */
+#define EEPROM_WRITE_OPCODE_SPI     0x02       /* EEPROM write opcode */
+#define EEPROM_A8_OPCODE_SPI        0x08       /* opcode bit-3 = address bit-8 */
+#define EEPROM_WREN_OPCODE_SPI      0x06       /* EEPROM set Write Enable latch */
+#define EEPROM_WRDI_OPCODE_SPI      0x04       /* EEPROM reset Write Enable latch */
+#define EEPROM_RDSR_OPCODE_SPI      0x05       /* EEPROM read Status register */
+#define EEPROM_WRSR_OPCODE_SPI      0x01       /* EEPROM write Status register */
+#define EEPROM_ERASE4K_OPCODE_SPI   0x20       /* EEPROM ERASE 4KB */
+#define EEPROM_ERASE64K_OPCODE_SPI  0xD8       /* EEPROM ERASE 64KB */
+#define EEPROM_ERASE256_OPCODE_SPI  0xDB       /* EEPROM ERASE 256B */
 
 /* EEPROM Size definitions */
 #define EEPROM_WORD_SIZE_SHIFT  6
@@ -2190,7 +2184,7 @@ struct e1000_host_command_info {
 #define EEPROM_COMPAT                 0x0003
 #define EEPROM_ID_LED_SETTINGS        0x0004
 #define EEPROM_VERSION                0x0005
-#define EEPROM_SERDES_AMPLITUDE       0x0006 /* For SERDES output amplitude adjustment. */
+#define EEPROM_SERDES_AMPLITUDE       0x0006   /* For SERDES output amplitude adjustment. */
 #define EEPROM_PHY_CLASS_WORD         0x0007
 #define EEPROM_INIT_CONTROL1_REG      0x000A
 #define EEPROM_INIT_CONTROL2_REG      0x000F
@@ -2203,8 +2197,8 @@ struct e1000_host_command_info {
 #define EEPROM_FLASH_VERSION          0x0032
 #define EEPROM_CHECKSUM_REG           0x003F
 
-#define E1000_EEPROM_CFG_DONE         0x00040000   /* MNG config cycle done */
-#define E1000_EEPROM_CFG_DONE_PORT_1  0x00080000   /* ...for second port */
+#define E1000_EEPROM_CFG_DONE         0x00040000       /* MNG config cycle done */
+#define E1000_EEPROM_CFG_DONE_PORT_1  0x00080000       /* ...for second port */
 
 /* Word definitions for ID LED Settings */
 #define ID_LED_RESERVED_0000 0x0000
@@ -2227,7 +2221,6 @@ struct e1000_host_command_info {
 #define IGP_ACTIVITY_LED_ENABLE 0x0300
 #define IGP_LED3_MODE           0x07000000
 
-
 /* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
 #define EEPROM_SERDES_AMPLITUDE_MASK  0x000F
 
@@ -2332,9 +2325,9 @@ struct e1000_host_command_info {
 #define E1000_EXTCNF_CTRL_SWFLAG            0x00000020
 
 /* PBA constants */
-#define E1000_PBA_8K 0x0008    /* 8KB, default Rx allocation */
-#define E1000_PBA_12K 0x000C    /* 12KB, default Rx allocation */
-#define E1000_PBA_16K 0x0010    /* 16KB, default TX allocation */
+#define E1000_PBA_8K 0x0008    /* 8KB, default Rx allocation */
+#define E1000_PBA_12K 0x000C   /* 12KB, default Rx allocation */
+#define E1000_PBA_16K 0x0010   /* 16KB, default TX allocation */
 #define E1000_PBA_20K 0x0014
 #define E1000_PBA_22K 0x0016
 #define E1000_PBA_24K 0x0018
@@ -2343,7 +2336,7 @@ struct e1000_host_command_info {
 #define E1000_PBA_34K 0x0022
 #define E1000_PBA_38K 0x0026
 #define E1000_PBA_40K 0x0028
-#define E1000_PBA_48K 0x0030    /* 48KB, default RX allocation */
+#define E1000_PBA_48K 0x0030   /* 48KB, default RX allocation */
 
 #define E1000_PBS_16K E1000_PBA_16K
 
@@ -2353,9 +2346,9 @@ struct e1000_host_command_info {
 #define FLOW_CONTROL_TYPE         0x8808
 
 /* The historical defaults for the flow control values are given below. */
-#define FC_DEFAULT_HI_THRESH        (0x8000)    /* 32KB */
-#define FC_DEFAULT_LO_THRESH        (0x4000)    /* 16KB */
-#define FC_DEFAULT_TX_TIMER         (0x100)     /* ~130 us */
+#define FC_DEFAULT_HI_THRESH        (0x8000)   /* 32KB */
+#define FC_DEFAULT_LO_THRESH        (0x4000)   /* 16KB */
+#define FC_DEFAULT_TX_TIMER         (0x100)    /* ~130 us */
 
 /* PCIX Config space */
 #define PCIX_COMMAND_REGISTER    0xE6
@@ -2369,7 +2362,6 @@ struct e1000_host_command_info {
 #define PCIX_STATUS_HI_MMRBC_4K      0x3
 #define PCIX_STATUS_HI_MMRBC_2K      0x2
 
-
 /* Number of bits required to shift right the "pause" bits from the
  * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
  */
@@ -2390,7 +2382,6 @@ struct e1000_host_command_info {
  */
 #define ILOS_SHIFT  3
 
-
 #define RECEIVE_BUFFER_ALIGN_SIZE  (256)
 
 /* Number of milliseconds we wait for auto-negotiation to complete */
@@ -2443,7 +2434,6 @@ struct e1000_host_command_info {
           (((length) > (adapter)->min_frame_size) && \
            ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
 
-
 /* Structures, enums, and macros for the PHY */
 
 /* Bit definitions for the Management Data IO (MDIO) and Management Data
@@ -2460,49 +2450,49 @@ struct e1000_host_command_info {
 
 /* PHY 1000 MII Register/Bit Definitions */
 /* PHY Registers defined by IEEE */
-#define PHY_CTRL         0x00 /* Control Register */
-#define PHY_STATUS       0x01 /* Status Regiser */
-#define PHY_ID1          0x02 /* Phy Id Reg (word 1) */
-#define PHY_ID2          0x03 /* Phy Id Reg (word 2) */
-#define PHY_AUTONEG_ADV  0x04 /* Autoneg Advertisement */
-#define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
-#define PHY_AUTONEG_EXP  0x06 /* Autoneg Expansion Reg */
-#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
-#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
-#define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
-#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
-#define PHY_EXT_STATUS   0x0F /* Extended Status Reg */
-
-#define MAX_PHY_REG_ADDRESS        0x1F  /* 5 bit address bus (0-0x1F) */
-#define MAX_PHY_MULTI_PAGE_REG     0xF   /* Registers equal on all pages */
+#define PHY_CTRL         0x00  /* Control Register */
+#define PHY_STATUS       0x01  /* Status Register */
+#define PHY_ID1          0x02  /* Phy Id Reg (word 1) */
+#define PHY_ID2          0x03  /* Phy Id Reg (word 2) */
+#define PHY_AUTONEG_ADV  0x04  /* Autoneg Advertisement */
+#define PHY_LP_ABILITY   0x05  /* Link Partner Ability (Base Page) */
+#define PHY_AUTONEG_EXP  0x06  /* Autoneg Expansion Reg */
+#define PHY_NEXT_PAGE_TX 0x07  /* Next Page TX */
+#define PHY_LP_NEXT_PAGE 0x08  /* Link Partner Next Page */
+#define PHY_1000T_CTRL   0x09  /* 1000Base-T Control Reg */
+#define PHY_1000T_STATUS 0x0A  /* 1000Base-T Status Reg */
+#define PHY_EXT_STATUS   0x0F  /* Extended Status Reg */
+
+#define MAX_PHY_REG_ADDRESS        0x1F        /* 5 bit address bus (0-0x1F) */
+#define MAX_PHY_MULTI_PAGE_REG     0xF /* Registers equal on all pages */
 
 /* M88E1000 Specific Registers */
-#define M88E1000_PHY_SPEC_CTRL     0x10  /* PHY Specific Control Register */
-#define M88E1000_PHY_SPEC_STATUS   0x11  /* PHY Specific Status Register */
-#define M88E1000_INT_ENABLE        0x12  /* Interrupt Enable Register */
-#define M88E1000_INT_STATUS        0x13  /* Interrupt Status Register */
-#define M88E1000_EXT_PHY_SPEC_CTRL 0x14  /* Extended PHY Specific Control */
-#define M88E1000_RX_ERR_CNTR       0x15  /* Receive Error Counter */
-
-#define M88E1000_PHY_EXT_CTRL      0x1A  /* PHY extend control register */
-#define M88E1000_PHY_PAGE_SELECT   0x1D  /* Reg 29 for page number setting */
-#define M88E1000_PHY_GEN_CONTROL   0x1E  /* Its meaning depends on reg 29 */
-#define M88E1000_PHY_VCO_REG_BIT8  0x100 /* Bits 8 & 11 are adjusted for */
-#define M88E1000_PHY_VCO_REG_BIT11 0x800    /* improved BER performance */
+#define M88E1000_PHY_SPEC_CTRL     0x10        /* PHY Specific Control Register */
+#define M88E1000_PHY_SPEC_STATUS   0x11        /* PHY Specific Status Register */
+#define M88E1000_INT_ENABLE        0x12        /* Interrupt Enable Register */
+#define M88E1000_INT_STATUS        0x13        /* Interrupt Status Register */
+#define M88E1000_EXT_PHY_SPEC_CTRL 0x14        /* Extended PHY Specific Control */
+#define M88E1000_RX_ERR_CNTR       0x15        /* Receive Error Counter */
+
+#define M88E1000_PHY_EXT_CTRL      0x1A        /* PHY extend control register */
+#define M88E1000_PHY_PAGE_SELECT   0x1D        /* Reg 29 for page number setting */
+#define M88E1000_PHY_GEN_CONTROL   0x1E        /* Its meaning depends on reg 29 */
+#define M88E1000_PHY_VCO_REG_BIT8  0x100       /* Bits 8 & 11 are adjusted for */
+#define M88E1000_PHY_VCO_REG_BIT11 0x800       /* improved BER performance */
 
 #define IGP01E1000_IEEE_REGS_PAGE  0x0000
 #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
 #define IGP01E1000_IEEE_FORCE_GIGA      0x0140
 
 /* IGP01E1000 Specific Registers */
-#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
-#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
-#define IGP01E1000_PHY_PORT_CTRL   0x12 /* PHY Specific Control Register */
-#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
-#define IGP01E1000_GMII_FIFO       0x14 /* GMII FIFO Register */
-#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
+#define IGP01E1000_PHY_PORT_CONFIG 0x10        /* PHY Specific Port Config Register */
+#define IGP01E1000_PHY_PORT_STATUS 0x11        /* PHY Specific Status Register */
+#define IGP01E1000_PHY_PORT_CTRL   0x12        /* PHY Specific Control Register */
+#define IGP01E1000_PHY_LINK_HEALTH 0x13        /* PHY Link Health Register */
+#define IGP01E1000_GMII_FIFO       0x14        /* GMII FIFO Register */
+#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15    /* PHY Channel Quality Register */
 #define IGP02E1000_PHY_POWER_MGMT      0x19
-#define IGP01E1000_PHY_PAGE_SELECT     0x1F /* PHY Page Select Core Register */
+#define IGP01E1000_PHY_PAGE_SELECT     0x1F    /* PHY Page Select Core Register */
 
 /* IGP01E1000 AGC Registers - stores the cable length values*/
 #define IGP01E1000_PHY_AGC_A        0x1172
@@ -2546,118 +2536,118 @@ struct e1000_host_command_info {
 #define IGP01E1000_ANALOG_REGS_PAGE  0x20C0
 
 /* PHY Control Register */
-#define MII_CR_SPEED_SELECT_MSB 0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */
-#define MII_CR_COLL_TEST_ENABLE 0x0080  /* Collision test enable */
-#define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
-#define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
-#define MII_CR_ISOLATE          0x0400  /* Isolate PHY from MII */
-#define MII_CR_POWER_DOWN       0x0800  /* Power down */
-#define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
-#define MII_CR_SPEED_SELECT_LSB 0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */
-#define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
-#define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
+#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
+#define MII_CR_FULL_DUPLEX      0x0100 /* FDX =1, half duplex =0 */
+#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
+#define MII_CR_ISOLATE          0x0400 /* Isolate PHY from MII */
+#define MII_CR_POWER_DOWN       0x0800 /* Power down */
+#define MII_CR_AUTO_NEG_EN      0x1000 /* Auto Neg Enable */
+#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define MII_CR_LOOPBACK         0x4000 /* 0 = normal, 1 = loopback */
+#define MII_CR_RESET            0x8000 /* 0 = normal, 1 = PHY reset */
 
 /* PHY Status Register */
-#define MII_SR_EXTENDED_CAPS     0x0001 /* Extended register capabilities */
-#define MII_SR_JABBER_DETECT     0x0002 /* Jabber Detected */
-#define MII_SR_LINK_STATUS       0x0004 /* Link Status 1 = link */
-#define MII_SR_AUTONEG_CAPS      0x0008 /* Auto Neg Capable */
-#define MII_SR_REMOTE_FAULT      0x0010 /* Remote Fault Detect */
-#define MII_SR_AUTONEG_COMPLETE  0x0020 /* Auto Neg Complete */
-#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
-#define MII_SR_EXTENDED_STATUS   0x0100 /* Ext. status info in Reg 0x0F */
-#define MII_SR_100T2_HD_CAPS     0x0200 /* 100T2 Half Duplex Capable */
-#define MII_SR_100T2_FD_CAPS     0x0400 /* 100T2 Full Duplex Capable */
-#define MII_SR_10T_HD_CAPS       0x0800 /* 10T   Half Duplex Capable */
-#define MII_SR_10T_FD_CAPS       0x1000 /* 10T   Full Duplex Capable */
-#define MII_SR_100X_HD_CAPS      0x2000 /* 100X  Half Duplex Capable */
-#define MII_SR_100X_FD_CAPS      0x4000 /* 100X  Full Duplex Capable */
-#define MII_SR_100T4_CAPS        0x8000 /* 100T4 Capable */
+#define MII_SR_EXTENDED_CAPS     0x0001        /* Extended register capabilities */
+#define MII_SR_JABBER_DETECT     0x0002        /* Jabber Detected */
+#define MII_SR_LINK_STATUS       0x0004        /* Link Status 1 = link */
+#define MII_SR_AUTONEG_CAPS      0x0008        /* Auto Neg Capable */
+#define MII_SR_REMOTE_FAULT      0x0010        /* Remote Fault Detect */
+#define MII_SR_AUTONEG_COMPLETE  0x0020        /* Auto Neg Complete */
+#define MII_SR_PREAMBLE_SUPPRESS 0x0040        /* Preamble may be suppressed */
+#define MII_SR_EXTENDED_STATUS   0x0100        /* Ext. status info in Reg 0x0F */
+#define MII_SR_100T2_HD_CAPS     0x0200        /* 100T2 Half Duplex Capable */
+#define MII_SR_100T2_FD_CAPS     0x0400        /* 100T2 Full Duplex Capable */
+#define MII_SR_10T_HD_CAPS       0x0800        /* 10T   Half Duplex Capable */
+#define MII_SR_10T_FD_CAPS       0x1000        /* 10T   Full Duplex Capable */
+#define MII_SR_100X_HD_CAPS      0x2000        /* 100X  Half Duplex Capable */
+#define MII_SR_100X_FD_CAPS      0x4000        /* 100X  Full Duplex Capable */
+#define MII_SR_100T4_CAPS        0x8000        /* 100T4 Capable */
 
 /* Autoneg Advertisement Register */
-#define NWAY_AR_SELECTOR_FIELD 0x0001   /* indicates IEEE 802.3 CSMA/CD */
-#define NWAY_AR_10T_HD_CAPS    0x0020   /* 10T   Half Duplex Capable */
-#define NWAY_AR_10T_FD_CAPS    0x0040   /* 10T   Full Duplex Capable */
-#define NWAY_AR_100TX_HD_CAPS  0x0080   /* 100TX Half Duplex Capable */
-#define NWAY_AR_100TX_FD_CAPS  0x0100   /* 100TX Full Duplex Capable */
-#define NWAY_AR_100T4_CAPS     0x0200   /* 100T4 Capable */
-#define NWAY_AR_PAUSE          0x0400   /* Pause operation desired */
-#define NWAY_AR_ASM_DIR        0x0800   /* Asymmetric Pause Direction bit */
-#define NWAY_AR_REMOTE_FAULT   0x2000   /* Remote Fault detected */
-#define NWAY_AR_NEXT_PAGE      0x8000   /* Next Page ability supported */
+#define NWAY_AR_SELECTOR_FIELD 0x0001  /* indicates IEEE 802.3 CSMA/CD */
+#define NWAY_AR_10T_HD_CAPS    0x0020  /* 10T   Half Duplex Capable */
+#define NWAY_AR_10T_FD_CAPS    0x0040  /* 10T   Full Duplex Capable */
+#define NWAY_AR_100TX_HD_CAPS  0x0080  /* 100TX Half Duplex Capable */
+#define NWAY_AR_100TX_FD_CAPS  0x0100  /* 100TX Full Duplex Capable */
+#define NWAY_AR_100T4_CAPS     0x0200  /* 100T4 Capable */
+#define NWAY_AR_PAUSE          0x0400  /* Pause operation desired */
+#define NWAY_AR_ASM_DIR        0x0800  /* Asymmetric Pause Direction bit */
+#define NWAY_AR_REMOTE_FAULT   0x2000  /* Remote Fault detected */
+#define NWAY_AR_NEXT_PAGE      0x8000  /* Next Page ability supported */
 
 /* Link Partner Ability Register (Base Page) */
-#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
-#define NWAY_LPAR_10T_HD_CAPS    0x0020 /* LP is 10T   Half Duplex Capable */
-#define NWAY_LPAR_10T_FD_CAPS    0x0040 /* LP is 10T   Full Duplex Capable */
-#define NWAY_LPAR_100TX_HD_CAPS  0x0080 /* LP is 100TX Half Duplex Capable */
-#define NWAY_LPAR_100TX_FD_CAPS  0x0100 /* LP is 100TX Full Duplex Capable */
-#define NWAY_LPAR_100T4_CAPS     0x0200 /* LP is 100T4 Capable */
-#define NWAY_LPAR_PAUSE          0x0400 /* LP Pause operation desired */
-#define NWAY_LPAR_ASM_DIR        0x0800 /* LP Asymmetric Pause Direction bit */
-#define NWAY_LPAR_REMOTE_FAULT   0x2000 /* LP has detected Remote Fault */
-#define NWAY_LPAR_ACKNOWLEDGE    0x4000 /* LP has rx'd link code word */
-#define NWAY_LPAR_NEXT_PAGE      0x8000 /* Next Page ability supported */
+#define NWAY_LPAR_SELECTOR_FIELD 0x0000        /* LP protocol selector field */
+#define NWAY_LPAR_10T_HD_CAPS    0x0020        /* LP is 10T   Half Duplex Capable */
+#define NWAY_LPAR_10T_FD_CAPS    0x0040        /* LP is 10T   Full Duplex Capable */
+#define NWAY_LPAR_100TX_HD_CAPS  0x0080        /* LP is 100TX Half Duplex Capable */
+#define NWAY_LPAR_100TX_FD_CAPS  0x0100        /* LP is 100TX Full Duplex Capable */
+#define NWAY_LPAR_100T4_CAPS     0x0200        /* LP is 100T4 Capable */
+#define NWAY_LPAR_PAUSE          0x0400        /* LP Pause operation desired */
+#define NWAY_LPAR_ASM_DIR        0x0800        /* LP Asymmetric Pause Direction bit */
+#define NWAY_LPAR_REMOTE_FAULT   0x2000        /* LP has detected Remote Fault */
+#define NWAY_LPAR_ACKNOWLEDGE    0x4000        /* LP has rx'd link code word */
+#define NWAY_LPAR_NEXT_PAGE      0x8000        /* Next Page ability supported */
 
 /* Autoneg Expansion Register */
-#define NWAY_ER_LP_NWAY_CAPS      0x0001 /* LP has Auto Neg Capability */
-#define NWAY_ER_PAGE_RXD          0x0002 /* LP is 10T   Half Duplex Capable */
-#define NWAY_ER_NEXT_PAGE_CAPS    0x0004 /* LP is 10T   Full Duplex Capable */
-#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
-#define NWAY_ER_PAR_DETECT_FAULT  0x0010 /* LP is 100TX Full Duplex Capable */
+#define NWAY_ER_LP_NWAY_CAPS      0x0001       /* LP has Auto Neg Capability */
+#define NWAY_ER_PAGE_RXD          0x0002       /* LP is 10T   Half Duplex Capable */
+#define NWAY_ER_NEXT_PAGE_CAPS    0x0004       /* LP is 10T   Full Duplex Capable */
+#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008       /* LP is 100TX Half Duplex Capable */
+#define NWAY_ER_PAR_DETECT_FAULT  0x0010       /* LP is 100TX Full Duplex Capable */
 
 /* Next Page TX Register */
-#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
-#define NPTX_TOGGLE         0x0800 /* Toggles between exchanges
-                                    * of different NP
-                                    */
-#define NPTX_ACKNOWLDGE2    0x1000 /* 1 = will comply with msg
-                                    * 0 = cannot comply with msg
-                                    */
-#define NPTX_MSG_PAGE       0x2000 /* formatted(1)/unformatted(0) pg */
-#define NPTX_NEXT_PAGE      0x8000 /* 1 = addition NP will follow
-                                    * 0 = sending last NP
-                                    */
+#define NPTX_MSG_CODE_FIELD 0x0001     /* NP msg code or unformatted data */
+#define NPTX_TOGGLE         0x0800     /* Toggles between exchanges
+                                        * of different NP
+                                        */
+#define NPTX_ACKNOWLDGE2    0x1000     /* 1 = will comply with msg
+                                        * 0 = cannot comply with msg
+                                        */
+#define NPTX_MSG_PAGE       0x2000     /* formatted(1)/unformatted(0) pg */
+#define NPTX_NEXT_PAGE      0x8000     /* 1 = addition NP will follow
+                                        * 0 = sending last NP
+                                        */
 
 /* Link Partner Next Page Register */
-#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
-#define LP_RNPR_TOGGLE         0x0800 /* Toggles between exchanges
-                                       * of different NP
-                                       */
-#define LP_RNPR_ACKNOWLDGE2    0x1000 /* 1 = will comply with msg
-                                       * 0 = cannot comply with msg
-                                       */
-#define LP_RNPR_MSG_PAGE       0x2000  /* formatted(1)/unformatted(0) pg */
-#define LP_RNPR_ACKNOWLDGE     0x4000  /* 1 = ACK / 0 = NO ACK */
-#define LP_RNPR_NEXT_PAGE      0x8000  /* 1 = addition NP will follow
-                                        * 0 = sending last NP
-                                        */
+#define LP_RNPR_MSG_CODE_FIELD 0x0001  /* NP msg code or unformatted data */
+#define LP_RNPR_TOGGLE         0x0800  /* Toggles between exchanges
+                                        * of different NP
+                                        */
+#define LP_RNPR_ACKNOWLDGE2    0x1000  /* 1 = will comply with msg
+                                        * 0 = cannot comply with msg
+                                        */
+#define LP_RNPR_MSG_PAGE       0x2000  /* formatted(1)/unformatted(0) pg */
+#define LP_RNPR_ACKNOWLDGE     0x4000  /* 1 = ACK / 0 = NO ACK */
+#define LP_RNPR_NEXT_PAGE      0x8000  /* 1 = addition NP will follow
+                                        * 0 = sending last NP
+                                        */
 
 /* 1000BASE-T Control Register */
-#define CR_1000T_ASYM_PAUSE      0x0080 /* Advertise asymmetric pause bit */
-#define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
-#define CR_1000T_FD_CAPS         0x0200 /* Advertise 1000T FD capability  */
-#define CR_1000T_REPEATER_DTE    0x0400 /* 1=Repeater/switch device port */
-                                        /* 0=DTE device */
-#define CR_1000T_MS_VALUE        0x0800 /* 1=Configure PHY as Master */
-                                        /* 0=Configure PHY as Slave */
-#define CR_1000T_MS_ENABLE       0x1000 /* 1=Master/Slave manual config value */
-                                        /* 0=Automatic Master/Slave config */
-#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
-#define CR_1000T_TEST_MODE_1     0x2000 /* Transmit Waveform test */
-#define CR_1000T_TEST_MODE_2     0x4000 /* Master Transmit Jitter test */
-#define CR_1000T_TEST_MODE_3     0x6000 /* Slave Transmit Jitter test */
-#define CR_1000T_TEST_MODE_4     0x8000 /* Transmitter Distortion test */
+#define CR_1000T_ASYM_PAUSE      0x0080        /* Advertise asymmetric pause bit */
+#define CR_1000T_HD_CAPS         0x0100        /* Advertise 1000T HD capability */
+#define CR_1000T_FD_CAPS         0x0200        /* Advertise 1000T FD capability  */
+#define CR_1000T_REPEATER_DTE    0x0400        /* 1=Repeater/switch device port */
+                                       /* 0=DTE device */
+#define CR_1000T_MS_VALUE        0x0800        /* 1=Configure PHY as Master */
+                                       /* 0=Configure PHY as Slave */
+#define CR_1000T_MS_ENABLE       0x1000        /* 1=Master/Slave manual config value */
+                                       /* 0=Automatic Master/Slave config */
+#define CR_1000T_TEST_MODE_NORMAL 0x0000       /* Normal Operation */
+#define CR_1000T_TEST_MODE_1     0x2000        /* Transmit Waveform test */
+#define CR_1000T_TEST_MODE_2     0x4000        /* Master Transmit Jitter test */
+#define CR_1000T_TEST_MODE_3     0x6000        /* Slave Transmit Jitter test */
+#define CR_1000T_TEST_MODE_4     0x8000        /* Transmitter Distortion test */
 
 /* 1000BASE-T Status Register */
-#define SR_1000T_IDLE_ERROR_CNT   0x00FF /* Num idle errors since last read */
-#define SR_1000T_ASYM_PAUSE_DIR   0x0100 /* LP asymmetric pause direction bit */
-#define SR_1000T_LP_HD_CAPS       0x0400 /* LP is 1000T HD capable */
-#define SR_1000T_LP_FD_CAPS       0x0800 /* LP is 1000T FD capable */
-#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
-#define SR_1000T_LOCAL_RX_STATUS  0x2000 /* Local receiver OK */
-#define SR_1000T_MS_CONFIG_RES    0x4000 /* 1=Local TX is Master, 0=Slave */
-#define SR_1000T_MS_CONFIG_FAULT  0x8000 /* Master/Slave config fault */
+#define SR_1000T_IDLE_ERROR_CNT   0x00FF       /* Num idle errors since last read */
+#define SR_1000T_ASYM_PAUSE_DIR   0x0100       /* LP asymmetric pause direction bit */
+#define SR_1000T_LP_HD_CAPS       0x0400       /* LP is 1000T HD capable */
+#define SR_1000T_LP_FD_CAPS       0x0800       /* LP is 1000T FD capable */
+#define SR_1000T_REMOTE_RX_STATUS 0x1000       /* Remote receiver OK */
+#define SR_1000T_LOCAL_RX_STATUS  0x2000       /* Local receiver OK */
+#define SR_1000T_MS_CONFIG_RES    0x4000       /* 1=Local TX is Master, 0=Slave */
+#define SR_1000T_MS_CONFIG_FAULT  0x8000       /* Master/Slave config fault */
 #define SR_1000T_REMOTE_RX_STATUS_SHIFT          12
 #define SR_1000T_LOCAL_RX_STATUS_SHIFT           13
 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT    5
@@ -2665,64 +2655,64 @@ struct e1000_host_command_info {
 #define FFE_IDLE_ERR_COUNT_TIMEOUT_100           100
 
 /* Extended Status Register */
-#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
-#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
-#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
-#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
+#define IEEE_ESR_1000T_HD_CAPS 0x1000  /* 1000T HD capable */
+#define IEEE_ESR_1000T_FD_CAPS 0x2000  /* 1000T FD capable */
+#define IEEE_ESR_1000X_HD_CAPS 0x4000  /* 1000X HD capable */
+#define IEEE_ESR_1000X_FD_CAPS 0x8000  /* 1000X FD capable */
 
-#define PHY_TX_POLARITY_MASK   0x0100 /* register 10h bit 8 (polarity bit) */
-#define PHY_TX_NORMAL_POLARITY 0      /* register 10h bit 8 (normal polarity) */
+#define PHY_TX_POLARITY_MASK   0x0100  /* register 10h bit 8 (polarity bit) */
+#define PHY_TX_NORMAL_POLARITY 0       /* register 10h bit 8 (normal polarity) */
 
-#define AUTO_POLARITY_DISABLE  0x0010 /* register 11h bit 4 */
-                                      /* (0=enable, 1=disable) */
+#define AUTO_POLARITY_DISABLE  0x0010  /* register 11h bit 4 */
+                                     /* (0=enable, 1=disable) */
 
 /* M88E1000 PHY Specific Control Register */
-#define M88E1000_PSCR_JABBER_DISABLE    0x0001 /* 1=Jabber Function disabled */
-#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
-#define M88E1000_PSCR_SQE_TEST          0x0004 /* 1=SQE Test enabled */
-#define M88E1000_PSCR_CLK125_DISABLE    0x0010 /* 1=CLK125 low,
-                                                * 0=CLK125 toggling
-                                                */
-#define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000  /* MDI Crossover Mode bits 6:5 */
-                                               /* Manual MDI configuration */
-#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020  /* Manual MDIX configuration */
-#define M88E1000_PSCR_AUTO_X_1000T     0x0040  /* 1000BASE-T: Auto crossover,
-                                                *  100BASE-TX/10BASE-T:
-                                                *  MDI Mode
-                                                */
-#define M88E1000_PSCR_AUTO_X_MODE      0x0060  /* Auto crossover enabled
-                                                * all speeds.
-                                                */
+#define M88E1000_PSCR_JABBER_DISABLE    0x0001 /* 1=Jabber Function disabled */
+#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
+#define M88E1000_PSCR_SQE_TEST          0x0004 /* 1=SQE Test enabled */
+#define M88E1000_PSCR_CLK125_DISABLE    0x0010 /* 1=CLK125 low,
+                                                * 0=CLK125 toggling
+                                                */
+#define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000  /* MDI Crossover Mode bits 6:5 */
+                                              /* Manual MDI configuration */
+#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020  /* Manual MDIX configuration */
+#define M88E1000_PSCR_AUTO_X_1000T     0x0040  /* 1000BASE-T: Auto crossover,
+                                                *  100BASE-TX/10BASE-T:
+                                                *  MDI Mode
+                                                */
+#define M88E1000_PSCR_AUTO_X_MODE      0x0060  /* Auto crossover enabled
+                                                * all speeds.
+                                                */
 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
-                                        /* 1=Enable Extended 10BASE-T distance
-                                         * (Lower 10BASE-T RX Threshold)
-                                         * 0=Normal 10BASE-T RX Threshold */
+                                       /* 1=Enable Extended 10BASE-T distance
+                                        * (Lower 10BASE-T RX Threshold)
+                                        * 0=Normal 10BASE-T RX Threshold */
 #define M88E1000_PSCR_MII_5BIT_ENABLE      0x0100
-                                        /* 1=5-Bit interface in 100BASE-TX
-                                         * 0=MII interface in 100BASE-TX */
-#define M88E1000_PSCR_SCRAMBLER_DISABLE    0x0200 /* 1=Scrambler disable */
-#define M88E1000_PSCR_FORCE_LINK_GOOD      0x0400 /* 1=Force link good */
-#define M88E1000_PSCR_ASSERT_CRS_ON_TX     0x0800 /* 1=Assert CRS on Transmit */
+                                       /* 1=5-Bit interface in 100BASE-TX
+                                        * 0=MII interface in 100BASE-TX */
+#define M88E1000_PSCR_SCRAMBLER_DISABLE    0x0200      /* 1=Scrambler disable */
+#define M88E1000_PSCR_FORCE_LINK_GOOD      0x0400      /* 1=Force link good */
+#define M88E1000_PSCR_ASSERT_CRS_ON_TX     0x0800      /* 1=Assert CRS on Transmit */
 
 #define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT    1
 #define M88E1000_PSCR_AUTO_X_MODE_SHIFT          5
 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
 
 /* M88E1000 PHY Specific Status Register */
-#define M88E1000_PSSR_JABBER             0x0001 /* 1=Jabber */
-#define M88E1000_PSSR_REV_POLARITY       0x0002 /* 1=Polarity reversed */
-#define M88E1000_PSSR_DOWNSHIFT          0x0020 /* 1=Downshifted */
-#define M88E1000_PSSR_MDIX               0x0040 /* 1=MDIX; 0=MDI */
-#define M88E1000_PSSR_CABLE_LENGTH       0x0380 /* 0=<50M;1=50-80M;2=80-110M;
-                                            * 3=110-140M;4=>140M */
-#define M88E1000_PSSR_LINK               0x0400 /* 1=Link up, 0=Link down */
-#define M88E1000_PSSR_SPD_DPLX_RESOLVED  0x0800 /* 1=Speed & Duplex resolved */
-#define M88E1000_PSSR_PAGE_RCVD          0x1000 /* 1=Page received */
-#define M88E1000_PSSR_DPLX               0x2000 /* 1=Duplex 0=Half Duplex */
-#define M88E1000_PSSR_SPEED              0xC000 /* Speed, bits 14:15 */
-#define M88E1000_PSSR_10MBS              0x0000 /* 00=10Mbs */
-#define M88E1000_PSSR_100MBS             0x4000 /* 01=100Mbs */
-#define M88E1000_PSSR_1000MBS            0x8000 /* 10=1000Mbs */
+#define M88E1000_PSSR_JABBER             0x0001        /* 1=Jabber */
+#define M88E1000_PSSR_REV_POLARITY       0x0002        /* 1=Polarity reversed */
+#define M88E1000_PSSR_DOWNSHIFT          0x0020        /* 1=Downshifted */
+#define M88E1000_PSSR_MDIX               0x0040        /* 1=MDIX; 0=MDI */
+#define M88E1000_PSSR_CABLE_LENGTH       0x0380        /* 0=<50M;1=50-80M;2=80-110M;
+                                                * 3=110-140M;4=>140M */
+#define M88E1000_PSSR_LINK               0x0400        /* 1=Link up, 0=Link down */
+#define M88E1000_PSSR_SPD_DPLX_RESOLVED  0x0800        /* 1=Speed & Duplex resolved */
+#define M88E1000_PSSR_PAGE_RCVD          0x1000        /* 1=Page received */
+#define M88E1000_PSSR_DPLX               0x2000        /* 1=Duplex 0=Half Duplex */
+#define M88E1000_PSSR_SPEED              0xC000        /* Speed, bits 14:15 */
+#define M88E1000_PSSR_10MBS              0x0000        /* 00=10Mbs */
+#define M88E1000_PSSR_100MBS             0x4000        /* 01=100Mbs */
+#define M88E1000_PSSR_1000MBS            0x8000        /* 10=1000Mbs */
 
 #define M88E1000_PSSR_REV_POLARITY_SHIFT 1
 #define M88E1000_PSSR_DOWNSHIFT_SHIFT    5
@@ -2730,12 +2720,12 @@ struct e1000_host_command_info {
 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
 
 /* M88E1000 Extended PHY Specific Control Register */
-#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
-#define M88E1000_EPSCR_DOWN_NO_IDLE   0x8000 /* 1=Lost lock detect enabled.
-                                              * Will assert lost lock and bring
-                                              * link down if idle not seen
-                                              * within 1ms in 1000BASE-T
-                                              */
+#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000   /* 1=Fiber loopback */
+#define M88E1000_EPSCR_DOWN_NO_IDLE   0x8000   /* 1=Lost lock detect enabled.
+                                                * Will assert lost lock and bring
+                                                * link down if idle not seen
+                                                * within 1ms in 1000BASE-T
+                                                */
 /* Number of times we will attempt to autonegotiate before downshifting if we
  * are the master */
 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
@@ -2750,9 +2740,9 @@ struct e1000_host_command_info {
 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100
 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X    0x0200
 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X    0x0300
-#define M88E1000_EPSCR_TX_CLK_2_5     0x0060 /* 2.5 MHz TX_CLK */
-#define M88E1000_EPSCR_TX_CLK_25      0x0070 /* 25  MHz TX_CLK */
-#define M88E1000_EPSCR_TX_CLK_0       0x0000 /* NO  TX_CLK */
+#define M88E1000_EPSCR_TX_CLK_2_5     0x0060   /* 2.5 MHz TX_CLK */
+#define M88E1000_EPSCR_TX_CLK_25      0x0070   /* 25  MHz TX_CLK */
+#define M88E1000_EPSCR_TX_CLK_0       0x0000   /* NO  TX_CLK */
 
 /* M88EC018 Rev 2 specific DownShift settings */
 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK  0x0E00
@@ -2774,18 +2764,18 @@ struct e1000_host_command_info {
 #define IGP01E1000_PSCFR_DISABLE_TRANSMIT      0x2000
 
 /* IGP01E1000 Specific Port Status Register - R/O */
-#define IGP01E1000_PSSR_AUTONEG_FAILED         0x0001 /* RO LH SC */
+#define IGP01E1000_PSSR_AUTONEG_FAILED         0x0001  /* RO LH SC */
 #define IGP01E1000_PSSR_POLARITY_REVERSED      0x0002
 #define IGP01E1000_PSSR_CABLE_LENGTH           0x007C
 #define IGP01E1000_PSSR_FULL_DUPLEX            0x0200
 #define IGP01E1000_PSSR_LINK_UP                0x0400
 #define IGP01E1000_PSSR_MDIX                   0x0800
-#define IGP01E1000_PSSR_SPEED_MASK             0xC000 /* speed bits mask */
+#define IGP01E1000_PSSR_SPEED_MASK             0xC000  /* speed bits mask */
 #define IGP01E1000_PSSR_SPEED_10MBPS           0x4000
 #define IGP01E1000_PSSR_SPEED_100MBPS          0x8000
 #define IGP01E1000_PSSR_SPEED_1000MBPS         0xC000
-#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT     0x0002 /* shift right 2 */
-#define IGP01E1000_PSSR_MDIX_SHIFT             0x000B /* shift right 11 */
+#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT     0x0002  /* shift right 2 */
+#define IGP01E1000_PSSR_MDIX_SHIFT             0x000B  /* shift right 11 */
 
 /* IGP01E1000 Specific Port Control Register - R/W */
 #define IGP01E1000_PSCR_TP_LOOPBACK            0x0010
@@ -2793,16 +2783,16 @@ struct e1000_host_command_info {
 #define IGP01E1000_PSCR_TEN_CRS_SELECT         0x0400
 #define IGP01E1000_PSCR_FLIP_CHIP              0x0800
 #define IGP01E1000_PSCR_AUTO_MDIX              0x1000
-#define IGP01E1000_PSCR_FORCE_MDI_MDIX         0x2000 /* 0-MDI, 1-MDIX */
+#define IGP01E1000_PSCR_FORCE_MDI_MDIX         0x2000  /* 0-MDI, 1-MDIX */
 
 /* IGP01E1000 Specific Port Link Health Register */
 #define IGP01E1000_PLHR_SS_DOWNGRADE           0x8000
 #define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR    0x4000
 #define IGP01E1000_PLHR_MASTER_FAULT           0x2000
 #define IGP01E1000_PLHR_MASTER_RESOLUTION      0x1000
-#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK       0x0800 /* LH */
-#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW   0x0400 /* LH */
-#define IGP01E1000_PLHR_DATA_ERR_1             0x0200 /* LH */
+#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK       0x0800  /* LH */
+#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW   0x0400  /* LH */
+#define IGP01E1000_PLHR_DATA_ERR_1             0x0200  /* LH */
 #define IGP01E1000_PLHR_DATA_ERR_0             0x0100
 #define IGP01E1000_PLHR_AUTONEG_FAULT          0x0040
 #define IGP01E1000_PLHR_AUTONEG_ACTIVE         0x0010
@@ -2817,9 +2807,9 @@ struct e1000_host_command_info {
 #define IGP01E1000_MSE_CHANNEL_B        0x0F00
 #define IGP01E1000_MSE_CHANNEL_A        0xF000
 
-#define IGP02E1000_PM_SPD                         0x0001  /* Smart Power Down */
-#define IGP02E1000_PM_D3_LPLU                     0x0004  /* Enable LPLU in non-D0a modes */
-#define IGP02E1000_PM_D0_LPLU                     0x0002  /* Enable LPLU in D0a mode */
+#define IGP02E1000_PM_SPD                         0x0001       /* Smart Power Down */
+#define IGP02E1000_PM_D3_LPLU                     0x0004       /* Enable LPLU in non-D0a modes */
+#define IGP02E1000_PM_D0_LPLU                     0x0002       /* Enable LPLU in D0a mode */
 
 /* IGP01E1000 DSP reset macros */
 #define DSP_RESET_ENABLE     0x0
@@ -2828,8 +2818,8 @@ struct e1000_host_command_info {
 
 /* IGP01E1000 & IGP02E1000 AGC Registers */
 
-#define IGP01E1000_AGC_LENGTH_SHIFT 7         /* Coarse - 13:11, Fine - 10:7 */
-#define IGP02E1000_AGC_LENGTH_SHIFT 9         /* Coarse - 15:13, Fine - 12:9 */
+#define IGP01E1000_AGC_LENGTH_SHIFT 7  /* Coarse - 13:11, Fine - 10:7 */
+#define IGP02E1000_AGC_LENGTH_SHIFT 9  /* Coarse - 15:13, Fine - 12:9 */
 
 /* IGP02E1000 AGC Register Length 9-bit mask */
 #define IGP02E1000_AGC_LENGTH_MASK  0x7F
@@ -2847,9 +2837,9 @@ struct e1000_host_command_info {
 #define IGP01E1000_PHY_POLARITY_MASK    0x0078
 
 /* IGP01E1000 GMII FIFO Register */
-#define IGP01E1000_GMII_FLEX_SPD               0x10 /* Enable flexible speed
-                                                     * on Link-Up */
-#define IGP01E1000_GMII_SPD                    0x20 /* Enable SPD */
+#define IGP01E1000_GMII_FLEX_SPD               0x10    /* Enable flexible speed
+                                                        * on Link-Up */
+#define IGP01E1000_GMII_SPD                    0x20    /* Enable SPD */
 
 /* IGP01E1000 Analog Register */
 #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS       0x20D1
@@ -2883,7 +2873,6 @@ struct e1000_host_command_info {
 #define M88E1111_I_PHY_ID  0x01410CC0
 #define L1LXT971A_PHY_ID   0x001378E0
 
-
 /* Bits...
  * 15-5: page
  * 4-0: register offset
@@ -2893,41 +2882,41 @@ struct e1000_host_command_info {
         (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
 
 #define IGP3_PHY_PORT_CTRL           \
-        PHY_REG(769, 17) /* Port General Configuration */
+        PHY_REG(769, 17)       /* Port General Configuration */
 #define IGP3_PHY_RATE_ADAPT_CTRL \
-        PHY_REG(769, 25) /* Rate Adapter Control Register */
+        PHY_REG(769, 25)       /* Rate Adapter Control Register */
 
 #define IGP3_KMRN_FIFO_CTRL_STATS \
-        PHY_REG(770, 16) /* KMRN FIFO's control/status register */
+        PHY_REG(770, 16)       /* KMRN FIFO's control/status register */
 #define IGP3_KMRN_POWER_MNG_CTRL \
-        PHY_REG(770, 17) /* KMRN Power Management Control Register */
+        PHY_REG(770, 17)       /* KMRN Power Management Control Register */
 #define IGP3_KMRN_INBAND_CTRL \
-        PHY_REG(770, 18) /* KMRN Inband Control Register */
+        PHY_REG(770, 18)       /* KMRN Inband Control Register */
 #define IGP3_KMRN_DIAG \
-        PHY_REG(770, 19) /* KMRN Diagnostic register */
-#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */
+        PHY_REG(770, 19)       /* KMRN Diagnostic register */
+#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002    /* RX PCS is not synced */
 #define IGP3_KMRN_ACK_TIMEOUT \
-        PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
+        PHY_REG(770, 20)       /* KMRN Acknowledge Timeouts register */
 
 #define IGP3_VR_CTRL \
-        PHY_REG(776, 18) /* Voltage regulator control register */
-#define IGP3_VR_CTRL_MODE_SHUT       0x0200 /* Enter powerdown, shutdown VRs */
-#define IGP3_VR_CTRL_MODE_MASK       0x0300 /* Shutdown VR Mask */
+        PHY_REG(776, 18)       /* Voltage regulator control register */
+#define IGP3_VR_CTRL_MODE_SHUT       0x0200    /* Enter powerdown, shutdown VRs */
+#define IGP3_VR_CTRL_MODE_MASK       0x0300    /* Shutdown VR Mask */
 
 #define IGP3_CAPABILITY \
-        PHY_REG(776, 19) /* IGP3 Capability Register */
+        PHY_REG(776, 19)       /* IGP3 Capability Register */
 
 /* Capabilities for SKU Control  */
-#define IGP3_CAP_INITIATE_TEAM       0x0001 /* Able to initiate a team */
-#define IGP3_CAP_WFM                 0x0002 /* Support WoL and PXE */
-#define IGP3_CAP_ASF                 0x0004 /* Support ASF */
-#define IGP3_CAP_LPLU                0x0008 /* Support Low Power Link Up */
-#define IGP3_CAP_DC_AUTO_SPEED       0x0010 /* Support AC/DC Auto Link Speed */
-#define IGP3_CAP_SPD                 0x0020 /* Support Smart Power Down */
-#define IGP3_CAP_MULT_QUEUE          0x0040 /* Support 2 tx & 2 rx queues */
-#define IGP3_CAP_RSS                 0x0080 /* Support RSS */
-#define IGP3_CAP_8021PQ              0x0100 /* Support 802.1Q & 802.1p */
-#define IGP3_CAP_AMT_CB              0x0200 /* Support active manageability and circuit breaker */
+#define IGP3_CAP_INITIATE_TEAM       0x0001    /* Able to initiate a team */
+#define IGP3_CAP_WFM                 0x0002    /* Support WoL and PXE */
+#define IGP3_CAP_ASF                 0x0004    /* Support ASF */
+#define IGP3_CAP_LPLU                0x0008    /* Support Low Power Link Up */
+#define IGP3_CAP_DC_AUTO_SPEED       0x0010    /* Support AC/DC Auto Link Speed */
+#define IGP3_CAP_SPD                 0x0020    /* Support Smart Power Down */
+#define IGP3_CAP_MULT_QUEUE          0x0040    /* Support 2 tx & 2 rx queues */
+#define IGP3_CAP_RSS                 0x0080    /* Support RSS */
+#define IGP3_CAP_8021PQ              0x0100    /* Support 802.1Q & 802.1p */
+#define IGP3_CAP_AMT_CB              0x0200    /* Support active manageability and circuit breaker */
 
 #define IGP3_PPC_JORDAN_EN           0x0001
 #define IGP3_PPC_JORDAN_GIGA_SPEED   0x0002
@@ -2937,69 +2926,69 @@ struct e1000_host_command_info {
 #define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA        0x0020
 #define IGP3_KMRN_PMC_K0S_MODE1_EN_100         0x0040
 
-#define IGP3E1000_PHY_MISC_CTRL                0x1B   /* Misc. Ctrl register */
-#define IGP3_PHY_MISC_DUPLEX_MANUAL_SET        0x1000 /* Duplex Manual Set */
+#define IGP3E1000_PHY_MISC_CTRL                0x1B    /* Misc. Ctrl register */
+#define IGP3_PHY_MISC_DUPLEX_MANUAL_SET        0x1000  /* Duplex Manual Set */
 
 #define IGP3_KMRN_EXT_CTRL  PHY_REG(770, 18)
 #define IGP3_KMRN_EC_DIS_INBAND    0x0080
 
 #define IGP03E1000_E_PHY_ID  0x02A80390
-#define IFE_E_PHY_ID         0x02A80330 /* 10/100 PHY */
+#define IFE_E_PHY_ID         0x02A80330        /* 10/100 PHY */
 #define IFE_PLUS_E_PHY_ID    0x02A80320
 #define IFE_C_E_PHY_ID       0x02A80310
 
-#define IFE_PHY_EXTENDED_STATUS_CONTROL   0x10  /* 100BaseTx Extended Status, Control and Address */
-#define IFE_PHY_SPECIAL_CONTROL           0x11  /* 100BaseTx PHY special control register */
-#define IFE_PHY_RCV_FALSE_CARRIER         0x13  /* 100BaseTx Receive False Carrier Counter */
-#define IFE_PHY_RCV_DISCONNECT            0x14  /* 100BaseTx Receive Disconnet Counter */
-#define IFE_PHY_RCV_ERROT_FRAME           0x15  /* 100BaseTx Receive Error Frame Counter */
-#define IFE_PHY_RCV_SYMBOL_ERR            0x16  /* Receive Symbol Error Counter */
-#define IFE_PHY_PREM_EOF_ERR              0x17  /* 100BaseTx Receive Premature End Of Frame Error Counter */
-#define IFE_PHY_RCV_EOF_ERR               0x18  /* 10BaseT Receive End Of Frame Error Counter */
-#define IFE_PHY_TX_JABBER_DETECT          0x19  /* 10BaseT Transmit Jabber Detect Counter */
-#define IFE_PHY_EQUALIZER                 0x1A  /* PHY Equalizer Control and Status */
-#define IFE_PHY_SPECIAL_CONTROL_LED       0x1B  /* PHY special control and LED configuration */
-#define IFE_PHY_MDIX_CONTROL              0x1C  /* MDI/MDI-X Control register */
-#define IFE_PHY_HWI_CONTROL               0x1D  /* Hardware Integrity Control (HWI) */
-
-#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE  0x2000  /* Defaut 1 = Disable auto reduced power down */
-#define IFE_PESC_100BTX_POWER_DOWN           0x0400  /* Indicates the power state of 100BASE-TX */
-#define IFE_PESC_10BTX_POWER_DOWN            0x0200  /* Indicates the power state of 10BASE-T */
-#define IFE_PESC_POLARITY_REVERSED           0x0100  /* Indicates 10BASE-T polarity */
-#define IFE_PESC_PHY_ADDR_MASK               0x007C  /* Bit 6:2 for sampled PHY address */
-#define IFE_PESC_SPEED                       0x0002  /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */
-#define IFE_PESC_DUPLEX                      0x0001  /* Auto-negotiation duplex result 1=Full, 0=Half */
+#define IFE_PHY_EXTENDED_STATUS_CONTROL   0x10 /* 100BaseTx Extended Status, Control and Address */
+#define IFE_PHY_SPECIAL_CONTROL           0x11 /* 100BaseTx PHY special control register */
+#define IFE_PHY_RCV_FALSE_CARRIER         0x13 /* 100BaseTx Receive False Carrier Counter */
+#define IFE_PHY_RCV_DISCONNECT            0x14 /* 100BaseTx Receive Disconnect Counter */
+#define IFE_PHY_RCV_ERROT_FRAME           0x15 /* 100BaseTx Receive Error Frame Counter */
+#define IFE_PHY_RCV_SYMBOL_ERR            0x16 /* Receive Symbol Error Counter */
+#define IFE_PHY_PREM_EOF_ERR              0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */
+#define IFE_PHY_RCV_EOF_ERR               0x18 /* 10BaseT Receive End Of Frame Error Counter */
+#define IFE_PHY_TX_JABBER_DETECT          0x19 /* 10BaseT Transmit Jabber Detect Counter */
+#define IFE_PHY_EQUALIZER                 0x1A /* PHY Equalizer Control and Status */
+#define IFE_PHY_SPECIAL_CONTROL_LED       0x1B /* PHY special control and LED configuration */
+#define IFE_PHY_MDIX_CONTROL              0x1C /* MDI/MDI-X Control register */
+#define IFE_PHY_HWI_CONTROL               0x1D /* Hardware Integrity Control (HWI) */
+
+#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE  0x2000    /* Default 1 = Disable auto reduced power down */
+#define IFE_PESC_100BTX_POWER_DOWN           0x0400    /* Indicates the power state of 100BASE-TX */
+#define IFE_PESC_10BTX_POWER_DOWN            0x0200    /* Indicates the power state of 10BASE-T */
+#define IFE_PESC_POLARITY_REVERSED           0x0100    /* Indicates 10BASE-T polarity */
+#define IFE_PESC_PHY_ADDR_MASK               0x007C    /* Bit 6:2 for sampled PHY address */
+#define IFE_PESC_SPEED                       0x0002    /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */
+#define IFE_PESC_DUPLEX                      0x0001    /* Auto-negotiation duplex result 1=Full, 0=Half */
 #define IFE_PESC_POLARITY_REVERSED_SHIFT     8
 
-#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN   0x0100  /* 1 = Dyanmic Power Down disabled */
-#define IFE_PSC_FORCE_POLARITY               0x0020  /* 1=Reversed Polarity, 0=Normal */
-#define IFE_PSC_AUTO_POLARITY_DISABLE        0x0010  /* 1=Auto Polarity Disabled, 0=Enabled */
-#define IFE_PSC_JABBER_FUNC_DISABLE          0x0001  /* 1=Jabber Disabled, 0=Normal Jabber Operation */
+#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN   0x0100    /* 1 = Dynamic Power Down disabled */
+#define IFE_PSC_FORCE_POLARITY               0x0020    /* 1=Reversed Polarity, 0=Normal */
+#define IFE_PSC_AUTO_POLARITY_DISABLE        0x0010    /* 1=Auto Polarity Disabled, 0=Enabled */
+#define IFE_PSC_JABBER_FUNC_DISABLE          0x0001    /* 1=Jabber Disabled, 0=Normal Jabber Operation */
 #define IFE_PSC_FORCE_POLARITY_SHIFT         5
 #define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT  4
 
-#define IFE_PMC_AUTO_MDIX                    0x0080  /* 1=enable MDI/MDI-X feature, default 0=disabled */
-#define IFE_PMC_FORCE_MDIX                   0x0040  /* 1=force MDIX-X, 0=force MDI */
-#define IFE_PMC_MDIX_STATUS                  0x0020  /* 1=MDI-X, 0=MDI */
-#define IFE_PMC_AUTO_MDIX_COMPLETE           0x0010  /* Resolution algorithm is completed */
+#define IFE_PMC_AUTO_MDIX                    0x0080    /* 1=enable MDI/MDI-X feature, default 0=disabled */
+#define IFE_PMC_FORCE_MDIX                   0x0040    /* 1=force MDIX-X, 0=force MDI */
+#define IFE_PMC_MDIX_STATUS                  0x0020    /* 1=MDI-X, 0=MDI */
+#define IFE_PMC_AUTO_MDIX_COMPLETE           0x0010    /* Resolution algorithm is completed */
 #define IFE_PMC_MDIX_MODE_SHIFT              6
-#define IFE_PHC_MDIX_RESET_ALL_MASK          0x0000  /* Disable auto MDI-X */
-
-#define IFE_PHC_HWI_ENABLE                   0x8000  /* Enable the HWI feature */
-#define IFE_PHC_ABILITY_CHECK                0x4000  /* 1= Test Passed, 0=failed */
-#define IFE_PHC_TEST_EXEC                    0x2000  /* PHY launch test pulses on the wire */
-#define IFE_PHC_HIGHZ                        0x0200  /* 1 = Open Circuit */
-#define IFE_PHC_LOWZ                         0x0400  /* 1 = Short Circuit */
-#define IFE_PHC_LOW_HIGH_Z_MASK              0x0600  /* Mask for indication type of problem on the line */
-#define IFE_PHC_DISTANCE_MASK                0x01FF  /* Mask for distance to the cable problem, in 80cm granularity */
-#define IFE_PHC_RESET_ALL_MASK               0x0000  /* Disable HWI */
-#define IFE_PSCL_PROBE_MODE                  0x0020  /* LED Probe mode */
-#define IFE_PSCL_PROBE_LEDS_OFF              0x0006  /* Force LEDs 0 and 2 off */
-#define IFE_PSCL_PROBE_LEDS_ON               0x0007  /* Force LEDs 0 and 2 on */
-
-#define ICH_FLASH_COMMAND_TIMEOUT            5000    /* 5000 uSecs - adjusted */
-#define ICH_FLASH_ERASE_TIMEOUT              3000000 /* Up to 3 seconds - worst case */
-#define ICH_FLASH_CYCLE_REPEAT_COUNT         10      /* 10 cycles */
+#define IFE_PHC_MDIX_RESET_ALL_MASK          0x0000    /* Disable auto MDI-X */
+
+#define IFE_PHC_HWI_ENABLE                   0x8000    /* Enable the HWI feature */
+#define IFE_PHC_ABILITY_CHECK                0x4000    /* 1= Test Passed, 0=failed */
+#define IFE_PHC_TEST_EXEC                    0x2000    /* PHY launch test pulses on the wire */
+#define IFE_PHC_HIGHZ                        0x0200    /* 1 = Open Circuit */
+#define IFE_PHC_LOWZ                         0x0400    /* 1 = Short Circuit */
+#define IFE_PHC_LOW_HIGH_Z_MASK              0x0600    /* Mask for indication type of problem on the line */
+#define IFE_PHC_DISTANCE_MASK                0x01FF    /* Mask for distance to the cable problem, in 80cm granularity */
+#define IFE_PHC_RESET_ALL_MASK               0x0000    /* Disable HWI */
+#define IFE_PSCL_PROBE_MODE                  0x0020    /* LED Probe mode */
+#define IFE_PSCL_PROBE_LEDS_OFF              0x0006    /* Force LEDs 0 and 2 off */
+#define IFE_PSCL_PROBE_LEDS_ON               0x0007    /* Force LEDs 0 and 2 on */
+
+#define ICH_FLASH_COMMAND_TIMEOUT            5000      /* 5000 uSecs - adjusted */
+#define ICH_FLASH_ERASE_TIMEOUT              3000000   /* Up to 3 seconds - worst case */
+#define ICH_FLASH_CYCLE_REPEAT_COUNT         10        /* 10 cycles */
 #define ICH_FLASH_SEG_SIZE_256               256
 #define ICH_FLASH_SEG_SIZE_4K                4096
 #define ICH_FLASH_SEG_SIZE_64K               65536
@@ -3043,10 +3032,10 @@ struct e1000_host_command_info {
 #define MII_CR_SPEED_100    0x2000
 #define MII_CR_SPEED_10     0x0000
 #define E1000_PHY_ADDRESS   0x01
-#define PHY_AUTO_NEG_TIME   45  /* 4.5 Seconds */
-#define PHY_FORCE_TIME      20  /* 2.0 Seconds */
+#define PHY_AUTO_NEG_TIME   45 /* 4.5 Seconds */
+#define PHY_FORCE_TIME      20 /* 2.0 Seconds */
 #define PHY_REVISION_MASK   0xFFFFFFF0
-#define DEVICE_SPEED_MASK   0x00000300  /* Device Ctrl Reg Speed Mask */
+#define DEVICE_SPEED_MASK   0x00000300 /* Device Ctrl Reg Speed Mask */
 #define REG4_SPEED_MASK     0x01E0
 #define REG9_SPEED_MASK     0x0300
 #define ADVERTISE_10_HALF   0x0001
@@ -3055,8 +3044,8 @@ struct e1000_host_command_info {
 #define ADVERTISE_100_FULL  0x0008
 #define ADVERTISE_1000_HALF 0x0010
 #define ADVERTISE_1000_FULL 0x0020
-#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F  /* Everything but 1000-Half */
-#define AUTONEG_ADVERTISE_10_100_ALL    0x000F /* All 10/100 speeds*/
-#define AUTONEG_ADVERTISE_10_ALL        0x0003 /* 10Mbps Full & Half speeds*/
+#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
+#define AUTONEG_ADVERTISE_10_100_ALL    0x000F /* All 10/100 speeds */
+#define AUTONEG_ADVERTISE_10_ALL        0x0003 /* 10Mbps Full & Half speeds */
 
 #endif /* _E1000_HW_H_ */
index d7dea6946e85267d91e36c263ac530b296a6fa18..8302e1881b834f0ea49441f3840406be925ba3ee 100644 (file)
@@ -2255,7 +2255,6 @@ static bool e1000_has_link(struct e1000_adapter *adapter)
 {
        struct e1000_hw *hw = &adapter->hw;
        bool link_active = false;
-       s32 ret_val = 0;
 
        /* get_link_status is set on LSC (link status) interrupt or
         * rx sequence error interrupt.  get_link_status will stay
@@ -2265,18 +2264,18 @@ static bool e1000_has_link(struct e1000_adapter *adapter)
        switch (hw->media_type) {
        case e1000_media_type_copper:
                if (hw->get_link_status) {
-                       ret_val = e1000_check_for_link(hw);
+                       e1000_check_for_link(hw);
                        link_active = !hw->get_link_status;
                } else {
                        link_active = true;
                }
                break;
        case e1000_media_type_fiber:
-               ret_val = e1000_check_for_link(hw);
+               e1000_check_for_link(hw);
                link_active = !!(er32(STATUS) & E1000_STATUS_LU);
                break;
        case e1000_media_type_internal_serdes:
-               ret_val = e1000_check_for_link(hw);
+               e1000_check_for_link(hw);
                link_active = hw->serdes_has_link;
                break;
        default:
@@ -4405,8 +4404,7 @@ static void e1000_vlan_rx_register(struct net_device *netdev,
                ew32(RCTL, rctl);
 
                if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
-                       e1000_vlan_rx_kill_vid(netdev,
-                                              adapter->mng_vlan_id);
+                       e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
                        adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
                }
        }
@@ -4679,7 +4677,7 @@ static void e1000_netpoll(struct net_device *netdev)
 /**
  * e1000_io_error_detected - called when PCI error is detected
  * @pdev: Pointer to PCI device
- * @state: The current pci conneection state
+ * @state: The current pci connection state
  *
  * This function is called after a PCI bus error affecting
  * this device has been detected.