for (i = 0; i < fragcount; ++i) {
desc[i].next_desc_addr = &(desc[i + 1]);
- desc[i].start_addr = (unsigned long)buf + i*fragsize;
+ desc[i].start_addr = (unsigned long)buf + i * fragsize;
desc[i].cfg = cfg;
desc[i].x_count = count;
desc[i].x_modify = wdsize;
}
/* make circular */
- desc[fragcount-1].next_desc_addr = desc;
+ desc[fragcount - 1].next_desc_addr = desc;
}
int sport_config_tx_dma(struct sport_device *sport, void *buf,
unsigned int cfg;
dma_addr_t addr;
- count = fragsize/sport->wdsize;
+ count = fragsize / sport->wdsize;
if (sport->tx_desc)
dma_free_coherent(NULL, sport->tx_desc_size,
cfg = DMAFLOW_LIST | DI_EN | compute_wdsize(sport->wdsize) | NDSIZE_6;
setup_desc(sport->tx_desc, buf, fragcount, fragsize,
- cfg|DMAEN, count, sport->wdsize);
-
+ cfg | DMAEN, count, sport->wdsize);
return 0;
}
EXPORT_SYMBOL(sport_config_tx_dma);
unsigned int cfg;
dma_addr_t addr;
- count = fragsize/sport->wdsize;
+ count = fragsize / sport->wdsize;
if (sport->rx_desc)
dma_free_coherent(NULL, sport->rx_desc_size,
| WNR | NDSIZE_6;
setup_desc(sport->rx_desc, buf, fragcount, fragsize,
- cfg|DMAEN, count, sport->wdsize);
-
+ cfg | DMAEN, count, sport->wdsize);
return 0;
}
EXPORT_SYMBOL(sport_config_rx_dma);
static unsigned long status;
status = get_dma_curr_irqstat(sport->tx_dma_chan);
- if (status & (DMA_DONE|DMA_ERR)) {
+ if (status & (DMA_DONE | DMA_ERR)) {
clear_dma_irqstat(sport->tx_dma_chan);
SSYNC();
}
unsigned long status;
status = get_dma_curr_irqstat(sport->rx_dma_chan);
- if (status & (DMA_DONE|DMA_ERR)) {
+ if (status & (DMA_DONE | DMA_ERR)) {
clear_dma_irqstat(sport->rx_dma_chan);
SSYNC();
}