const struct espi_intr_counts *t1_espi_get_intr_counts(struct peespi *espi)
{
- return &espi->intr_cnt;
+ return &espi->intr_cnt;
}
static void espi_setup_for_pm3393(adapter_t *adapter)
/* 802.3ae 10Gb/s MDIO Manageable Device(MMD)
*/
enum {
- MMD_RESERVED,
- MMD_PMAPMD,
- MMD_WIS,
- MMD_PCS,
- MMD_PHY_XGXS, /* XGMII Extender Sublayer */
- MMD_DTE_XGXS,
+ MMD_RESERVED,
+ MMD_PMAPMD,
+ MMD_WIS,
+ MMD_PCS,
+ MMD_PHY_XGXS, /* XGMII Extender Sublayer */
+ MMD_DTE_XGXS,
};
enum {
- PHY_XGXS_CTRL_1,
- PHY_XGXS_STATUS_1
+ PHY_XGXS_CTRL_1,
+ PHY_XGXS_STATUS_1
};
#define OFFSET(REG_ADDR) (REG_ADDR << 2)
{
u32 pcix_cause;
- pci_read_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, &pcix_cause);
+ pci_read_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE, &pcix_cause);
if (pcix_cause) {
pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE,
- pcix_cause);
+ pcix_cause);
t1_fatal_err(adapter); /* PCI errors are fatal */
}
return 0;
*/
int elmer0_ext_intr_handler(adapter_t *adapter)
{
- struct cphy *phy;
+ struct cphy *phy;
int phy_cause;
- u32 cause;
+ u32 cause;
t1_tpi_read(adapter, A_ELMER0_INT_CAUSE, &cause);
}
/* Enable interrupts for external devices. */
- pl_intr = readl(adapter->regs + A_PL_CAUSE);
+ pl_intr = readl(adapter->regs + A_PL_CAUSE);
writel(pl_intr | F_PL_INTR_EXT | F_PL_INTR_PCIX,
adapter->regs + A_PL_CAUSE);
case CHBT_BOARD_N110:
case CHBT_BOARD_N210:
writel(V_TPIPAR(0xf), adapter->regs + A_TPI_PAR);
- t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);
+ t1_tpi_write(adapter, A_ELMER0_GPO, 0x800);
break;
}
return 0;