drm/i915/bxt: Program Tx Rx and Dphy clocks

BXT DSI clocks are different than previous platforms. So adding a
new function to program following clocks and dividers:
1. Program variable divider to generate input to Tx clock divider
   (Output value must be < 39.5Mhz)
2. Select divide by 2 option to get < 20Mhz for Tx clock
3. Program 8by3 divider to generate Rx clock

v2: Fixed Jani's review comments. Adjusted the Macro definition as
    per convention. Simplified the logic for bit definitions for
    MIPI PORT A and PORT C in same registers.

v3: Refactored the macros for TX, RX Escape and DPHY clocks as per
    Jani's suggestion.

v4: Addressed Jani's review comments.

Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 87de3a085ff6f01536d972b4615905ad14ee13dd..8c24851b930cd89f6486e2ab3894f93d9b40180c 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7547,6 +7547,68 @@ enum skl_disp_power_wells {
 
 #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c)   /* ports A and C only */
 
+/* BXT MIPI clock controls */
+#define BXT_MAX_VAR_OUTPUT_KHZ                 39500
+
+#define BXT_MIPI_CLOCK_CTL                     0x46090
+#define  BXT_MIPI1_DIV_SHIFT                   26
+#define  BXT_MIPI2_DIV_SHIFT                   10
+#define  BXT_MIPI_DIV_SHIFT(port)              \
+                       _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
+                                       BXT_MIPI2_DIV_SHIFT)
+/* Var clock divider to generate TX source. Result must be < 39.5 M */
+#define  BXT_MIPI1_ESCLK_VAR_DIV_MASK          (0x3F << 26)
+#define  BXT_MIPI2_ESCLK_VAR_DIV_MASK          (0x3F << 10)
+#define  BXT_MIPI_ESCLK_VAR_DIV_MASK(port)     \
+                       _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
+                                               BXT_MIPI2_ESCLK_VAR_DIV_MASK)
+
+#define  BXT_MIPI_ESCLK_VAR_DIV(port, val)     \
+                       (val << BXT_MIPI_DIV_SHIFT(port))
+/* TX control divider to select actual TX clock output from (8x/var) */
+#define  BXT_MIPI1_TX_ESCLK_SHIFT              21
+#define  BXT_MIPI2_TX_ESCLK_SHIFT              5
+#define  BXT_MIPI_TX_ESCLK_SHIFT(port)         \
+                       _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
+                                       BXT_MIPI2_TX_ESCLK_SHIFT)
+#define  BXT_MIPI1_TX_ESCLK_FIXDIV_MASK                (3 << 21)
+#define  BXT_MIPI2_TX_ESCLK_FIXDIV_MASK                (3 << 5)
+#define  BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)   \
+                       _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
+                                               BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
+#define  BXT_MIPI_TX_ESCLK_8XDIV_BY2(port)     \
+               (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
+#define  BXT_MIPI_TX_ESCLK_8XDIV_BY4(port)     \
+               (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
+#define  BXT_MIPI_TX_ESCLK_8XDIV_BY8(port)     \
+               (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
+/* RX control divider to select actual RX clock output from 8x*/
+#define  BXT_MIPI1_RX_ESCLK_SHIFT              19
+#define  BXT_MIPI2_RX_ESCLK_SHIFT              3
+#define  BXT_MIPI_RX_ESCLK_SHIFT(port)         \
+                       _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
+                                       BXT_MIPI2_RX_ESCLK_SHIFT)
+#define  BXT_MIPI1_RX_ESCLK_FIXDIV_MASK                (3 << 19)
+#define  BXT_MIPI2_RX_ESCLK_FIXDIV_MASK                (3 << 3)
+#define  BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port)   \
+               (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
+#define  BXT_MIPI_RX_ESCLK_8X_BY2(port)        \
+               (1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
+#define  BXT_MIPI_RX_ESCLK_8X_BY3(port)        \
+               (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
+#define  BXT_MIPI_RX_ESCLK_8X_BY4(port)        \
+               (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
+/* BXT-A WA: Always prog DPHY dividers to 00 */
+#define  BXT_MIPI1_DPHY_DIV_SHIFT              16
+#define  BXT_MIPI2_DPHY_DIV_SHIFT              0
+#define  BXT_MIPI_DPHY_DIV_SHIFT(port)         \
+                       _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
+                                       BXT_MIPI2_DPHY_DIV_SHIFT)
+#define  BXT_MIPI_1_DPHY_DIVIDER_MASK          (3 << 16)
+#define  BXT_MIPI_2_DPHY_DIVIDER_MASK          (3 << 0)
+#define  BXT_MIPI_DPHY_DIVIDER_MASK(port)      \
+               (3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
+
 /* BXT MIPI mode configure */
 #define  _BXT_MIPIA_TRANS_HACTIVE                      0x6B0F8
 #define  _BXT_MIPIC_TRANS_HACTIVE                      0x6B8F8

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index f335e6cd443141af3743fe22ccb3a59efd6dfdcb..38633628199734a4364cfcf38437e985d601c46d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -384,6 +384,42 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
        return pclk;
 }
 
+/* Program BXT Mipi clocks and dividers */
+static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
+{
+       u32 tmp;
+       u32 divider;
+       u32 dsi_rate;
+       u32 pll_ratio;
+       struct drm_i915_private *dev_priv = dev->dev_private;
+
+       /* Clear old configurations */
+       tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
+       tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
+       tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
+       tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
+       tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
+
+       /* Get the current DSI rate(actual) */
+       pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
+                               BXT_DSI_PLL_RATIO_MASK;
+       dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
+
+       /* Max possible output of clock is 39.5 MHz, program value -1 */
+       divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
+       tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
+
+       /*
+        * Tx escape clock must be as close to 20MHz possible, but should
+        * not exceed it. Hence select divide by 2
+        */
+       tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);
+
+       tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port);
+
+       I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
+}
+
 static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
 {
        struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
@@ -435,6 +471,8 @@ static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
 static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
 {
        struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+       struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+       enum port port;
        u32 val;
 
        DRM_DEBUG_KMS("\n");
@@ -453,6 +491,10 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
                return;
        }
 
+       /* Program TX, RX, Dphy clocks */
+       for_each_dsi_port(port, intel_dsi->ports)
+               bxt_dsi_program_clocks(encoder->base.dev, port);
+
        /* Enable DSI PLL */
        val = I915_READ(BXT_DSI_PLL_ENABLE);
        val |= BXT_DSI_PLL_DO_ENABLE;