staging/rdma/hfi1: Correctly limit VLs against SDMA engines

Correctly reduce the number of VLs when limited by the number
of SDMA engines.

The hardware has multiple egress mechanisms, SDMA and pio, and multiples
of those. These mechanisms are chosen using the VL (8)

The fix corrects a panic issue with one of the platforms that doesn't have
enough SDMA (4) mechanisms for the typical number of VLs.

Reviewed-by: Mike Marciniszyn <mike.marciniszyn@intel.com>
Signed-off-by: Dean Luick <dean.luick@intel.com>
Signed-off-by: Jubin John <jubin.john@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/rdma/hfi1/chip.c b/drivers/staging/rdma/hfi1/chip.c
index 03a665f0254ee279f22c785ec19516021cad4ebf..0c27cc09c918507804ae436b41b9b1b5d210f912 100644 (file)
--- a/drivers/staging/rdma/hfi1/chip.c
+++ b/drivers/staging/rdma/hfi1/chip.c
@@ -10645,9 +10645,9 @@ struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev,
        /* insure num_vls isn't larger than number of sdma engines */
        if (HFI1_CAP_IS_KSET(SDMA) && num_vls > dd->chip_sdma_engines) {
                dd_dev_err(dd, "num_vls %u too large, using %u VLs\n",
-                               num_vls, HFI1_MAX_VLS_SUPPORTED);
-               ppd->vls_supported = num_vls = HFI1_MAX_VLS_SUPPORTED;
-               ppd->vls_operational = ppd->vls_supported;
+                          num_vls, dd->chip_sdma_engines);
+               num_vls = dd->chip_sdma_engines;
+               ppd->vls_supported = dd->chip_sdma_engines;
        }
 
        /*