clocksource: sunxi: Rename sunxi to sun4i

During the introduction of the Allwinner SoC platforms, sunxi was
initially meant as a generic name for all the variants of the Allwinner
SoC.

It was ok at the time of the support of only the A10 and A13 that
looks pretty much the same, but it's beginning to be troublesome with
the future addition of the Allwinner A31 (sun6i) that is quite
different, and would introduce some weird logic, where sunxi would
actually mean in some case sun4i and sun5i but without sun6i...

Moreover, it makes the compatible strings naming scheme not consistent
with other architectures, where usually for this kind of compability, we
just use the oldest SoC name that has this IP, so let's do just this.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
new file mode 100644 (file)
index 0000000..48aeb78
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
@@ -0,0 +1,17 @@
+Allwinner A1X SoCs Timer Controller
+
+Required properties:
+
+- compatible : should be "allwinner,sun4i-timer"
+- reg : Specifies base physical address and size of the registers.
+- interrupts : The interrupt of the first timer
+- clocks: phandle to the source clock (usually a 24 MHz fixed clock)
+
+Example:
+
+timer {
+       compatible = "allwinner,sun4i-timer";
+       reg = <0x01c20c00 0x400>;
+       interrupts = <22>;
+       clocks = <&osc>;
+};

diff --git a/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt
deleted file mode 100644 (file)
index 0c7b64e..0000000
--- a/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-Allwinner A1X SoCs Timer Controller
-
-Required properties:
-
-- compatible : should be "allwinner,sunxi-timer"
-- reg : Specifies base physical address and size of the registers.
-- interrupts : The interrupt of the first timer
-- clocks: phandle to the source clock (usually a 24 MHz fixed clock)
-
-Example:
-
-timer {
-       compatible = "allwinner,sunxi-timer";
-       reg = <0x01c20c00 0x400>;
-       interrupts = <22>;
-       clocks = <&osc>;
-};

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 06c28945357d9f4584485ba3ef9ce9c5930e44f5..d259c782d742873f0e0c53b1a43e7bcd85069286 100644 (file)
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -7,5 +7,5 @@ config ARCH_SUNXI
        select GENERIC_IRQ_CHIP
        select PINCTRL
        select SPARSE_IRQ
-       select SUNXI_TIMER
-       select PINCTRL_SUNXI
\ No newline at end of file
+       select SUN4I_TIMER
+       select PINCTRL_SUNXI

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index e507ab7df60b88d6bae4a3f69e28d8f6845924cd..9002185a0a1a3b95fe68ccb1e5c94694df320de5 100644 (file)
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -25,7 +25,7 @@ config DW_APB_TIMER_OF
 config ARMADA_370_XP_TIMER
        bool
 
-config SUNXI_TIMER
+config SUN4I_TIMER
        bool
 
 config VT8500_TIMER

diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 4d8283aec5b51286ba3942ce4e3223a9281ab3cf..7d5d23a591d9eef2d1eac0384780e861453bcc53 100644 (file)
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -16,7 +16,7 @@ obj-$(CONFIG_CLKSRC_NOMADIK_MTU)      += nomadik-mtu.o
 obj-$(CONFIG_CLKSRC_DBX500_PRCMU)      += clksrc-dbx500-prcmu.o
 obj-$(CONFIG_ARMADA_370_XP_TIMER)      += time-armada-370-xp.o
 obj-$(CONFIG_ARCH_BCM2835)     += bcm2835_timer.o
-obj-$(CONFIG_SUNXI_TIMER)      += sunxi_timer.o
+obj-$(CONFIG_SUN4I_TIMER)      += sun4i_timer.o
 obj-$(CONFIG_ARCH_TEGRA)       += tegra20_timer.o
 obj-$(CONFIG_VT8500_TIMER)     += vt8500_timer.o
 

diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c
new file mode 100644 (file)
index 0000000..d4674e7
--- /dev/null
+++ b/drivers/clocksource/sun4i_timer.c
@@ -0,0 +1,148 @@
+/*
+ * Allwinner A1X SoCs timer handling.
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Benn Huang <benn@allwinnertech.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqreturn.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#define TIMER_IRQ_EN_REG       0x00
+#define TIMER_IRQ_EN(val)              (1 << val)
+#define TIMER_IRQ_ST_REG       0x04
+#define TIMER_CTL_REG(val)     (0x10 * val + 0x10)
+#define TIMER_CTL_ENABLE               (1 << 0)
+#define TIMER_CTL_AUTORELOAD           (1 << 1)
+#define TIMER_CTL_ONESHOT              (1 << 7)
+#define TIMER_INTVAL_REG(val)  (0x10 * val + 0x14)
+#define TIMER_CNTVAL_REG(val)  (0x10 * val + 0x18)
+
+#define TIMER_SCAL             16
+
+static void __iomem *timer_base;
+
+static void sun4i_clkevt_mode(enum clock_event_mode mode,
+                             struct clock_event_device *clk)
+{
+       u32 u = readl(timer_base + TIMER_CTL_REG(0));
+
+       switch (mode) {
+       case CLOCK_EVT_MODE_PERIODIC:
+               u &= ~(TIMER_CTL_ONESHOT);
+               writel(u | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
+               break;
+
+       case CLOCK_EVT_MODE_ONESHOT:
+               writel(u | TIMER_CTL_ONESHOT, timer_base + TIMER_CTL_REG(0));
+               break;
+       case CLOCK_EVT_MODE_UNUSED:
+       case CLOCK_EVT_MODE_SHUTDOWN:
+       default:
+               writel(u & ~(TIMER_CTL_ENABLE), timer_base + TIMER_CTL_REG(0));
+               break;
+       }
+}
+
+static int sun4i_clkevt_next_event(unsigned long evt,
+                                  struct clock_event_device *unused)
+{
+       u32 u = readl(timer_base + TIMER_CTL_REG(0));
+       writel(evt, timer_base + TIMER_CNTVAL_REG(0));
+       writel(u | TIMER_CTL_ENABLE | TIMER_CTL_AUTORELOAD,
+              timer_base + TIMER_CTL_REG(0));
+
+       return 0;
+}
+
+static struct clock_event_device sun4i_clockevent = {
+       .name = "sun4i_tick",
+       .rating = 300,
+       .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+       .set_mode = sun4i_clkevt_mode,
+       .set_next_event = sun4i_clkevt_next_event,
+};
+
+
+static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
+{
+       struct clock_event_device *evt = (struct clock_event_device *)dev_id;
+
+       writel(0x1, timer_base + TIMER_IRQ_ST_REG);
+       evt->event_handler(evt);
+
+       return IRQ_HANDLED;
+}
+
+static struct irqaction sun4i_timer_irq = {
+       .name = "sun4i_timer0",
+       .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+       .handler = sun4i_timer_interrupt,
+       .dev_id = &sun4i_clockevent,
+};
+
+static void __init sun4i_timer_init(struct device_node *node)
+{
+       unsigned long rate = 0;
+       struct clk *clk;
+       int ret, irq;
+       u32 val;
+
+       timer_base = of_iomap(node, 0);
+       if (!timer_base)
+               panic("Can't map registers");
+
+       irq = irq_of_parse_and_map(node, 0);
+       if (irq <= 0)
+               panic("Can't parse IRQ");
+
+       clk = of_clk_get(node, 0);
+       if (IS_ERR(clk))
+               panic("Can't get timer clock");
+
+       rate = clk_get_rate(clk);
+
+       writel(rate / (TIMER_SCAL * HZ),
+              timer_base + TIMER_INTVAL_REG(0));
+
+       /* set clock source to HOSC, 16 pre-division */
+       val = readl(timer_base + TIMER_CTL_REG(0));
+       val &= ~(0x07 << 4);
+       val &= ~(0x03 << 2);
+       val |= (4 << 4) | (1 << 2);
+       writel(val, timer_base + TIMER_CTL_REG(0));
+
+       /* set mode to auto reload */
+       val = readl(timer_base + TIMER_CTL_REG(0));
+       writel(val | TIMER_CTL_AUTORELOAD, timer_base + TIMER_CTL_REG(0));
+
+       ret = setup_irq(irq, &sun4i_timer_irq);
+       if (ret)
+               pr_warn("failed to setup irq %d\n", irq);
+
+       /* Enable timer0 interrupt */
+       val = readl(timer_base + TIMER_IRQ_EN_REG);
+       writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
+
+       sun4i_clockevent.cpumask = cpumask_of(0);
+
+       clockevents_config_and_register(&sun4i_clockevent, rate / TIMER_SCAL,
+                                       0x1, 0xff);
+}
+CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
+                      sun4i_timer_init);

diff --git a/drivers/clocksource/sunxi_timer.c b/drivers/clocksource/sunxi_timer.c
deleted file mode 100644 (file)
index 308bbe3..0000000
--- a/drivers/clocksource/sunxi_timer.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Allwinner A1X SoCs timer handling.
- *
- * Copyright (C) 2012 Maxime Ripard
- *
- * Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * Based on code from
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Benn Huang <benn@allwinnertech.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/clk.h>
-#include <linux/clockchips.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/irqreturn.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-
-#define TIMER_IRQ_EN_REG       0x00
-#define TIMER_IRQ_EN(val)              (1 << val)
-#define TIMER_IRQ_ST_REG       0x04
-#define TIMER_CTL_REG(val)     (0x10 * val + 0x10)
-#define TIMER_CTL_ENABLE               (1 << 0)
-#define TIMER_CTL_AUTORELOAD           (1 << 1)
-#define TIMER_CTL_ONESHOT              (1 << 7)
-#define TIMER_INTVAL_REG(val)  (0x10 * val + 0x14)
-#define TIMER_CNTVAL_REG(val)  (0x10 * val + 0x18)
-
-#define TIMER_SCAL             16
-
-static void __iomem *timer_base;
-
-static void sunxi_clkevt_mode(enum clock_event_mode mode,
-                             struct clock_event_device *clk)
-{
-       u32 u = readl(timer_base + TIMER_CTL_REG(0));
-
-       switch (mode) {
-       case CLOCK_EVT_MODE_PERIODIC:
-               u &= ~(TIMER_CTL_ONESHOT);
-               writel(u | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
-               break;
-
-       case CLOCK_EVT_MODE_ONESHOT:
-               writel(u | TIMER_CTL_ONESHOT, timer_base + TIMER_CTL_REG(0));
-               break;
-       case CLOCK_EVT_MODE_UNUSED:
-       case CLOCK_EVT_MODE_SHUTDOWN:
-       default:
-               writel(u & ~(TIMER_CTL_ENABLE), timer_base + TIMER_CTL_REG(0));
-               break;
-       }
-}
-
-static int sunxi_clkevt_next_event(unsigned long evt,
-                                  struct clock_event_device *unused)
-{
-       u32 u = readl(timer_base + TIMER_CTL_REG(0));
-       writel(evt, timer_base + TIMER_CNTVAL_REG(0));
-       writel(u | TIMER_CTL_ENABLE | TIMER_CTL_AUTORELOAD,
-              timer_base + TIMER_CTL_REG(0));
-
-       return 0;
-}
-
-static struct clock_event_device sunxi_clockevent = {
-       .name = "sunxi_tick",
-       .rating = 300,
-       .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-       .set_mode = sunxi_clkevt_mode,
-       .set_next_event = sunxi_clkevt_next_event,
-};
-
-
-static irqreturn_t sunxi_timer_interrupt(int irq, void *dev_id)
-{
-       struct clock_event_device *evt = (struct clock_event_device *)dev_id;
-
-       writel(0x1, timer_base + TIMER_IRQ_ST_REG);
-       evt->event_handler(evt);
-
-       return IRQ_HANDLED;
-}
-
-static struct irqaction sunxi_timer_irq = {
-       .name = "sunxi_timer0",
-       .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-       .handler = sunxi_timer_interrupt,
-       .dev_id = &sunxi_clockevent,
-};
-
-static void __init sunxi_timer_init(struct device_node *node)
-{
-       unsigned long rate = 0;
-       struct clk *clk;
-       int ret, irq;
-       u32 val;
-
-       timer_base = of_iomap(node, 0);
-       if (!timer_base)
-               panic("Can't map registers");
-
-       irq = irq_of_parse_and_map(node, 0);
-       if (irq <= 0)
-               panic("Can't parse IRQ");
-
-       clk = of_clk_get(node, 0);
-       if (IS_ERR(clk))
-               panic("Can't get timer clock");
-
-       rate = clk_get_rate(clk);
-
-       writel(rate / (TIMER_SCAL * HZ),
-              timer_base + TIMER_INTVAL_REG(0));
-
-       /* set clock source to HOSC, 16 pre-division */
-       val = readl(timer_base + TIMER_CTL_REG(0));
-       val &= ~(0x07 << 4);
-       val &= ~(0x03 << 2);
-       val |= (4 << 4) | (1 << 2);
-       writel(val, timer_base + TIMER_CTL_REG(0));
-
-       /* set mode to auto reload */
-       val = readl(timer_base + TIMER_CTL_REG(0));
-       writel(val | TIMER_CTL_AUTORELOAD, timer_base + TIMER_CTL_REG(0));
-
-       ret = setup_irq(irq, &sunxi_timer_irq);
-       if (ret)
-               pr_warn("failed to setup irq %d\n", irq);
-
-       /* Enable timer0 interrupt */
-       val = readl(timer_base + TIMER_IRQ_EN_REG);
-       writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
-
-       sunxi_clockevent.cpumask = cpumask_of(0);
-
-       clockevents_config_and_register(&sunxi_clockevent, rate / TIMER_SCAL,
-                                       0x1, 0xff);
-}
-CLOCKSOURCE_OF_DECLARE(sunxi, "allwinner,sunxi-timer",
-                      sunxi_timer_init);