net: dsa: mv88e6xxx: factorize GLOBAL_CONTROL setup
authorVivien Didelot <vivien.didelot@savoirfairelinux.com>
Mon, 9 May 2016 17:22:51 +0000 (13:22 -0400)
committerDavid S. Miller <davem@davemloft.net>
Mon, 9 May 2016 18:26:11 +0000 (14:26 -0400)
All switch models configure the GLOBAL_CONTROL register with slightly
differences.

Discarding packets with excessive collisions
(GLOBAL_CONTROL_DISCARD_EXCESS) is specific to 6352 and similar
switches, and setting a maximum frame size
(GLOBAL_CONTROL_MAX_FRAME_1632) is specific to 6185 and similar
switches.

As we are centralizing the chips setup, skip these settings and don't
discard any frames yet, until we found out that such discarding by the
hardware is necessary.

Assume a common setup to enable the PHY Polling Unit if present, don't
discard any packets, and mask all interrupt sources.

Tested on 88E6352 and 88E6185.

Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/dsa/mv88e6123.c
drivers/net/dsa/mv88e6131.c
drivers/net/dsa/mv88e6171.c
drivers/net/dsa/mv88e6352.c
drivers/net/dsa/mv88e6xxx.c

index d74695ac0be68c19f1a18407498279005b379a35..1cd30ac19c1a8f63435b4ba547d2a9027e31adbb 100644 (file)
@@ -58,14 +58,6 @@ static int mv88e6123_setup_global(struct dsa_switch *ds)
        int ret;
        u32 reg;
 
-       /* Disable the PHY polling unit (since there won't be any
-        * external PHYs to poll), don't discard packets with
-        * excessive collisions, and mask all interrupt sources.
-        */
-       ret = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL, 0x0000);
-       if (ret)
-               return ret;
-
        /* Configure the upstream port, and configure the upstream
         * port as the port to which ingress and egress monitor frames
         * are to be sent.
index e22ca7b7fa5136d711e2ee3f945b4a8cd07fbf77..d05fc7980e0cbf11f5699fd0d84d6d8032493eb5 100644 (file)
@@ -65,17 +65,6 @@ static int mv88e6131_setup_global(struct dsa_switch *ds)
        int ret;
        u32 reg;
 
-       /* Enable the PHY polling unit, don't discard packets with
-        * excessive collisions, use a weighted fair queueing scheme
-        * to arbitrate between packet queues, set the maximum frame
-        * size to 1632, and mask all interrupt sources.
-        */
-       ret = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL,
-                                 GLOBAL_CONTROL_PPU_ENABLE |
-                                 GLOBAL_CONTROL_MAX_FRAME_1632);
-       if (ret)
-               return ret;
-
        /* Set the VLAN ethertype to 0x8100. */
        ret = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CORE_TAG_TYPE, 0x8100);
        if (ret)
index 4bbf2e1a90aa2328f93e54580637761fb4940e81..6c8554ce24e66d3ad56e84ce1320c74ad8db653f 100644 (file)
@@ -65,15 +65,6 @@ static int mv88e6171_setup_global(struct dsa_switch *ds)
        int ret;
        u32 reg;
 
-       /* Discard packets with excessive collisions, mask all
-        * interrupt sources, enable PPU.
-        */
-       ret = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL,
-                                 GLOBAL_CONTROL_PPU_ENABLE |
-                                 GLOBAL_CONTROL_DISCARD_EXCESS);
-       if (ret)
-               return ret;
-
        /* Configure the upstream port, and configure the upstream
         * port as the port to which ingress and egress monitor frames
         * are to be sent.
index 3e0be872df954b10c2fee55b8ce5fc1750a18843..a27616c00ad6cea669993904d517ad28b0ee989a 100644 (file)
@@ -84,15 +84,6 @@ static int mv88e6352_setup_global(struct dsa_switch *ds)
        int ret;
        u32 reg;
 
-       /* Discard packets with excessive collisions,
-        * mask all interrupt sources, enable PPU (bit 14, undocumented).
-        */
-       ret = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL,
-                                 GLOBAL_CONTROL_PPU_ENABLE |
-                                 GLOBAL_CONTROL_DISCARD_EXCESS);
-       if (ret)
-               return ret;
-
        /* Configure the upstream port, and configure the upstream
         * port as the port to which ingress and egress monitor frames
         * are to be sent.
index 32b36a8fb446f47effc3819edee8de1f8610bbf2..f1cd66073bf7ac453a9290a113ba252ce6237d9c 100644 (file)
@@ -2922,9 +2922,22 @@ int mv88e6xxx_setup_ports(struct dsa_switch *ds)
 
 static int mv88e6xxx_setup_global(struct mv88e6xxx_priv_state *ps)
 {
+       u16 reg;
        int err;
        int i;
 
+       /* Enable the PHY Polling Unit if present, don't discard any packets,
+        * and mask all interrupt sources.
+        */
+       reg = 0;
+       if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU) ||
+           mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU_ACTIVE))
+               reg |= GLOBAL_CONTROL_PPU_ENABLE;
+
+       err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL, reg);
+       if (err)
+               return err;
+
        /* Set the default address aging time to 5 minutes, and
         * enable address learn messages to be sent to all message
         * ports.