vlock: for support double frq out [1/1]

PD#SWPL-12698

Problem:
Add feature for support input 25Hz, 30Hz

Solution:
Add feature for support input 25Hz, 30Hz

Verify:
tl1

Change-Id: I753547078e26b77edd6e69f452afcd9d49a17063
Signed-off-by: Yong Qin <yong.qin@amlogic.com>

diff --git a/arch/arm/boot/dts/amlogic/tl1_t962x2_t309.dts b/arch/arm/boot/dts/amlogic/tl1_t962x2_t309.dts
index 3f8a6a540aced8ac2d741d0b5b35de66cb195612..5d03e0115fa5e1e0d80cea29a57def813895a3e0 100644 (file)
--- a/arch/arm/boot/dts/amlogic/tl1_t962x2_t309.dts
+++ b/arch/arm/boot/dts/amlogic/tl1_t962x2_t309.dts
@@ -505,7 +505,7 @@
        };
 
        amlvecm {
-               compatible = "amlogic, vecm";
+               compatible = "amlogic, vecm-tl1";
                dev_name = "aml_vecm";
                status = "okay";
                gamma_en = <1>;/*1:enabel ;0:disable*/

diff --git a/arch/arm/boot/dts/amlogic/tm2_t962x3_ab301.dts b/arch/arm/boot/dts/amlogic/tm2_t962x3_ab301.dts
index 4e049f4230351347555314422a7d69d94849199d..03882c921d7e6bd8ce4202d4927e7444e23825a3 100644 (file)
--- a/arch/arm/boot/dts/amlogic/tm2_t962x3_ab301.dts
+++ b/arch/arm/boot/dts/amlogic/tm2_t962x3_ab301.dts
@@ -510,7 +510,7 @@
        };
 
        amlvecm {
-               compatible = "amlogic, vecm-tl1";
+               compatible = "amlogic, vecm-tm2";
                dev_name = "aml_vecm";
                status = "okay";
                gamma_en = <1>;/*1:enabel ;0:disable*/

diff --git a/arch/arm/boot/dts/amlogic/tm2_t962x3_t312.dts b/arch/arm/boot/dts/amlogic/tm2_t962x3_t312.dts
index 45b567e72f282be728517077e2216276f0600571..70a351994c820eb9349ac25ed5313582395a4d66 100644 (file)
--- a/arch/arm/boot/dts/amlogic/tm2_t962x3_t312.dts
+++ b/arch/arm/boot/dts/amlogic/tm2_t962x3_t312.dts
@@ -516,7 +516,7 @@
        };
 
        amlvecm {
-               compatible = "amlogic, vecm-tl1";
+               compatible = "amlogic, vecm-tm2";
                dev_name = "aml_vecm";
                status = "okay";
                gamma_en = <1>;/*1:enabel ;0:disable*/

diff --git a/arch/arm64/boot/dts/amlogic/tl1_t962x2_t309.dts b/arch/arm64/boot/dts/amlogic/tl1_t962x2_t309.dts
index 98f994d0d1a734adf957c11e6822503c3aefe295..8d62ed6bbe8f80586a96c1fff7017dcdac06e0cf 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/tl1_t962x2_t309.dts
+++ b/arch/arm64/boot/dts/amlogic/tl1_t962x2_t309.dts
@@ -503,7 +503,7 @@
        };
 
        amlvecm {
-               compatible = "amlogic, vecm";
+               compatible = "amlogic, vecm-tl1";
                dev_name = "aml_vecm";
                status = "okay";
                gamma_en = <1>;/*1:enabel ;0:disable*/

diff --git a/arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_1g.dts b/arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_1g.dts
index e9c4c29c5e7687d6b867ec7ab08efc03a4ca82ce..f12baa32970530fd39120cbfcbb6d01789e8add1 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_1g.dts
+++ b/arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_1g.dts
@@ -520,7 +520,7 @@
        };
 
        amlvecm {
-               compatible = "amlogic, vecm";
+               compatible = "amlogic, vecm-tl1";
                dev_name = "aml_vecm";
                status = "okay";
                gamma_en = <1>;/*1:enabel ;0:disable*/

diff --git a/arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_2g.dts b/arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_2g.dts
index 5871b9a409b8c69b8d954a9188838fcfa927e548..2de9b760a5fc7a2ed1328b07dccf5d21d1e0ef5b 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_2g.dts
+++ b/arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_2g.dts
@@ -514,7 +514,7 @@
        };
 
        amlvecm {
-               compatible = "amlogic, vecm";
+               compatible = "amlogic, vecm-tl1";
                dev_name = "aml_vecm";
                status = "okay";
                gamma_en = <1>;/*1:enabel ;0:disable*/

diff --git a/arch/arm64/boot/dts/amlogic/tm2_t962x3_ab301.dts b/arch/arm64/boot/dts/amlogic/tm2_t962x3_ab301.dts
index 65f63f90c310cfc772b468bb6cfccdaefa700c1b..8d23cee950051e846f5687de889a669a6ffb1c52 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/tm2_t962x3_ab301.dts
+++ b/arch/arm64/boot/dts/amlogic/tm2_t962x3_ab301.dts
@@ -508,7 +508,7 @@
        };
 
        amlvecm {
-               compatible = "amlogic, vecm";
+               compatible = "amlogic, vecm-tm2";
                dev_name = "aml_vecm";
                status = "okay";
                gamma_en = <1>;/*1:enabel ;0:disable*/

diff --git a/drivers/amlogic/media/enhancement/amvecm/amvecm.c b/drivers/amlogic/media/enhancement/amvecm/amvecm.c
index 8deeedda55f9b845ed693c2f92d9116785091923..860c7e55fa5d990a3c4b9f94dd1b387b1905fde6 100644 (file)
--- a/drivers/amlogic/media/enhancement/amvecm/amvecm.c
+++ b/drivers/amlogic/media/enhancement/amvecm/amvecm.c
@@ -6799,7 +6799,7 @@ static const struct vecm_match_data_s vecm_dt_tl1 = {
 };
 
 static const struct vecm_match_data_s vecm_dt_sm1 = {
-       .vlk_support = true,
+       .vlk_support = false,
        .vlk_new_fsm = 1,
        .vlk_hwver = vlock_hw_ver2,
        .vlk_phlock_en = false,
@@ -6807,7 +6807,7 @@ static const struct vecm_match_data_s vecm_dt_sm1 = {
 };
 
 static const struct vecm_match_data_s vecm_dt_tm2 = {
-       .vlk_support = true,
+       .vlk_support = false,
        .vlk_new_fsm = 1,
        .vlk_hwver = vlock_hw_ver2,
        .vlk_phlock_en = false,
@@ -6823,6 +6823,10 @@ static const struct of_device_id aml_vecm_dt_match[] = {
                .compatible = "amlogic, vecm-tl1",
                .data = &vecm_dt_tl1,
        },
+       {
+               .compatible = "amlogic, vecm-sm1",
+               .data = &vecm_dt_sm1,
+       },
        {
                .compatible = "amlogic, vecm-tm2",
                .data = &vecm_dt_tm2,

diff --git a/drivers/amlogic/media/enhancement/amvecm/vlock.c b/drivers/amlogic/media/enhancement/amvecm/vlock.c
index d6b5d389862d90be9f537362cc728010f894237c..7d973d44ae500e3defe5a7059fb8eb1ce0080512 100644 (file)
--- a/drivers/amlogic/media/enhancement/amvecm/vlock.c
+++ b/drivers/amlogic/media/enhancement/amvecm/vlock.c
@@ -484,9 +484,15 @@ static void vlock_setting(struct vframe_s *vf,
                                WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
                                                1, 28, 1);
                } else {
-                       if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1))
-                               WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
-                                               1, 28, 1);
+                       if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) {
+                               if ((input_hz > 0) && (output_hz > 0) &&
+                                   (input_hz * 2 == output_hz))
+                                       WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
+                                                          0, 28, 1);
+                               else
+                                       WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
+                                                          1, 28, 1);
+                       }
                }
                freq_hz = input_hz | (output_hz << 8);
                WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL, freq_hz, 0, 16);
@@ -494,9 +500,14 @@ static void vlock_setting(struct vframe_s *vf,
                 *Ifrm_cnt_mod:0x3001(bit23~16);
                 *(output_freq/input_freq)*Ifrm_cnt_mod must be integer
                 */
-               if (vlock_adapt == 0)
-                       WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL, 1, 16, 8);
-               else
+               if (vlock_adapt == 0) {
+                       if ((output_hz > 0) && (input_hz > 0))
+                               WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
+                                                  output_hz / input_hz, 16, 8);
+                       else
+                               WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
+                                                  1, 16, 8);
+               } else
                        WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
                                input_hz, 16, 8);
                temp_value = READ_VPP_REG(enc_max_line_addr);
@@ -539,9 +550,15 @@ static void vlock_setting(struct vframe_s *vf,
                                WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
                                                1, 28, 1);
                } else {
-                       if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1))
-                               WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
-                                               1, 28, 1);
+                       if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) {
+                               if ((input_hz > 0) && (output_hz > 0) &&
+                                   (input_hz * 2 == output_hz))
+                                       WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
+                                                          0, 28, 1);
+                               else
+                                       WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
+                                                          1, 28, 1);
+                       }
                }
                freq_hz = input_hz | (output_hz << 8);
                WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL, freq_hz, 0, 16);
@@ -550,7 +567,12 @@ static void vlock_setting(struct vframe_s *vf,
                 *(output_freq/input_freq)*Ifrm_cnt_mod must be integer
                 */
                if (vlock_adapt == 0)
-                       WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL, 1, 16, 8);
+                       if ((output_hz > 0) && (input_hz > 0))
+                               WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
+                                                  output_hz / input_hz, 16, 8);
+                       else
+                               WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
+                                                  1, 16, 8);
                else
                        WRITE_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL,
                                input_hz, 16, 8);
@@ -1070,6 +1092,10 @@ static void vlock_enable_step3_soft_enc(void)
                return;
        }
        ia = (READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST) + last_i_vsync + 1) / 2;
+       /*for 25Hz->50Hz, 30Hz->60Hz*/
+       if (READ_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL, 16, 8) == 2)
+               ia = ia / 2;
+
        oa = READ_VPP_REG(VPU_VLOCK_RO_VS_O_DIST);
 
        if ((ia == 0) || (oa == 0)) {
@@ -1280,7 +1306,12 @@ static void vlock_enable_step3_pll(void)
                ia = READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST) / 2;
        else
                ia = READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST);
+       /*for 25Hz->50Hz, 30Hz->60Hz*/
+       if (READ_VPP_REG_BITS(VPU_VLOCK_MISC_CTRL, 16, 8) == 2)
+               ia = ia / 2;
+
        oa = READ_VPP_REG(VPU_VLOCK_RO_VS_O_DIST);
+
        abs_cnt = abs(ia - oa);
        if (abs_cnt > (oa / 3)) {
                if (vlock_debug & VLOCK_DEBUG_INFO)
@@ -1730,8 +1761,7 @@ void vlock_dt_match_init(struct vecm_match_data_s *pdata)
 
 void vlock_set_phase(u32 percent)
 {
-       u32 vs_i_val = READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST);
-       /*u32 vs_o_val = READ_VPP_REG(VPU_VLOCK_RO_VS_O_DIST);*/
+       u32 ia = READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST);
        u32 data = 0;
 
        if (!vlock.phlock_en)
@@ -1743,7 +1773,7 @@ void vlock_set_phase(u32 percent)
        }
 
        vlock.phlock_percent = percent;
-       data = (vs_i_val * (100 + vlock.phlock_percent))/200;
+       data = (ia * (100 + vlock.phlock_percent)) / 200;
        WRITE_VPP_REG(VPU_VLOCK_LOOP1_PHSDIF_TGT, data);
 
        vlock_reset(1);
@@ -1784,16 +1814,13 @@ void vlock_phaselock_check(struct stvlock_sig_sts *pvlock,
 {
        /*vs_i*/
        u32 ia = READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST);
-       u32 oa = READ_VPP_REG(VPU_VLOCK_RO_VS_O_DIST);
        u32 val, pre;
 
        if (vlock.phlock_en) {
                if ((pvlock->frame_cnt_in % 20) == 0) {
-                       /*ia = READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST);*/
-                       ia = (ia + oa) / 2;
                        pre = READ_VPP_REG(VPU_VLOCK_LOOP1_PHSDIF_TGT);
                        val = (ia * (100 + vlock.phlock_percent))/200;
-                       if (val != pre) {
+                       if (abs(val - pre) > 5) {
                                WRITE_VPP_REG(VPU_VLOCK_LOOP1_PHSDIF_TGT, val);
                                vlock_reset(1);
                                vlock_reset(0);
@@ -1875,18 +1902,29 @@ u32 vlock_fsm_check_support(struct stvlock_sig_sts *pvlock,
                struct vframe_s *vf, struct vinfo_s *vinfo)
 {
        u32 ret = true;
-
-       if (((pvlock->input_hz != pvlock->output_hz) && (vlock_adapt == 0)) ||
-               (pvlock->input_hz == 0) || (pvlock->output_hz == 0) ||
+       u32 vs_support = false;
+
+       /* ex:30Hz->30Hz 50Hz->50Hz ...*/
+       if ((pvlock->input_hz > 0) &&
+           (pvlock->input_hz == pvlock->output_hz))
+               vs_support = true;
+       /* ex:30Hz->60Hz 25Hz->50Hz */
+       if ((pvlock->input_hz > 0) &&
+           (pvlock->input_hz * 2 == pvlock->output_hz))
+               vs_support = true;
+
+       if ((!vs_support && (vlock_adapt == 0)) ||
+           (pvlock->input_hz == 0) || (pvlock->output_hz == 0) ||
                (((vf->type_original & VIDTYPE_TYPEMASK)
                        != VIDTYPE_PROGRESSIVE) &&
                        is_meson_txlx_package_962E())) {
 
                if (vlock_debug & VLOCK_DEBUG_INFO) {
-                       pr_info("[%s] for no support case!!!\n",
-                               __func__);
-                       pr_info("input_hz:%d, output_hz:%d\n",
-                               pvlock->input_hz, pvlock->output_hz);
+                       pr_info("[%s] for no support case!!! vf:0x%x\n",
+                               __func__, vf->type_original);
+                       pr_info("vs_sup:%d input_hz:%d, output_hz:%d\n",
+                               vs_support, pvlock->input_hz,
+                               pvlock->output_hz);
                        pr_info("type_original:0x%x\n", vf->type_original);
                }
                ret = false;
@@ -1899,8 +1937,12 @@ u32 vlock_fsm_check_support(struct stvlock_sig_sts *pvlock,
                ret = false;
        }
 
-       if (vinfo->fr_adj_type == VOUT_FR_ADJ_NONE)
+       if (vinfo->fr_adj_type == VOUT_FR_ADJ_NONE) {
+               if (vlock_debug & VLOCK_DEBUG_INFO)
+                       pr_info("[%s] for adj_type VOUT_FR_ADJ_NONE!!!\n",
+                               __func__);
                ret = false;
+       }
 
        return ret;
 }
@@ -2584,6 +2626,7 @@ void vlock_param_config(struct device_node *node)
                vlock_line_limit = val;
 
 #ifdef CONFIG_AMLOGIC_LCD
+       /* lock vlock config data from LCD module */
        schedule_work(&aml_lcd_vlock_param_work);
 #endif
 

diff --git a/drivers/amlogic/media/enhancement/amvecm/vlock.h b/drivers/amlogic/media/enhancement/amvecm/vlock.h
index 63aced0a287928182de45fa21c70d23befd7b3a2..7eb6a7dd400e03e9e2d1dc33ba4f4a2ae933add2 100644 (file)
--- a/drivers/amlogic/media/enhancement/amvecm/vlock.h
+++ b/drivers/amlogic/media/enhancement/amvecm/vlock.h
@@ -23,7 +23,7 @@
 #include <linux/amlogic/media/vfm/vframe.h>
 #include "linux/amlogic/media/amvecm/ve.h"
 
-#define VLOCK_VER "Ref.2019/7/29:FR_ADJ_NONE not support vlock"
+#define VLOCK_VER "Ref.2019/8/18:vlock for double frq out"
 
 #define VLOCK_REG_NUM  33