MIPS: genex: Indent delay slots & clean whitespace

Various branches and jumps in noreorder parts of genex.S don't have
their delay slot instructions indented conventionally with the extra
space.

Fix these, as well as various other inconsistent whitespace problems in
this file, such as spaces used after some opcodes instead of a tab.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13196/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index bff9644b9ad1ae94d7fa4b935dd5fb72f3147073..17326a90d53c7187111b8c5b0b15144844d0e07f 100644 (file)
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -130,7 +130,7 @@ LEAF(__r4k_wait)
        /* end of rollback region (the region size must be power of two) */
 1:
        jr      ra
-       nop
+        nop
        .set    pop
        END(__r4k_wait)
 
@@ -172,7 +172,7 @@ NESTED(handle_int, PT_SIZE, sp)
        mfc0    k0, CP0_EPC
        .set    noreorder
        j       k0
-       rfe
+        rfe
 #else
        and     k0, ST0_IE
        bnez    k0, 1f
@@ -189,7 +189,7 @@ NESTED(handle_int, PT_SIZE, sp)
        LONG_L  s0, TI_REGS($28)
        LONG_S  sp, TI_REGS($28)
        PTR_LA  ra, ret_from_irq
-       PTR_LA  v0, plat_irq_dispatch
+       PTR_LA  v0, plat_irq_dispatch
        jr      v0
 #ifdef CONFIG_CPU_MICROMIPS
        nop
@@ -292,7 +292,7 @@ ejtag_return:
        MFC0    k0, CP0_DESAVE
        .set    mips32
        deret
-       .set pop
+       .set    pop
        END(ejtag_debug_handler)
 
 /*
@@ -329,10 +329,10 @@ NESTED(nmi_handler, PT_SIZE, sp)
         * Clear BEV - required for page fault exception handler to work
         */
        mfc0    k0, CP0_STATUS
-       ori     k0, k0, ST0_EXL
+       ori     k0, k0, ST0_EXL
        li      k1, ~(ST0_BEV | ST0_ERL)
-       and     k0, k0, k1
-       mtc0    k0, CP0_STATUS
+       and     k0, k0, k1
+       mtc0    k0, CP0_STATUS
        _ehb
        SAVE_ALL
        move    a0, sp
@@ -396,7 +396,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
 
        .macro  __BUILD_count exception
        LONG_L  t0,exception_count_\exception
-       LONG_ADDIU t0, 1
+       LONG_ADDIU      t0, 1
        LONG_S  t0,exception_count_\exception
        .comm   exception_count\exception, 8, 8
        .endm
@@ -457,8 +457,8 @@ NESTED(nmi_handler, PT_SIZE, sp)
        MFC0    k1, CP0_ENTRYHI
        andi    k1, MIPS_ENTRYHI_ASID | MIPS_ENTRYHI_ASIDX
        MFC0    k0, CP0_EPC
-       PTR_SRL k0, _PAGE_SHIFT + 1
-       PTR_SLL k0, _PAGE_SHIFT + 1
+       PTR_SRL k0, _PAGE_SHIFT + 1
+       PTR_SLL k0, _PAGE_SHIFT + 1
        or      k1, k0
        MTC0    k1, CP0_ENTRYHI
        mtc0_tlbw_hazard
@@ -478,27 +478,27 @@ NESTED(nmi_handler, PT_SIZE, sp)
        /* microMIPS: 0x007d6b3c: rdhwr v1,$29 */
        MFC0    k1, CP0_EPC
 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS64_R2)
-       and     k0, k1, 1
-       beqz    k0, 1f
-       xor     k1, k0
-       lhu     k0, (k1)
-       lhu     k1, 2(k1)
-       ins     k1, k0, 16, 16
-       lui     k0, 0x007d
-       b       docheck
-       ori     k0, 0x6b3c
+       and     k0, k1, 1
+       beqz    k0, 1f
+        xor    k1, k0
+       lhu     k0, (k1)
+       lhu     k1, 2(k1)
+       ins     k1, k0, 16, 16
+       lui     k0, 0x007d
+       b       docheck
+        ori    k0, 0x6b3c
 1:
-       lui     k0, 0x7c03
-       lw      k1, (k1)
-       ori     k0, 0xe83b
+       lui     k0, 0x7c03
+       lw      k1, (k1)
+       ori     k0, 0xe83b
 #else
-       andi    k0, k1, 1
-       bnez    k0, handle_ri
-       lui     k0, 0x7c03
-       lw      k1, (k1)
-       ori     k0, 0xe83b
+       andi    k0, k1, 1
+       bnez    k0, handle_ri
+        lui    k0, 0x7c03
+       lw      k1, (k1)
+       ori     k0, 0xe83b
 #endif
-       .set    reorder
+       .set    reorder
 docheck:
        bne     k0, k1, handle_ri       /* if not ours */