drm/i915: fix SERR_INT init/reset code

The SERR_INT register is very similar to the other IIR registers, so
let's zero it at preinstall/uninstall and WARN for a non-zero value at
postinstall, just like we do with the other IIR registers. For this
one, there's no need to double-clear since it can't store more than
one interrupt.

v2: - Remove the is_zero assertion (Ben).

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 65e901ed1af8c55f3e34cf8894db21cc422ad8c6..bfb7e14e14df95c6069486a6dd31cc56d84643db 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2872,6 +2872,10 @@ static void ibx_irq_preinstall(struct drm_device *dev)
                return;
 
        GEN5_IRQ_RESET(SDE);
+
+       if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
+               I915_WRITE(SERR_INT, 0xffffffff);
+
        /*
         * SDEIER is also touched by the interrupt handler to work around missed
         * PCH interrupts. Hence we can't update it after the interrupt handler
@@ -3002,14 +3006,11 @@ static void ibx_irq_postinstall(struct drm_device *dev)
        if (HAS_PCH_NOP(dev))
                return;
 
-       if (HAS_PCH_IBX(dev)) {
+       if (HAS_PCH_IBX(dev))
                mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
-       } else {
+       else
                mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
 
-               I915_WRITE(SERR_INT, I915_READ(SERR_INT));
-       }
-
        GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
        I915_WRITE(SDEIMR, ~mask);
 }
@@ -3353,7 +3354,7 @@ static void ironlake_irq_uninstall(struct drm_device *dev)
 
        GEN5_IRQ_RESET(SDE);
        if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
-               I915_WRITE(SERR_INT, I915_READ(SERR_INT));
+               I915_WRITE(SERR_INT, 0xffffffff);
 }
 
 static void i8xx_irq_preinstall(struct drm_device * dev)