drm/radeon: refactor SI tiling table initialization

Simplify the control flow of si_tiling_mode_table_init() similar to how
it was done in gfx_v7_0.c and gfx_v8_0.c.

Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index f878d6962da58b4aed296c22e485846bc14183c4..b3e7c8bf877dd33bcc2cb2d3554a132f61e1fbf2 100644 (file)
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2442,8 +2442,10 @@ void dce6_bandwidth_update(struct radeon_device *rdev)
  */
 static void si_tiling_mode_table_init(struct radeon_device *rdev)
 {
-       const u32 num_tile_mode_states = 32;
-       u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
+       u32 *tile = rdev->config.si.tile_mode_array;
+       const u32 num_tile_mode_states =
+                       ARRAY_SIZE(rdev->config.si.tile_mode_array);
+       u32 reg_offset, split_equal_to_row_size;
 
        switch (rdev->config.si.mem_row_size_in_kb) {
        case 1:
@@ -2458,491 +2460,442 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
                break;
        }
 
-       if ((rdev->family == CHIP_TAHITI) ||
-           (rdev->family == CHIP_PITCAIRN)) {
-               for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
-                       switch (reg_offset) {
-                       case 0:  /* non-AA compressed depth or any compressed stencil */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 1:  /* 2xAA/4xAA compressed depth only */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 2:  /* 8xAA compressed depth only */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 3:  /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 4:  /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 5:  /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(split_equal_to_row_size) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 6:  /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(split_equal_to_row_size) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
-                               break;
-                       case 7:  /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(split_equal_to_row_size) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 8:  /* 1D and 1D Array Surfaces */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 9:  /* Displayable maps. */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 10:  /* Display 8bpp. */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 11:  /* Display 16bpp. */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 12:  /* Display 32bpp. */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
-                               break;
-                       case 13:  /* Thin. */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 14:  /* Thin 8 bpp. */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
-                               break;
-                       case 15:  /* Thin 16 bpp. */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
-                               break;
-                       case 16:  /* Thin 32 bpp. */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
-                               break;
-                       case 17:  /* Thin 64 bpp. */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(split_equal_to_row_size) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
-                               break;
-                       case 21:  /* 8 bpp PRT. */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 22:  /* 16 bpp PRT */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
-                               break;
-                       case 23:  /* 32 bpp PRT */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 24:  /* 64 bpp PRT */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 25:  /* 128 bpp PRT */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
-                                                NUM_BANKS(ADDR_SURF_8_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
-                               break;
-                       default:
-                               gb_tile_moden = 0;
-                               break;
-                       }
-                       rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;
-                       WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
-               }
-       } else if ((rdev->family == CHIP_VERDE) ||
-                  (rdev->family == CHIP_OLAND) ||
-                  (rdev->family == CHIP_HAINAN)) {
-               for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
-                       switch (reg_offset) {
-                       case 0:  /* non-AA compressed depth or any compressed stencil */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P4_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
-                               break;
-                       case 1:  /* 2xAA/4xAA compressed depth only */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P4_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
-                               break;
-                       case 2:  /* 8xAA compressed depth only */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P4_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
-                               break;
-                       case 3:  /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P4_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
-                               break;
-                       case 4:  /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P4_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 5:  /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P4_8x16) |
-                                                TILE_SPLIT(split_equal_to_row_size) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 6:  /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P4_8x16) |
-                                                TILE_SPLIT(split_equal_to_row_size) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 7:  /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P4_8x16) |
-                                                TILE_SPLIT(split_equal_to_row_size) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
-                               break;
-                       case 8:  /* 1D and 1D Array Surfaces */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P4_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 9:  /* Displayable maps. */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P4_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 10:  /* Display 8bpp. */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P4_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
-                               break;
-                       case 11:  /* Display 16bpp. */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P4_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 12:  /* Display 32bpp. */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P4_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 13:  /* Thin. */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P4_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 14:  /* Thin 8 bpp. */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P4_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 15:  /* Thin 16 bpp. */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P4_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 16:  /* Thin 32 bpp. */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P4_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 17:  /* Thin 64 bpp. */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P4_8x16) |
-                                                TILE_SPLIT(split_equal_to_row_size) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 21:  /* 8 bpp PRT. */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 22:  /* 16 bpp PRT */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
-                               break;
-                       case 23:  /* 32 bpp PRT */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 24:  /* 64 bpp PRT */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
-                                                NUM_BANKS(ADDR_SURF_16_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
-                               break;
-                       case 25:  /* 128 bpp PRT */
-                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
-                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
-                                                NUM_BANKS(ADDR_SURF_8_BANK) |
-                                                BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
-                               break;
-                       default:
-                               gb_tile_moden = 0;
-                               break;
-                       }
-                       rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;
-                       WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
-               }
-       } else
+       for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
+               tile[reg_offset] = 0;
+
+       switch(rdev->family) {
+       case CHIP_TAHITI:
+       case CHIP_PITCAIRN:
+               /* non-AA compressed depth or any compressed stencil */
+               tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* 2xAA/4xAA compressed depth only */
+               tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* 8xAA compressed depth only */
+               tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
+               tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
+               tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
+               tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(split_equal_to_row_size) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
+               tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(split_equal_to_row_size) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
+               /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
+               tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(split_equal_to_row_size) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* 1D and 1D Array Surfaces */
+               tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
+                          MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* Displayable maps. */
+               tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* Display 8bpp. */
+               tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* Display 16bpp. */
+               tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* Display 32bpp. */
+               tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
+               /* Thin. */
+               tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* Thin 8 bpp. */
+               tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
+               /* Thin 16 bpp. */
+               tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
+               /* Thin 32 bpp. */
+               tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
+               /* Thin 64 bpp. */
+               tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(split_equal_to_row_size) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
+               /* 8 bpp PRT. */
+               tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* 16 bpp PRT */
+               tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+               /* 32 bpp PRT */
+               tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* 64 bpp PRT */
+               tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* 128 bpp PRT */
+               tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
+                          NUM_BANKS(ADDR_SURF_8_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
+
+               for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
+                       WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
+               break;
+
+       case CHIP_VERDE:
+       case CHIP_OLAND:
+       case CHIP_HAINAN:
+               /* non-AA compressed depth or any compressed stencil */
+               tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+               /* 2xAA/4xAA compressed depth only */
+               tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+               /* 8xAA compressed depth only */
+               tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+               /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
+               tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+               /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
+               tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
+               tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+                          TILE_SPLIT(split_equal_to_row_size) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
+               tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+                          TILE_SPLIT(split_equal_to_row_size) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
+               tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+                          TILE_SPLIT(split_equal_to_row_size) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+               /* 1D and 1D Array Surfaces */
+               tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
+                          MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* Displayable maps. */
+               tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* Display 8bpp. */
+               tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+               /* Display 16bpp. */
+               tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* Display 32bpp. */
+               tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* Thin. */
+               tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* Thin 8 bpp. */
+               tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* Thin 16 bpp. */
+               tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* Thin 32 bpp. */
+               tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* Thin 64 bpp. */
+               tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+                          TILE_SPLIT(split_equal_to_row_size) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* 8 bpp PRT. */
+               tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* 16 bpp PRT */
+               tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+               /* 32 bpp PRT */
+               tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* 64 bpp PRT */
+               tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+                          NUM_BANKS(ADDR_SURF_16_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+               /* 128 bpp PRT */
+               tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                          MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+                          PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
+                          NUM_BANKS(ADDR_SURF_8_BANK) |
+                          BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                          BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                          MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
+
+               for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
+                       WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
+               break;
+
+       default:
                DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
+       }
 }
 
 static void si_select_se_sh(struct radeon_device *rdev,