drm/amdgpu: add vcn enc rings

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 14be7614c9b3d32b763027e7f06bd5e4108a2cc9..91050ca153e93048fe1003b20f44a6c77251c2de 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -126,6 +126,8 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
 
 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
 {
+       int i;
+
        kfree(adev->vcn.saved_bo);
 
        amd_sched_entity_fini(&adev->vcn.ring_dec.sched, &adev->vcn.entity_dec);
@@ -138,6 +140,9 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
 
        amdgpu_ring_fini(&adev->vcn.ring_dec);
 
+       for (i = 0; i < adev->vcn.num_enc_rings; ++i)
+               amdgpu_ring_fini(&adev->vcn.ring_enc[i]);
+
        release_firmware(adev->vcn.fw);
 
        return 0;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 550656891a8b83175e3d0d8b87310a8b55785a6b..444fed503f4414b1fe046b36efa664db05547672 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -50,7 +50,7 @@ struct amdgpu_vcn {
        struct amdgpu_irq_src   irq;
        struct amd_sched_entity entity_dec;
        struct amd_sched_entity entity_enc;
-       uint32_t                srbm_soft_reset;
+       unsigned                num_enc_rings;
 };
 
 int amdgpu_vcn_sw_init(struct amdgpu_device *adev);

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 2e650685e35af58e3c32dc7289cbd7b1bb62c01e..b8f4e7713921f6fbf9c0ee483b069d493e4fc7bf 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -51,6 +51,8 @@ static int vcn_v1_0_early_init(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+       adev->vcn.num_enc_rings = 2;
+
        vcn_v1_0_set_dec_ring_funcs(adev);
        vcn_v1_0_set_irq_funcs(adev);
 
@@ -67,7 +69,7 @@ static int vcn_v1_0_early_init(void *handle)
 static int vcn_v1_0_sw_init(void *handle)
 {
        struct amdgpu_ring *ring;
-       int r;
+       int i, r;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
        /* VCN TRAP */
@@ -86,6 +88,16 @@ static int vcn_v1_0_sw_init(void *handle)
        ring = &adev->vcn.ring_dec;
        sprintf(ring->name, "vcn_dec");
        r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
+       if (r)
+               return r;
+
+       for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+               ring = &adev->vcn.ring_enc[i];
+               sprintf(ring->name, "vcn_enc%d", i);
+               r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
+               if (r)
+                       return r;
+       }
 
        return r;
 }
@@ -401,6 +413,20 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
        WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
                        ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
 
+       ring = &adev->vcn.ring_enc[0];
+       WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR), lower_32_bits(ring->wptr));
+       WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR), lower_32_bits(ring->wptr));
+       WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO), ring->gpu_addr);
+       WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
+       WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE), ring->ring_size / 4);
+
+       ring = &adev->vcn.ring_enc[1];
+       WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_RPTR2), lower_32_bits(ring->wptr));
+       WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_WPTR2), lower_32_bits(ring->wptr));
+       WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO2), ring->gpu_addr);
+       WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI2), upper_32_bits(ring->gpu_addr));
+       WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE2), ring->ring_size / 4);
+
        return 0;
 }