PCI: Add Downstream Port Containment portdrv service type

Add the Downstream Port Containment (PCIE_PORT_SERVICE_DPC) portdrv service
type, available if the device has the DPC extended capability.

[bhelgaas: split to separate patch, changelog]
Signed-off-by: Keith Busch <keith.busch@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h
index 63cb2ef9c5aebb7907aa71317293b76589dacad0..7d82f6d47e68c105468fcee32fec2ca3f58b88f6 100644 (file)
--- a/drivers/pci/pcie/portdrv.h
+++ b/drivers/pci/pcie/portdrv.h
@@ -11,7 +11,7 @@
 
 #include <linux/compiler.h>
 
-#define PCIE_PORT_DEVICE_MAXSERVICES   4
+#define PCIE_PORT_DEVICE_MAXSERVICES   5
 /*
  * According to the PCI Express Base Specification 2.0, the indices of
  * the MSI-X table entries used by port services must not exceed 31

diff --git a/drivers/pci/pcie/portdrv_acpi.c b/drivers/pci/pcie/portdrv_acpi.c
index b4d2894ee3fc83c8e60a1fc8159452d8a54ad8dd..44296eb729d3b21cb95a1e224721bc2420ef5f15 100644 (file)
--- a/drivers/pci/pcie/portdrv_acpi.c
+++ b/drivers/pci/pcie/portdrv_acpi.c
@@ -51,7 +51,7 @@ int pcie_port_acpi_setup(struct pci_dev *port, int *srv_mask)
 
        flags = root->osc_control_set;
 
-       *srv_mask = PCIE_PORT_SERVICE_VC;
+       *srv_mask = PCIE_PORT_SERVICE_VC | PCIE_PORT_SERVICE_DPC;
        if (flags & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL)
                *srv_mask |= PCIE_PORT_SERVICE_HP;
        if (flags & OSC_PCI_EXPRESS_PME_CONTROL)

diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index 94d3b82415c1357c010c8dda1a0b69000bb5e97b..2ab0f424a3788ba40c00871cf0afb6243194b11b 100644 (file)
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -262,7 +262,7 @@ static int get_port_device_capability(struct pci_dev *dev)
                return 0;
 
        cap_mask = PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP
-                       | PCIE_PORT_SERVICE_VC;
+                       | PCIE_PORT_SERVICE_VC | PCIE_PORT_SERVICE_DPC;
        if (pci_aer_available())
                cap_mask |= PCIE_PORT_SERVICE_AER;
 
@@ -311,6 +311,8 @@ static int get_port_device_capability(struct pci_dev *dev)
                 */
                pcie_pme_interrupt_enable(dev, false);
        }
+       if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC))
+               services |= PCIE_PORT_SERVICE_DPC;
 
        return services;
 }

diff --git a/include/linux/pcieport_if.h b/include/linux/pcieport_if.h
index 4f1089f2cc98b6b4690ac67aedce42ef4350e122..afcd130ab3a914c6a8af4736ae8cdc6cac11b703 100644 (file)
--- a/include/linux/pcieport_if.h
+++ b/include/linux/pcieport_if.h
@@ -21,6 +21,8 @@
 #define PCIE_PORT_SERVICE_HP           (1 << PCIE_PORT_SERVICE_HP_SHIFT)
 #define PCIE_PORT_SERVICE_VC_SHIFT     3       /* Virtual Channel */
 #define PCIE_PORT_SERVICE_VC           (1 << PCIE_PORT_SERVICE_VC_SHIFT)
+#define PCIE_PORT_SERVICE_DPC_SHIFT    4       /* Downstream Port Containment */
+#define PCIE_PORT_SERVICE_DPC          (1 << PCIE_PORT_SERVICE_DPC_SHIFT)
 
 struct pcie_device {
        int             irq;        /* Service IRQ/MSI/MSI-X Vector */

diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 1becea86c73c9d217ef867fac0cce73e075c6427..61e95c14254760bbd66467ae54c60f231f0cfd0f 100644 (file)
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -670,7 +670,8 @@
 #define PCI_EXT_CAP_ID_SECPCI  0x19    /* Secondary PCIe Capability */
 #define PCI_EXT_CAP_ID_PMUX    0x1A    /* Protocol Multiplexing */
 #define PCI_EXT_CAP_ID_PASID   0x1B    /* Process Address Space ID */
-#define PCI_EXT_CAP_ID_MAX     PCI_EXT_CAP_ID_PASID
+#define PCI_EXT_CAP_ID_DPC     0x1D    /* Downstream Port Containment */
+#define PCI_EXT_CAP_ID_MAX     PCI_EXT_CAP_ID_DPC
 
 #define PCI_EXT_CAP_DSN_SIZEOF 12
 #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40