ARM: zynq: use zynq clk bindings

Make the Zynq platform use the newly created zynq clk bindings.

Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 21ed87bc3503fd73dfdbec050183799448ecc2e6..ccfe0ab8c87702076afaf621963c730e1d34be3f 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -959,6 +959,7 @@ config ARCH_ZYNQ
        bool "Xilinx Zynq ARM Cortex A9 Platform"
        select ARM_AMBA
        select ARM_GIC
+       select COMMON_CLK
        select CPU_V7
        select GENERIC_CLOCKEVENTS
        select ICST

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 8b30e596deabfb84a1bd42739af81d962c91ade8..bb3085ca4f068f3d3f3b433bb7c9bef29a92e52a 100644 (file)
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -53,5 +53,61 @@
                        interrupts = <0 50 4>;
                        clock = <50000000>;
                };
+
+               slcr: slcr@f8000000 {
+                       compatible = "xlnx,zynq-slcr";
+                       reg = <0xF8000000 0x1000>;
+
+                       clocks {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               ps_clk: ps_clk {
+                                       #clock-cells = <0>;
+                                       compatible = "fixed-clock";
+                                       /* clock-frequency set in board-specific file */
+                                       clock-output-names = "ps_clk";
+                               };
+                               armpll: armpll {
+                                       #clock-cells = <0>;
+                                       compatible = "xlnx,zynq-pll";
+                                       clocks = <&ps_clk>;
+                                       reg = <0x100 0x110>;
+                                       clock-output-names = "armpll";
+                               };
+                               ddrpll: ddrpll {
+                                       #clock-cells = <0>;
+                                       compatible = "xlnx,zynq-pll";
+                                       clocks = <&ps_clk>;
+                                       reg = <0x104 0x114>;
+                                       clock-output-names = "ddrpll";
+                               };
+                               iopll: iopll {
+                                       #clock-cells = <0>;
+                                       compatible = "xlnx,zynq-pll";
+                                       clocks = <&ps_clk>;
+                                       reg = <0x108 0x118>;
+                                       clock-output-names = "iopll";
+                               };
+                               uart_clk: uart_clk {
+                                       #clock-cells = <1>;
+                                       compatible = "xlnx,zynq-periph-clock";
+                                       clocks = <&iopll &armpll &ddrpll>;
+                                       reg = <0x154>;
+                                       clock-output-names = "uart0_ref_clk",
+                                                            "uart1_ref_clk";
+                               };
+                               cpu_clk: cpu_clk {
+                                       #clock-cells = <1>;
+                                       compatible = "xlnx,zynq-cpu-clock";
+                                       clocks = <&iopll &armpll &ddrpll>;
+                                       reg = <0x120 0x1C4>;
+                                       clock-output-names = "cpu_6x4x",
+                                                            "cpu_3x2x",
+                                                            "cpu_2x",
+                                                            "cpu_1x";
+                               };
+                       };
+               };
        };
 };

diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index e25a307438ad27776f5994ba81ea99e46266dc9e..86f44d5b0265bf8fe3b7c6da4370d409e7f9b7d0 100644 (file)
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -28,3 +28,7 @@
        };
 
 };
+
+&ps_clk {
+       clock-frequency = <33333330>;
+};

diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 5441323e2a6861a6ab2380d6aca548b1d57e65e4..79bf5fb4dad3526a9fd8b63de1c21d5c6536e8c2 100644 (file)
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -19,6 +19,8 @@
 #include <linux/cpumask.h>
 #include <linux/platform_device.h>
 #include <linux/clk.h>
+#include <linux/clk/zynq.h>
+#include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/of.h>
@@ -96,6 +98,15 @@ static struct map_desc io_desc[] __initdata = {
 
 static void __init xilinx_zynq_timer_init(void)
 {
+       struct device_node *np;
+       void __iomem *slcr;
+
+       np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr");
+       slcr = of_iomap(np, 0);
+       WARN_ON(!slcr);
+
+       xilinx_zynq_clocks_init(slcr);
+
        xttcpss_timer_init();
 }
 

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 71a25b91de0099b9375e434a233d48f7b1507929..d35a34c583695850321db97145888358eadb4a83 100644 (file)
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -19,6 +19,7 @@ endif
 obj-$(CONFIG_MACH_LOONGSON1)   += clk-ls1x.o
 obj-$(CONFIG_ARCH_U8500)       += ux500/
 obj-$(CONFIG_ARCH_VT8500)      += clk-vt8500.o
+obj-$(CONFIG_ARCH_ZYNQ)                += clk-zynq.o
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o