#define CX18_DEFAULT_ENC_PCM_BUFFERS 1
/* Maximum firmware DMA buffers per stream */
-#define CX18_MAX_MDLS_PER_STREAM 63
+#define CX18_MAX_FW_MDLS_PER_STREAM 63
/* DMA buffer, default size in kB allocated */
#define CX18_DEFAULT_ENC_TS_BUFSIZE 32
#define CX18_MAX_MDL_ACKS 2
-#define CX18_MAX_EPU_WORK_ORDERS 70 /* CPU_DE_RELEASE_MDL bursts 63 commands */
+#define CX18_MAX_EPU_WORK_ORDERS (CX18_MAX_FW_MDLS_PER_STREAM + 7)
+/* CPU_DE_RELEASE_MDL can burst CX18_MAX_FW_MDLS_PER_STREAM orders in a group */
#define CX18_F_EWO_MB_STALE_UPON_RECEIPT 0x1
#define CX18_F_EWO_MB_STALE_WHILE_PROC 0x2
mutex_lock(&s->qlock);
- /* q_busy is restricted to 63 buffers to stay within firmware limits */
- if (q == &s->q_busy && atomic_read(&q->buffers) >= 63)
+ /* q_busy is restricted to a max buffer count imposed by firmware */
+ if (q == &s->q_busy &&
+ atomic_read(&q->buffers) >= CX18_MAX_FW_MDLS_PER_STREAM)
q = &s->q_free;
if (to_front)
struct cx18_buffer *buf;
if (atomic_read(&s->q_free.buffers) == 0 ||
- atomic_read(&s->q_busy.buffers) >= 63)
+ atomic_read(&s->q_busy.buffers) >= CX18_MAX_FW_MDLS_PER_STREAM)
return;
/* Move from q_free to q_busy notifying the firmware, until the limit */
if (buf == NULL)
break;
q = cx18_stream_put_buf_fw(s, buf);
- } while (atomic_read(&s->q_busy.buffers) < 63 && q == &s->q_busy);
+ } while (atomic_read(&s->q_busy.buffers) < CX18_MAX_FW_MDLS_PER_STREAM
+ && q == &s->q_busy);
}
int cx18_start_v4l2_encode_stream(struct cx18_stream *s)