This results in smaller/faster/simpler code and allows future optimizations.
Also remove no longer needed ide[_mm]_{inl,outl}() and ide_hwif_t.{INL,OUTL}.
v2:
* updated for scc_pata
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
hwif->OUTSW = mm_outsw;
hwif->INW = mm_inw;
hwif->INSW = mm_insw;
- hwif->OUTL = NULL;
- hwif->INL = NULL;
hwif->OUTSL = NULL;
hwif->INSL = NULL;
}
}
/* PRD table */
- hwif->OUTL(hwif->dmatable_dma, hwif->dma_prdtable);
+ if (hwif->mmio == 2)
+ writel(hwif->dmatable_dma, (void __iomem *)hwif->dma_prdtable);
+ else
+ outl(hwif->dmatable_dma, hwif->dma_prdtable);
/* specify r/w */
hwif->OUTB(reading, hwif->dma_command);
insw(port, addr, count);
}
-static u32 ide_inl (unsigned long port)
-{
- return (u32) inl(port);
-}
-
static void ide_insl (unsigned long port, void *addr, u32 count)
{
insl(port, addr, count);
outsw(port, addr, count);
}
-static void ide_outl (u32 val, unsigned long port)
-{
- outl(val, port);
-}
-
static void ide_outsl (unsigned long port, void *addr, u32 count)
{
outsl(port, addr, count);
hwif->OUTB = ide_outb;
hwif->OUTBSYNC = ide_outbsync;
hwif->OUTW = ide_outw;
- hwif->OUTL = ide_outl;
hwif->OUTSW = ide_outsw;
hwif->OUTSL = ide_outsl;
hwif->INB = ide_inb;
hwif->INW = ide_inw;
- hwif->INL = ide_inl;
hwif->INSW = ide_insw;
hwif->INSL = ide_insl;
}
__ide_mm_insw((void __iomem *) port, addr, count);
}
-static u32 ide_mm_inl (unsigned long port)
-{
- return (u32) readl((void __iomem *) port);
-}
-
static void ide_mm_insl (unsigned long port, void *addr, u32 count)
{
__ide_mm_insl((void __iomem *) port, addr, count);
__ide_mm_outsw((void __iomem *) port, addr, count);
}
-static void ide_mm_outl (u32 value, unsigned long port)
-{
- writel(value, (void __iomem *) port);
-}
-
static void ide_mm_outsl (unsigned long port, void *addr, u32 count)
{
__ide_mm_outsl((void __iomem *) port, addr, count);
this one is controller specific! */
hwif->OUTBSYNC = ide_mm_outbsync;
hwif->OUTW = ide_mm_outw;
- hwif->OUTL = ide_mm_outl;
hwif->OUTSW = ide_mm_outsw;
hwif->OUTSL = ide_mm_outsl;
hwif->INB = ide_mm_inb;
hwif->INW = ide_mm_inw;
- hwif->INL = ide_mm_inl;
hwif->INSW = ide_mm_insw;
hwif->INSL = ide_mm_insl;
}
hwif->OUTB = tmp_hwif->OUTB;
hwif->OUTBSYNC = tmp_hwif->OUTBSYNC;
hwif->OUTW = tmp_hwif->OUTW;
- hwif->OUTL = tmp_hwif->OUTL;
hwif->OUTSW = tmp_hwif->OUTSW;
hwif->OUTSL = tmp_hwif->OUTSL;
hwif->INB = tmp_hwif->INB;
hwif->INW = tmp_hwif->INW;
- hwif->INL = tmp_hwif->INL;
hwif->INSW = tmp_hwif->INSW;
hwif->INSL = tmp_hwif->INSL;
current_timing = timing;
if (drive->media != ide_disk || !drive->present)
select |= HT_PREFETCH_MODE;
- (void) HWIF(drive)->INB(HT_CONFIG_PORT);
- (void) HWIF(drive)->INB(HT_CONFIG_PORT);
- (void) HWIF(drive)->INB(HT_CONFIG_PORT);
- (void) HWIF(drive)->INB(HT_CONFIG_PORT);
- HWIF(drive)->OUTB(select, HT_CONFIG_PORT);
+ (void)inb(HT_CONFIG_PORT);
+ (void)inb(HT_CONFIG_PORT);
+ (void)inb(HT_CONFIG_PORT);
+ (void)inb(HT_CONFIG_PORT);
+ outb(select, HT_CONFIG_PORT);
/*
* Set timing for this drive:
*/
- HWIF(drive)->OUTB(timing, IDE_SELECT_REG);
- (void) HWIF(drive)->INB(IDE_STATUS_REG);
+ outb(timing, IDE_SELECT_REG);
+ (void)inb(IDE_STATUS_REG);
#ifdef DEBUG
printk("ht6560b: %s: select=%#x timing=%#x\n",
drive->name, select, timing);
switch(hwif->pci_dev->device) {
case PCI_DEVICE_ID_ARTOP_ATP865:
case PCI_DEVICE_ID_ARTOP_ATP865R:
- mode = (hwif->INB(((hwif->channel) ?
- hwif->mate->dma_status :
- hwif->dma_status)) & 0x10) ? 4 : 3;
+ mode = (inb(hwif->channel ?
+ hwif->mate->dma_status :
+ hwif->dma_status) & 0x10) ? 4 : 3;
break;
case PCI_DEVICE_ID_ARTOP_ATP860:
case PCI_DEVICE_ID_ARTOP_ATP860R:
{
if (m5229_revision < 0x20)
return;
- if (!(hwif->channel))
- hwif->OUTB(hwif->INB(dmabase+2) & 0x60, dmabase+2);
+ if (!hwif->channel)
+ outb(inb(dmabase + 2) & 0x60, dmabase + 2);
ide_setup_dma(hwif, dmabase, 8);
}
drive->waiting_for_dma = 0;
/* read DMA command state */
- dma_cmd = hwif->INB(hwif->dma_command);
+ dma_cmd = inb(hwif->dma_command);
/* stop DMA */
- hwif->OUTB((dma_cmd & ~1), hwif->dma_command);
+ outb(dma_cmd & ~1, hwif->dma_command);
/* get DMA status */
- dma_stat = hwif->INB(hwif->dma_status);
+ dma_stat = inb(hwif->dma_status);
/* clear the INTR & ERROR bits */
- hwif->OUTB(dma_stat|6, hwif->dma_status);
+ outb(dma_stat | 6, hwif->dma_status);
if (cmd64x_alt_dma_status(dev)) {
u8 dma_intr = 0;
u8 dma_mask = (hwif->channel) ? ARTTIM23_INTR_CH1 :
struct pci_dev *dev = hwif->pci_dev;
u8 dma_alt_stat = 0, mask = (hwif->channel) ? MRDMODE_INTR_CH1 :
MRDMODE_INTR_CH0;
- u8 dma_stat = hwif->INB(hwif->dma_status);
+ u8 dma_stat = inb(hwif->dma_status);
(void) pci_read_config_byte(dev, MRDMODE, &dma_alt_stat);
#ifdef DEBUG
drive->waiting_for_dma = 0;
/* get DMA status */
- dma_stat = hwif->INB(hwif->dma_status);
+ dma_stat = inb(hwif->dma_status);
/* read DMA command state */
- dma_cmd = hwif->INB(hwif->dma_command);
+ dma_cmd = inb(hwif->dma_command);
/* stop DMA */
- hwif->OUTB((dma_cmd & ~1), hwif->dma_command);
+ outb(dma_cmd & ~1, hwif->dma_command);
/* clear the INTR & ERROR bits */
- hwif->OUTB(dma_stat|6, hwif->dma_status);
+ outb(dma_stat | 6, hwif->dma_status);
/* and free any DMA resources */
ide_destroy_dmatable(drive);
/* verify good DMA status */
pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
if (!cs5530_set_xfer_mode(drive, modes[pio])) {
- format = (hwif->INL(basereg+4) >> 31) & 1;
- hwif->OUTL(cs5530_pio_timings[format][pio],
+ format = (inl(basereg + 4) >> 31) & 1;
+ outl(cs5530_pio_timings[format][pio],
basereg+(drive->select.b.unit<<3));
}
}
break;
}
basereg = CS5530_BASEREG(hwif);
- reg = hwif->INL(basereg+4); /* get drive0 config register */
+ reg = inl(basereg + 4); /* get drive0 config register */
timings |= reg & 0x80000000; /* preserve PIO format bit */
if (unit == 0) { /* are we configuring drive0? */
- hwif->OUTL(timings, basereg+4); /* write drive0 config register */
+ outl(timings, basereg + 4); /* write drive0 config register */
} else {
if (timings & 0x00100000)
reg |= 0x00100000; /* enable UDMA timings for both drives */
else
reg &= ~0x00100000; /* disable UDMA timings for both drives */
- hwif->OUTL(reg, basereg+4); /* write drive0 config register */
- hwif->OUTL(timings, basereg+12); /* write drive1 config register */
+ outl(reg, basereg + 4); /* write drive0 config register */
+ outl(timings, basereg + 12); /* write drive1 config register */
}
/*
hwif->tuneproc = &cs5530_tuneproc;
basereg = CS5530_BASEREG(hwif);
- d0_timings = hwif->INL(basereg+0);
+ d0_timings = inl(basereg + 0);
if (CS5530_BAD_PIO(d0_timings)) {
/* PIO timings not initialized? */
- hwif->OUTL(cs5530_pio_timings[(d0_timings>>31)&1][0], basereg+0);
+ outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);
if (!hwif->drives[0].autotune)
hwif->drives[0].autotune = 1;
/* needs autotuning later */
}
- if (CS5530_BAD_PIO(hwif->INL(basereg+8))) {
- /* PIO timings not initialized? */
- hwif->OUTL(cs5530_pio_timings[(d0_timings>>31)&1][0], basereg+8);
+ if (CS5530_BAD_PIO(inl(basereg + 8))) {
+ /* PIO timings not initialized? */
+ outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);
if (!hwif->drives[1].autotune)
hwif->drives[1].autotune = 1;
/* needs autotuning later */
#if CY82C693_DEBUG_LOGS
/* for debug let's show the previous values */
- HWIF(drive)->OUTB(index, CY82_INDEX_PORT);
- data = HWIF(drive)->INB(CY82_DATA_PORT);
+ outb(index, CY82_INDEX_PORT);
+ data = inb(CY82_DATA_PORT);
printk (KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n",
drive->name, HWIF(drive)->channel, drive->select.b.unit,
data = (u8)mode|(u8)(single<<2);
- HWIF(drive)->OUTB(index, CY82_INDEX_PORT);
- HWIF(drive)->OUTB(data, CY82_DATA_PORT);
+ outb(index, CY82_INDEX_PORT);
+ outb(data, CY82_DATA_PORT);
#if CY82C693_DEBUG_INFO
printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
*/
data = BUSMASTER_TIMEOUT;
- HWIF(drive)->OUTB(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
- HWIF(drive)->OUTB(data, CY82_DATA_PORT);
+ outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
+ outb(data, CY82_DATA_PORT);
#if CY82C693_DEBUG_INFO
printk (KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
return 0;
}
- dma_stat = hwif->INB(hwif->dma_status);
+ dma_stat = inb(hwif->dma_status);
/* return 1 if INTR asserted */
if (dma_stat & 4)
return 1;
/* get dma command mode */
dma_cmd = hwif->INB(hwif->dma_command);
/* stop DMA */
- hwif->OUTB(dma_cmd & ~1, hwif->dma_command);
+ outb(dma_cmd & ~1, hwif->dma_command);
/* from ERRATA: clear the INTR & ERROR bits */
dma_cmd = hwif->INB(hwif->dma_command);
- hwif->OUTB(dma_cmd|6, hwif->dma_command);
+ outb(dma_cmd | 6, hwif->dma_command);
/* and free any DMA resources */
ide_destroy_dmatable(drive);
/* verify good DMA status */
* to SELECT_DRIVE() properly during first probe_hwif().
*/
timeout = 10000;
- hwif->OUTB(12, hwif->io_ports[IDE_CONTROL_OFFSET]);
+ outb(12, hwif->io_ports[IDE_CONTROL_OFFSET]);
udelay(10);
- hwif->OUTB(8, hwif->io_ports[IDE_CONTROL_OFFSET]);
+ outb(8, hwif->io_ports[IDE_CONTROL_OFFSET]);
do {
udelay(50);
stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]);
if (!hwif->dma_base)
return;
- hwif->OUTB(0x60, hwif->dma_status);
+ outb(0x60, hwif->dma_status);
hwif->dma_setup = &ns87415_ide_dma_setup;
hwif->ide_dma_check = &ns87415_ide_dma_check;
hwif->ide_dma_end = &ns87415_ide_dma_end;
return ((time*bus_speed+999)/1000);
}
-static void write_reg(ide_hwif_t *hwif, u8 value, int reg)
/* Write value to register reg, base of register
* is at reg_base (0x1f0 primary, 0x170 secondary,
* if not changed by PCI configuration).
* This is from setupvic.exe program.
*/
+static void write_reg(u8 value, int reg)
{
- hwif->INW(reg_base+1);
- hwif->INW(reg_base+1);
- hwif->OUTB(3, reg_base+2);
- hwif->OUTB(value, reg_base+reg);
- hwif->OUTB(0x83, reg_base+2);
+ inw(reg_base + 1);
+ inw(reg_base + 1);
+ outb(3, reg_base + 2);
+ outb(value, reg_base + reg);
+ outb(0x83, reg_base + 2);
}
-static u8 read_reg(ide_hwif_t *hwif, int reg)
/* Read value from register reg, base of register
* is at reg_base (0x1f0 primary, 0x170 secondary,
* if not changed by PCI configuration).
* This is from setupvic.exe program.
*/
+static u8 read_reg(int reg)
{
u8 ret = 0;
- hwif->INW(reg_base+1);
- hwif->INW(reg_base+1);
- hwif->OUTB(3, reg_base+2);
- ret = hwif->INB(reg_base+reg);
- hwif->OUTB(0x83, reg_base+2);
+ inw(reg_base + 1);
+ inw(reg_base + 1);
+ outb(3, reg_base + 2);
+ ret = inb(reg_base + reg);
+ outb(0x83, reg_base + 2);
+
return ret;
}
reg_base = hwif->io_ports[IDE_DATA_OFFSET];
/* allow Register-B */
- hwif->OUTB(0xc0, reg_base+CNTRL_REG);
+ outb(0xc0, reg_base + CNTRL_REG);
/* hmm, setupvic.exe does this ;-) */
- hwif->OUTB(0xff, reg_base+5);
+ outb(0xff, reg_base + 5);
/* if reads 0xff, adapter not exist? */
- (void) hwif->INB(reg_base+CNTRL_REG);
+ (void)inb(reg_base + CNTRL_REG);
/* if reads 0xc0, no interface exist? */
- read_reg(hwif, CNTRL_REG);
+ read_reg(CNTRL_REG);
/* read version, probably 0 */
- read_reg(hwif, STRAP_REG);
+ read_reg(STRAP_REG);
/* program primary drive */
- /* select Index-0 for Register-A */
- write_reg(hwif, 0, MISC_REG);
- /* set read cycle timings */
- write_reg(hwif, cycle1, READ_REG);
- /* set write cycle timings */
- write_reg(hwif, cycle1, WRITE_REG);
+ /* select Index-0 for Register-A */
+ write_reg(0, MISC_REG);
+ /* set read cycle timings */
+ write_reg(cycle1, READ_REG);
+ /* set write cycle timings */
+ write_reg(cycle1, WRITE_REG);
/* program secondary drive */
- /* select Index-1 for Register-B */
- write_reg(hwif, 1, MISC_REG);
- /* set read cycle timings */
- write_reg(hwif, cycle2, READ_REG);
- /* set write cycle timings */
- write_reg(hwif, cycle2, WRITE_REG);
+ /* select Index-1 for Register-B */
+ write_reg(1, MISC_REG);
+ /* set read cycle timings */
+ write_reg(cycle2, READ_REG);
+ /* set write cycle timings */
+ write_reg(cycle2, WRITE_REG);
/* use Register-A for drive 0 */
/* use Register-B for drive 1 */
- write_reg(hwif, 0x85, CNTRL_REG);
+ write_reg(0x85, CNTRL_REG);
/* set address setup, DRDY timings, */
/* and read prefetch for both drives */
- write_reg(hwif, misc, MISC_REG);
+ write_reg(misc, MISC_REG);
spin_unlock_irqrestore(&ide_lock, flags);
}
{
u8 value;
- hwif->OUTB(index, hwif->dma_vendor1);
- value = hwif->INB(hwif->dma_vendor3);
+ outb(index, hwif->dma_vendor1);
+ value = inb(hwif->dma_vendor3);
DBG("index[%02X] value[%02X]\n", index, value);
return value;
*/
static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
{
- hwif->OUTB(index, hwif->dma_vendor1);
- hwif->OUTB(value, hwif->dma_vendor3);
+ outb(index, hwif->dma_vendor1);
+ outb(value, hwif->dma_vendor3);
DBG("index[%02X] value[%02X]\n", index, value);
}
static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
{
unsigned long clock_reg = hwif->dma_master + 0x11;
- u8 clock = hwif->INB(clock_reg);
+ u8 clock = inb(clock_reg);
- hwif->OUTB(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
+ outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
}
static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
{
unsigned long clock_reg = hwif->dma_master + 0x11;
- u8 clock = hwif->INB(clock_reg);
+ u8 clock = inb(clock_reg);
- hwif->OUTB(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
+ outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
}
static int config_chipset_for_dma (ide_drive_t *drive)
unsigned long high_16 = hwif->dma_master;
unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
u32 word_count = 0;
- u8 clock = hwif->INB(high_16 + 0x11);
+ u8 clock = inb(high_16 + 0x11);
- hwif->OUTB(clock|(hwif->channel ? 0x08 : 0x02), high_16+0x11);
+ outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
word_count = (rq->nr_sectors << 8);
word_count = (rq_data_dir(rq) == READ) ?
word_count | 0x05000000 :
word_count | 0x06000000;
- hwif->OUTL(word_count, atapi_reg);
+ outl(word_count, atapi_reg);
}
ide_dma_start(drive);
}
unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
u8 clock = 0;
- hwif->OUTL(0, atapi_reg); /* zero out extra */
- clock = hwif->INB(high_16 + 0x11);
- hwif->OUTB(clock & ~(hwif->channel ? 0x08:0x02), high_16+0x11);
+ outl(0, atapi_reg); /* zero out extra */
+ clock = inb(high_16 + 0x11);
+ outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
}
if (drive->current_speed > XFER_UDMA_2)
pdc_old_disable_66MHz_clock(drive->hwif);
{
ide_hwif_t *hwif = HWIF(drive);
unsigned long high_16 = hwif->dma_master;
- u8 dma_stat = hwif->INB(hwif->dma_status);
- u8 sc1d = hwif->INB((high_16 + 0x001d));
+ u8 dma_stat = inb(hwif->dma_status);
+ u8 sc1d = inb(high_16 + 0x001d);
if (hwif->channel) {
/* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
static void pdc202xx_reset_host (ide_hwif_t *hwif)
{
unsigned long high_16 = hwif->dma_master;
- u8 udma_speed_flag = hwif->INB(high_16|0x001f);
+ u8 udma_speed_flag = inb(high_16 | 0x001f);
- hwif->OUTB((udma_speed_flag | 0x10), (high_16|0x001f));
+ outb(udma_speed_flag | 0x10, high_16 | 0x001f);
mdelay(100);
- hwif->OUTB((udma_speed_flag & ~0x10), (high_16|0x001f));
+ outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
mdelay(2000); /* 2 seconds ?! */
printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
return;
}
- udma_speed_flag = hwif->INB((dmabase|0x1f));
- primary_mode = hwif->INB((dmabase|0x1a));
- secondary_mode = hwif->INB((dmabase|0x1b));
+ udma_speed_flag = inb(dmabase | 0x1f);
+ primary_mode = inb(dmabase | 0x1a);
+ secondary_mode = inb(dmabase | 0x1b);
printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
"Primary %s Mode " \
"Secondary %s Mode.\n", hwif->cds->name,
printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
hwif->cds->name, udma_speed_flag,
(udma_speed_flag|1));
- hwif->OUTB(udma_speed_flag|1,(dmabase|0x1f));
- printk("%sACTIVE\n",
- (hwif->INB(dmabase|0x1f)&1) ? "":"IN");
+ outb(udma_speed_flag | 1, dmabase | 0x1f);
+ printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
}
#endif /* CONFIG_PDC202XX_BURST */
if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
(dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
if (!drive->init_speed) {
- u8 dma_stat = hwif->INB(hwif->dma_status);
+ u8 dma_stat = inb(hwif->dma_status);
dma_pio:
if (((ultra_enable << (7-drive->dn) & 0x80) == 0x80) &&
if (!noautodma)
hwif->autodma = 1;
- dma_stat = hwif->INB(hwif->dma_status);
+ dma_stat = inb(hwif->dma_status);
hwif->drives[0].autodma = (dma_stat & 0x20);
hwif->drives[1].autodma = (dma_stat & 0x40);
hwif->drives[0].autotune = (!(dma_stat & 0x20));
static void
sgiioc4_maskproc(ide_drive_t * drive, int mask)
{
- ide_hwif_t *hwif = HWIF(drive);
- hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
- IDE_CONTROL_REG);
+ writeb(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
+ (void __iomem *)IDE_CONTROL_REG);
}
static int
sgiioc4_checkirq(ide_hwif_t * hwif)
{
- u8 intr_reg =
- hwif->INL(hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4);
+ unsigned long intr_addr =
+ hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4;
- if (intr_reg & 0x03)
+ if ((u8)readl((void __iomem *)intr_addr) & 0x03)
return 1;
return 0;
}
+static u8 sgiioc4_INB(unsigned long);
static int
sgiioc4_clearirq(ide_drive_t * drive)
hwif->io_ports[IDE_IRQ_OFFSET] + (IOC4_INTR_REG << 2);
/* Code to check for PCI error conditions */
- intr_reg = hwif->INL(other_ir);
+ intr_reg = readl((void __iomem *)other_ir);
if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */
/*
- * Using hwif->INB to read the IDE_STATUS_REG has a side effect
+ * Using sgiioc4_INB to read the IDE_STATUS_REG has a side effect
* of clearing the interrupt. The first read should clear it
* if it is set. The second read should return a "clear" status
* if it got cleared. If not, then spin for a bit trying to
* clear it.
*/
- u8 stat = hwif->INB(IDE_STATUS_REG);
+ u8 stat = sgiioc4_INB(IDE_STATUS_REG);
int count = 0;
- stat = hwif->INB(IDE_STATUS_REG);
+ stat = sgiioc4_INB(IDE_STATUS_REG);
while ((stat & 0x80) && (count++ < 100)) {
udelay(1);
- stat = hwif->INB(IDE_STATUS_REG);
+ stat = sgiioc4_INB(IDE_STATUS_REG);
}
if (intr_reg & 0x02) {
pci_stat_cmd_reg;
pci_err_addr_low =
- hwif->INL(hwif->io_ports[IDE_IRQ_OFFSET]);
+ readl((void __iomem *)hwif->io_ports[IDE_IRQ_OFFSET]);
pci_err_addr_high =
- hwif->INL(hwif->io_ports[IDE_IRQ_OFFSET] + 4);
+ readl((void __iomem *)(hwif->io_ports[IDE_IRQ_OFFSET] + 4));
pci_read_config_dword(hwif->pci_dev, PCI_COMMAND,
&pci_stat_cmd_reg);
printk(KERN_ERR
}
/* Clear the Interrupt, Error bits on the IOC4 */
- hwif->OUTL(0x03, other_ir);
+ writel(0x03, (void __iomem *)other_ir);
- intr_reg = hwif->INL(other_ir);
+ intr_reg = readl((void __iomem *)other_ir);
}
return intr_reg & 3;
static void sgiioc4_ide_dma_start(ide_drive_t * drive)
{
ide_hwif_t *hwif = HWIF(drive);
- unsigned int reg = hwif->INL(hwif->dma_base + IOC4_DMA_CTRL * 4);
+ unsigned long ioc4_dma_addr = hwif->dma_base + IOC4_DMA_CTRL * 4;
+ unsigned int reg = readl((void __iomem *)ioc4_dma_addr);
unsigned int temp_reg = reg | IOC4_S_DMA_START;
- hwif->OUTL(temp_reg, hwif->dma_base + IOC4_DMA_CTRL * 4);
+ writel(temp_reg, (void __iomem *)ioc4_dma_addr);
}
static u32
sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base)
{
+ unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
u32 ioc4_dma;
int count;
count = 0;
- ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4);
+ ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) {
udelay(1);
- ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4);
+ ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
}
return ioc4_dma;
}
{
u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0;
ide_hwif_t *hwif = HWIF(drive);
- u64 dma_base = hwif->dma_base;
+ unsigned long dma_base = hwif->dma_base;
int dma_stat = 0;
unsigned long *ending_dma = ide_get_hwifdata(hwif);
- hwif->OUTL(IOC4_S_DMA_STOP, dma_base + IOC4_DMA_CTRL * 4);
+ writel(IOC4_S_DMA_STOP, (void __iomem *)(dma_base + IOC4_DMA_CTRL * 4));
ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
dma_stat = 1;
}
- bc_dev = hwif->INL(dma_base + IOC4_BC_DEV * 4);
- bc_mem = hwif->INL(dma_base + IOC4_BC_MEM * 4);
+ bc_dev = readl((void __iomem *)(dma_base + IOC4_BC_DEV * 4));
+ bc_mem = readl((void __iomem *)(dma_base + IOC4_BC_MEM * 4));
if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) {
if (bc_dev > bc_mem + 8) {
{
u32 ioc4_dma;
ide_hwif_t *hwif = HWIF(drive);
- u64 dma_base = hwif->dma_base;
+ unsigned long dma_base = hwif->dma_base;
+ unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
u32 dma_addr, ending_dma_addr;
- ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4);
+ ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
if (ioc4_dma & IOC4_S_DMA_ACTIVE) {
printk(KERN_WARNING
"%s(%s):Warning!! DMA from previous transfer was still active\n",
__FUNCTION__, drive->name);
- hwif->OUTL(IOC4_S_DMA_STOP, dma_base + IOC4_DMA_CTRL * 4);
+ writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
if (ioc4_dma & IOC4_S_DMA_STOP)
__FUNCTION__, drive->name);
}
- ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4);
+ ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
if (ioc4_dma & IOC4_S_DMA_ERROR) {
printk(KERN_WARNING
"%s(%s) : Warning!! - DMA Error during Previous"
" transfer | status 0x%x\n",
__FUNCTION__, drive->name, ioc4_dma);
- hwif->OUTL(IOC4_S_DMA_STOP, dma_base + IOC4_DMA_CTRL * 4);
+ writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
if (ioc4_dma & IOC4_S_DMA_STOP)
/* Address of the Scatter Gather List */
dma_addr = cpu_to_le32(hwif->dmatable_dma);
- hwif->OUTL(dma_addr, dma_base + IOC4_DMA_PTR_L * 4);
+ writel(dma_addr, (void __iomem *)(dma_base + IOC4_DMA_PTR_L * 4));
/* Address of the Ending DMA */
memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE);
ending_dma_addr = cpu_to_le32(hwif->dma_status);
- hwif->OUTL(ending_dma_addr, dma_base + IOC4_DMA_END_ADDR * 4);
+ writel(ending_dma_addr, (void __iomem *)(dma_base + IOC4_DMA_END_ADDR * 4));
- hwif->OUTL(dma_direction, dma_base + IOC4_DMA_CTRL * 4);
+ writel(dma_direction, (void __iomem *)ioc4_dma_addr);
drive->waiting_for_dma = 1;
}
default_hwif_mmiops(hwif);
/* Initializing chipset IRQ Registers */
- hwif->OUTL(0x03, irqport + IOC4_INTR_SET * 4);
+ writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4));
ide_init_sgiioc4(hwif);
unsigned long addr = siimage_selreg(hwif, 0x1);
if (SATA_ERROR_REG) {
- u32 ext_stat = hwif->INL(base + 0x10);
+ u32 ext_stat = readl((void __iomem *)(base + 0x10));
u8 watchdog = 0;
if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
- u32 sata_error = hwif->INL(SATA_ERROR_REG);
- hwif->OUTL(sata_error, SATA_ERROR_REG);
+ u32 sata_error = readl((void __iomem *)SATA_ERROR_REG);
+ writel(sata_error, (void __iomem *)SATA_ERROR_REG);
watchdog = (sata_error & 0x00680000) ? 1 : 0;
printk(KERN_WARNING "%s: sata_error = 0x%08x, "
"watchdog = %d, %s\n",
}
/* return 1 if INTR asserted */
- if ((hwif->INB(hwif->dma_status) & 0x04) == 0x04)
+ if ((readb((void __iomem *)hwif->dma_status) & 0x04) == 0x04)
return 1;
/* return 1 if Device INTR asserted */
- if ((hwif->INB(addr) & 8) == 8)
+ if ((readb((void __iomem *)addr) & 8) == 8)
return 0; //return 1;
return 0;
u32 stat_config = 0;
unsigned long addr = siimage_selreg(hwif, 0);
- if (hwif->mmio) {
- stat_config = hwif->INL(addr);
- } else
+ if (hwif->mmio)
+ stat_config = readl((void __iomem *)addr);
+ else
pci_read_config_dword(hwif->pci_dev, addr, &stat_config);
switch (state) {
if (SATA_STATUS_REG) {
ide_hwif_t *hwif = HWIF(drive);
- if ((hwif->INL(SATA_STATUS_REG) & 0x03) != 0x03) {
+ /* SATA_STATUS_REG is valid only when in MMIO mode */
+ if ((readl((void __iomem *)SATA_STATUS_REG) & 0x03) != 0x03) {
printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
- hwif->name, hwif->INL(SATA_STATUS_REG));
+ hwif->name, readl((void __iomem *)SATA_STATUS_REG));
HWGROUP(drive)->polling = 0;
return ide_started;
}
}
if (SATA_STATUS_REG) {
- u32 sata_stat = hwif->INL(SATA_STATUS_REG);
+ /* SATA_STATUS_REG is valid only when in MMIO mode */
+ u32 sata_stat = readl((void __iomem *)SATA_STATUS_REG);
printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n",
hwif->name, sata_stat, __FUNCTION__);
if (!(sata_stat)) {
* Was DMA enabled? If so, disable it - we're resetting the
* host. The IDE layer will be handling the drive for us.
*/
- val = hwif->INB(dma_base);
+ val = inb(dma_base);
if (val & 1) {
outb(val & ~1, dma_base);
printk("sl82c105: DMA was enabled\n");
scr &= (speed < XFER_MW_DMA_0) ? 0xf8ff : 0xff0f;
scr |= mode;
- hwif->OUTW(scr, scr_port);
+ outw(scr, scr_port);
return ide_config_drive_speed(drive, speed);
}
"attempting recovery...\n", drive->name);
/* Stop DMA */
- hwif->OUTB(dma_cmd & ~0x01, hwif->dma_command);
+ outb(dma_cmd & ~0x01, hwif->dma_command);
/* Setup the dummy DMA transfer */
- hwif->OUTW(0, sc_base + 0x0a); /* Sector Count */
- hwif->OUTW(0, twcr_port); /* Transfer Word Count 1 or 2 */
+ outw(0, sc_base + 0x0a); /* Sector Count */
+ outw(0, twcr_port); /* Transfer Word Count 1 or 2 */
/* Start the dummy DMA transfer */
- hwif->OUTB(0x00, hwif->dma_command); /* clear R_OR_WCTR for write */
- hwif->OUTB(0x01, hwif->dma_command); /* set START_STOPBM */
+ outb(0x00, hwif->dma_command); /* clear R_OR_WCTR for write */
+ outb(0x01, hwif->dma_command); /* set START_STOPBM */
/*
* If an interrupt was pending, it should come thru shortly.
* the appropriate system control registers for DMA to work
* with LBA48 and ATAPI devices...
*/
- hwif->OUTW(nsectors, sc_base + 0x0a); /* Sector Count */
- hwif->OUTW(SECTOR_SIZE / 2, twcr_port); /* Transfer Word Count 1/2 */
+ outw(nsectors, sc_base + 0x0a); /* Sector Count */
+ outw(SECTOR_SIZE / 2, twcr_port); /* Transfer Word Count 1/2 */
/* Install our timeout expiry hook, saving the current handler... */
ide_set_hwifdata(hwif, hwgroup->expiry);
}
/* System Control 1 Register bit 11 (ATA Hard Reset) write */
- hwif->OUTW(scr1, sc_base + 0x00);
+ outw(scr1, sc_base + 0x00);
return 0;
}
u16 scr1 = hwif->INW(sc_base + 0x00);;
/* System Control 1 Register bit 15 (Soft Reset) set */
- hwif->OUTW(scr1 | 0x8000, sc_base + 0x00);
+ outw(scr1 | 0x8000, sc_base + 0x00);
/* System Control 1 Register bit 14 (FIFO Reset) set */
- hwif->OUTW(scr1 | 0x4000, sc_base + 0x00);
+ outw(scr1 | 0x4000, sc_base + 0x00);
/* System Control 1 Register: reset clear */
- hwif->OUTW(scr1 & ~0xc000, sc_base + 0x00);
+ outw(scr1 & ~0xc000, sc_base + 0x00);
/* Store the system control register base for convenience... */
hwif->config_data = sc_base;
* Sector Count Control Register bits 0 and 1 set:
* software sets Sector Count Register for master and slave device
*/
- hwif->OUTW(0x0003, sc_base + 0x0c);
+ outw(0x0003, sc_base + 0x0c);
/* Sector Count Register limit */
hwif->rqsize = 0xffff;
if (reg != hwif->select_data) {
hwif->select_data = reg;
/* set PIO/DMA */
- hwif->OUTB(0x51|(hwif->channel<<3), hwif->config_data+1);
- hwif->OUTW(reg & 0xff, hwif->config_data);
+ outb(0x51 | (hwif->channel << 3), hwif->config_data + 1);
+ outw(reg & 0xff, hwif->config_data);
}
/* enable IRQ if not probing */
if (drive->present) {
- reg = hwif->INW(hwif->config_data + 3);
+ reg = inw(hwif->config_data + 3);
reg &= 0x13;
reg &= ~(1 << hwif->channel);
- hwif->OUTW(reg, hwif->config_data+3);
+ outw(reg, hwif->config_data + 3);
}
local_irq_restore(flags);
static void trm290_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
{
- ide_hwif_t *hwif = HWIF(drive);
-
BUG_ON(HWGROUP(drive)->handler != NULL); /* paranoia check */
ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL);
/* issue cmd to drive */
- hwif->OUTB(command, IDE_COMMAND_REG);
+ outb(command, IDE_COMMAND_REG);
}
static int trm290_ide_dma_setup(ide_drive_t *drive)
}
/* select DMA xfer */
trm290_prepare_drive(drive, 1);
- hwif->OUTL(hwif->dmatable_dma|rw, hwif->dma_command);
+ outl(hwif->dmatable_dma | rw, hwif->dma_command);
drive->waiting_for_dma = 1;
/* start DMA */
- hwif->OUTW((count * 2) - 1, hwif->dma_status);
+ outw((count * 2) - 1, hwif->dma_status);
return 0;
}
drive->waiting_for_dma = 0;
/* purge DMA mappings */
ide_destroy_dmatable(drive);
- status = hwif->INW(hwif->dma_status);
+ status = inw(hwif->dma_status);
return (status != 0x00ff);
}
ide_hwif_t *hwif = HWIF(drive);
u16 status = 0;
- status = hwif->INW(hwif->dma_status);
+ status = inw(hwif->dma_status);
return (status == 0x00ff);
}
local_irq_save(flags);
/* put config reg into first byte of hwif->select_data */
- hwif->OUTB(0x51|(hwif->channel<<3), hwif->config_data+1);
+ outb(0x51 | (hwif->channel << 3), hwif->config_data + 1);
/* select PIO as default */
hwif->select_data = 0x21;
- hwif->OUTB(hwif->select_data, hwif->config_data);
+ outb(hwif->select_data, hwif->config_data);
/* get IRQ info */
- reg = hwif->INB(hwif->config_data+3);
+ reg = inb(hwif->config_data + 3);
/* mask IRQs for both ports */
reg = (reg & 0x10) | 0x03;
- hwif->OUTB(reg, hwif->config_data+3);
+ outb(reg, hwif->config_data + 3);
local_irq_restore(flags);
if ((reg & 0x10))
static u16 next_offset = 0;
u8 old_mask;
- hwif->OUTB(0x54|(hwif->channel<<3), hwif->config_data+1);
- old = hwif->INW(hwif->config_data);
+ outb(0x54 | (hwif->channel << 3), hwif->config_data + 1);
+ old = inw(hwif->config_data);
old &= ~1;
- old_mask = hwif->INB(old+2);
+ old_mask = inb(old + 2);
if (old != compat && old_mask == 0xff) {
/* leave lower 10 bits untouched */
compat += (next_offset += 0x400);
hwif->io_ports[IDE_CONTROL_OFFSET] = compat + 2;
- hwif->OUTW(compat|1, hwif->config_data);
- new = hwif->INW(hwif->config_data);
+ outw(compat | 1, hwif->config_data);
+ new = inw(hwif->config_data);
printk(KERN_INFO "%s: control basereg workaround: "
"old=0x%04x, new=0x%04x\n",
hwif->name, old, new & ~1);
return (u16)data;
}
-static u32 scc_ide_inl(unsigned long port)
-{
- u32 data = in_be32((void*)port);
- return data;
-}
-
static void scc_ide_insw(unsigned long port, void *addr, u32 count)
{
u16 *ptr = (u16 *)addr;
out_be32((void*)port, addr);
}
-static void scc_ide_outl(u32 addr, unsigned long port)
-{
- out_be32((void*)port, addr);
-}
-
static void
scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port)
{
break;
}
- reg = hwif->INL(cckctrl_port);
+ reg = in_be32((void __iomem *)cckctrl_port);
if (reg & CCKCTRL_ATACLKOEN) {
offset = 1; /* 133MHz */
} else {
offset = 0; /* 100MHz */
}
reg = JCHSTtbl[offset][mode_wanted] << 16 | JCHHTtbl[offset][mode_wanted];
- hwif->OUTL(reg, piosht_port);
+ out_be32((void __iomem *)piosht_port, reg);
reg = JCHCTtbl[offset][mode_wanted];
- hwif->OUTL(reg, pioct_port);
+ out_be32((void __iomem *)pioct_port, reg);
ide_config_drive_speed(drive, speed);
}
unsigned long reg;
unsigned long jcactsel;
- reg = hwif->INL(cckctrl_port);
+ reg = in_be32((void __iomem *)cckctrl_port);
if (reg & CCKCTRL_ATACLKOEN) {
offset = 1; /* 133MHz */
} else {
jcactsel = JCACTSELtbl[offset][idx];
if (is_slave) {
- hwif->OUTL(JCHDCTxtbl[offset][idx], sdmact_port);
- hwif->OUTL(JCSTWTxtbl[offset][idx], scrcst_port);
- jcactsel = jcactsel << 2 ;
- hwif->OUTL( (hwif->INL( tdvhsel_port ) & ~TDVHSEL_SLAVE) | jcactsel, tdvhsel_port );
+ out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);
+ out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);
+ jcactsel = jcactsel << 2;
+ out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel);
} else {
- hwif->OUTL(JCHDCTxtbl[offset][idx], mdmact_port);
- hwif->OUTL(JCSTWTxtbl[offset][idx], mcrcst_port);
- hwif->OUTL( (hwif->INL( tdvhsel_port ) & ~TDVHSEL_MASTER) | jcactsel, tdvhsel_port );
+ out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);
+ out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);
+ out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel);
}
reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
- hwif->OUTL(reg, udenvt_port);
+ out_be32((void __iomem *)udenvt_port, reg);
return ide_config_drive_speed(drive, speed);
}
return 1; /* DMA is not supported */
}
+/**
+ * scc_ide_dma_setup - begin a DMA phase
+ * @drive: target device
+ *
+ * Build an IDE DMA PRD (IDE speak for scatter gather table)
+ * and then set up the DMA transfer registers.
+ *
+ * Returns 0 on success. If a PIO fallback is required then 1
+ * is returned.
+ */
+
+static int scc_dma_setup(ide_drive_t *drive)
+{
+ ide_hwif_t *hwif = drive->hwif;
+ struct request *rq = HWGROUP(drive)->rq;
+ unsigned int reading;
+ u8 dma_stat;
+
+ if (rq_data_dir(rq))
+ reading = 0;
+ else
+ reading = 1 << 3;
+
+ /* fall back to pio! */
+ if (!ide_build_dmatable(drive, rq)) {
+ ide_map_sg(drive, rq);
+ return 1;
+ }
+
+ /* PRD table */
+ out_be32((void __iomem *)hwif->dma_prdtable, hwif->dmatable_dma);
+
+ /* specify r/w */
+ out_be32((void __iomem *)hwif->dma_command, reading);
+
+ /* read dma_status for INTR & ERROR flags */
+ dma_stat = in_be32((void __iomem *)hwif->dma_status);
+
+ /* clear INTR & ERROR flags */
+ out_be32((void __iomem *)hwif->dma_status, dma_stat|6);
+ drive->waiting_for_dma = 1;
+ return 0;
+}
+
+
/**
* scc_ide_dma_end - Stop DMA
* @drive: IDE drive
u32 reg;
while (1) {
- reg = hwif->INL(intsts_port);
+ reg = in_be32((void __iomem *)intsts_port);
if (reg & INTSTS_SERROR) {
printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
- hwif->OUTL(INTSTS_SERROR|INTSTS_BMSINT, intsts_port);
+ out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);
- hwif->OUTB(hwif->INB(hwif->dma_command) & ~QCHCD_IOS_SS,
- hwif->dma_command);
+ out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
continue;
}
u32 maea0, maec0;
unsigned long ctl_base = hwif->config_data;
- maea0 = hwif->INL(ctl_base + 0xF50);
- maec0 = hwif->INL(ctl_base + 0xF54);
+ maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));
+ maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));
printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
- hwif->OUTL(INTSTS_PRERR|INTSTS_BMSINT, intsts_port);
+ out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);
- hwif->OUTB(hwif->INB(hwif->dma_command) & ~QCHCD_IOS_SS,
- hwif->dma_command);
+ out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
continue;
}
if (reg & INTSTS_RERR) {
printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
- hwif->OUTL(INTSTS_RERR|INTSTS_BMSINT, intsts_port);
+ out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);
- hwif->OUTB(hwif->INB(hwif->dma_command) & ~QCHCD_IOS_SS,
- hwif->dma_command);
+ out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
continue;
}
if (reg & INTSTS_ICERR) {
- hwif->OUTB(hwif->INB(hwif->dma_command) & ~QCHCD_IOS_SS,
- hwif->dma_command);
+ out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
- hwif->OUTL(INTSTS_ICERR|INTSTS_BMSINT, intsts_port);
+ out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);
continue;
}
if (reg & INTSTS_BMSINT) {
printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
- hwif->OUTL(INTSTS_BMSINT, intsts_port);
+ out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);
ide_do_reset(drive);
continue;
}
if (reg & INTSTS_BMHE) {
- hwif->OUTL(INTSTS_BMHE, intsts_port);
+ out_be32((void __iomem *)intsts_port, INTSTS_BMHE);
continue;
}
if (reg & INTSTS_ACTEINT) {
- hwif->OUTL(INTSTS_ACTEINT, intsts_port);
+ out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);
continue;
}
if (reg & INTSTS_IOIRQS) {
- hwif->OUTL(INTSTS_IOIRQS, intsts_port);
+ out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);
continue;
}
break;
hwif->INB = scc_ide_inb;
hwif->INW = scc_ide_inw;
- hwif->INL = scc_ide_inl;
hwif->INSW = scc_ide_insw;
hwif->INSL = scc_ide_insl;
hwif->OUTB = scc_ide_outb;
hwif->OUTBSYNC = scc_ide_outbsync;
hwif->OUTW = scc_ide_outw;
- hwif->OUTL = scc_ide_outl;
hwif->OUTSW = scc_ide_outsw;
hwif->OUTSL = scc_ide_outsl;
hwif->dma_status = hwif->dma_base + 0x04;
hwif->dma_prdtable = hwif->dma_base + 0x08;
- hwif->OUTL(hwif->dmatable_dma, (hwif->dma_base + 0x018)); /* PTERADD */
+ /* PTERADD */
+ out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
+ hwif->dma_setup = scc_dma_setup;
hwif->ide_dma_end = scc_ide_dma_end;
hwif->speedproc = scc_tune_chipset;
hwif->tuneproc = scc_tuneproc;
hwif->drives[0].autotune = IDE_TUNE_AUTO;
hwif->drives[1].autotune = IDE_TUNE_AUTO;
- if (hwif->INL(hwif->config_data + 0xff0) & CCKCTRL_ATACLKOEN) {
+ if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN) {
hwif->ultra_mask = 0x7f; /* 133MHz */
} else {
hwif->ultra_mask = 0x3f; /* 100MHz */
void (*OUTB)(u8 addr, unsigned long port);
void (*OUTBSYNC)(ide_drive_t *drive, u8 addr, unsigned long port);
void (*OUTW)(u16 addr, unsigned long port);
- void (*OUTL)(u32 addr, unsigned long port);
void (*OUTSW)(unsigned long port, void *addr, u32 count);
void (*OUTSL)(unsigned long port, void *addr, u32 count);
u8 (*INB)(unsigned long port);
u16 (*INW)(unsigned long port);
- u32 (*INL)(unsigned long port);
void (*INSW)(unsigned long port, void *addr, u32 count);
void (*INSL)(unsigned long port, void *addr, u32 count);
projects / GitHub / LineageOS / android_kernel_samsung_universal7580.git / commitdiff