clk: clock: Fix PCIE100M clock output some corner chip swing small issue

PD#170610: clock: Fix PCIE100M clock output

Change-Id: I8ada918f6910b537374115260ebaea7a4489e9d6
Signed-off-by: Shunzhou Jiang <shunzhou.jiang@amlogic.com>

diff --git a/drivers/amlogic/clk/g12a/g12a_clk-pll.c b/drivers/amlogic/clk/g12a/g12a_clk-pll.c
index 660428b4838ce11b0a989d76fe419b29c6648b59..90d3942d6d0a771ef5ae8933eaabfb1be42ae2f6 100644 (file)
--- a/drivers/amlogic/clk/g12a/g12a_clk-pll.c
+++ b/drivers/amlogic/clk/g12a/g12a_clk-pll.c
@@ -61,8 +61,8 @@
 #define G12A_PCIE_PLL_CNTL3  0x10058e00
 #define G12A_PCIE_PLL_CNTL4  0x000100c0
 #define G12A_PCIE_PLL_CNTL4_ 0x008100c0
-#define G12A_PCIE_PLL_CNTL5  0x28000048
-#define G12A_PCIE_PLL_CNTL5_ 0x28000068
+#define G12A_PCIE_PLL_CNTL5  0x68000048
+#define G12A_PCIE_PLL_CNTL5_ 0x68000068
 
 #define G12A_SYS_PLL_CNTL1 0x00000000
 #define G12A_SYS_PLL_CNTL2 0x00000000