powerpc/pseries: Advertise HPT resizing support via CAS
authorDavid Gibson <david@gibson.dropbear.id.au>
Fri, 9 Dec 2016 00:07:37 +0000 (11:07 +1100)
committerMichael Ellerman <mpe@ellerman.id.au>
Fri, 10 Feb 2017 02:28:01 +0000 (13:28 +1100)
The hypervisor needs to know a guest is capable of using the HPT resizing
PAPR extension in order to make full advantage of it for memory hotplug.

If the hypervisor knows the guest is HPT resize aware, it can size the
initial HPT based on the initial guest RAM size, relying on the guest to
resize the HPT when more memory is hot-added. Without this, the hypervisor
must size the HPT for the maximum possible guest RAM, which can lead to
a huge waste of space if the guest never actually expends to that maximum
size.

This patch advertises the guest's support for HPT resizing via the
ibm,client-architecture-support OF interface. We use bit 5 of byte 6 of
option vector 5 for this purpose, as defined in the PAPR ACR "HPT
resizing option".

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
Reviewed-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
arch/powerpc/include/asm/prom.h
arch/powerpc/kernel/prom_init.c

index 5e57705b47599973d19629a014035a7c1fb5a11d..00fcfcbdd053fbeece5d9c7f6f33b7e723d9c7f6 100644 (file)
@@ -151,6 +151,7 @@ struct of_drconf_cell {
 #define OV5_XCMO               0x0440  /* Page Coalescing */
 #define OV5_TYPE1_AFFINITY     0x0580  /* Type 1 NUMA affinity */
 #define OV5_PRRN               0x0540  /* Platform Resource Reassignment */
+#define OV5_RESIZE_HPT         0x0601  /* Hash Page Table resizing */
 #define OV5_PFO_HW_RNG         0x0E80  /* PFO Random Number Generator */
 #define OV5_PFO_HW_842         0x0E40  /* PFO Compression Accelerator */
 #define OV5_PFO_HW_ENCR                0x0E20  /* PFO Encryption Accelerator */
index ec47a939cbdd6dd81c6c05ed6707f28e12d9f0ea..d16b0f005290f4da2ada0b5cd433fc957a228d1d 100644 (file)
@@ -826,7 +826,7 @@ struct ibm_arch_vec __cacheline_aligned ibm_architecture_vec = {
                0,
 #endif
                .associativity = OV5_FEAT(OV5_TYPE1_AFFINITY) | OV5_FEAT(OV5_PRRN),
-               .bin_opts = 0,
+               .bin_opts = OV5_FEAT(OV5_RESIZE_HPT),
                .micro_checkpoint = 0,
                .reserved0 = 0,
                .max_cpus = cpu_to_be32(NR_CPUS),       /* number of cores supported */