ARM: sun6i: dt: Add SPI controllers to the A31 DTSI

The A31 has 4 SPI controllers. Add them in the DTSI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 93d7bb6b1697280660fb9d1a959e9117a8427bbe..fc07f7089b854d4b45b909ffeaafe25b5013b064 100644 (file)
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -350,6 +350,46 @@
                        status = "disabled";
                };
 
+               spi0: spi@01c68000 {
+                       compatible = "allwinner,sun6i-a31-spi";
+                       reg = <0x01c68000 0x1000>;
+                       interrupts = <0 65 4>;
+                       clocks = <&ahb1_gates 20>, <&spi0_clk>;
+                       clock-names = "ahb", "mod";
+                       resets = <&ahb1_rst 20>;
+                       status = "disabled";
+               };
+
+               spi1: spi@01c69000 {
+                       compatible = "allwinner,sun6i-a31-spi";
+                       reg = <0x01c69000 0x1000>;
+                       interrupts = <0 66 4>;
+                       clocks = <&ahb1_gates 21>, <&spi1_clk>;
+                       clock-names = "ahb", "mod";
+                       resets = <&ahb1_rst 21>;
+                       status = "disabled";
+               };
+
+               spi2: spi@01c6a000 {
+                       compatible = "allwinner,sun6i-a31-spi";
+                       reg = <0x01c6a000 0x1000>;
+                       interrupts = <0 67 4>;
+                       clocks = <&ahb1_gates 22>, <&spi2_clk>;
+                       clock-names = "ahb", "mod";
+                       resets = <&ahb1_rst 22>;
+                       status = "disabled";
+               };
+
+               spi3: spi@01c6b000 {
+                       compatible = "allwinner,sun6i-a31-spi";
+                       reg = <0x01c6b000 0x1000>;
+                       interrupts = <0 68 4>;
+                       clocks = <&ahb1_gates 23>, <&spi3_clk>;
+                       clock-names = "ahb", "mod";
+                       resets = <&ahb1_rst 23>;
+                       status = "disabled";
+               };
+
                gic: interrupt-controller@01c81000 {
                        compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
                        reg = <0x01c81000 0x1000>,