drm/radeon: use cached memory when evicting for vram on non agp

Force the use of cached memory when evicting from vram on non agp
hardware. Also force write combine on agp hw. This is to insure
the minimum cache type change when allocating memory and improving
memory eviction especialy on pci/pcie hw.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>

diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index b91118ccef867f5b59effd78d0ee93d65a932f8b..3f9f3bbc46811f98184a2a26e2e9e3ec84f59bab 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -88,10 +88,20 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
        if (domain & RADEON_GEM_DOMAIN_VRAM)
                rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
                                        TTM_PL_FLAG_VRAM;
-       if (domain & RADEON_GEM_DOMAIN_GTT)
-               rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
-       if (domain & RADEON_GEM_DOMAIN_CPU)
-               rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
+       if (domain & RADEON_GEM_DOMAIN_GTT) {
+               if (rbo->rdev->flags & RADEON_IS_AGP) {
+                       rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
+               } else {
+                       rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
+               }
+       }
+       if (domain & RADEON_GEM_DOMAIN_CPU) {
+               if (rbo->rdev->flags & RADEON_IS_AGP) {
+                       rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
+               } else {
+                       rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
+               }
+       }
        if (!c)
                rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
        rbo->placement.num_placement = c;