net: bcmgenet: update bcmgenet_ephy_power_up to clear CK25_DIS bit
authorFlorian Fainelli <f.fainelli@gmail.com>
Mon, 23 Mar 2015 22:09:52 +0000 (15:09 -0700)
committerDavid S. Miller <davem@davemloft.net>
Tue, 24 Mar 2015 02:10:42 +0000 (22:10 -0400)
The CK25_DIS bit controls whether a 25Mhz clock is fed to the GPHY or
not, in preparation for powering down the integrated GPHY when relevant,
make sure we clear that bit.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/broadcom/genet/bcmgenet.h
drivers/net/ethernet/broadcom/genet/bcmmii.c

index 1ea8389463185770037c3db50b2ef1dfc697f18b..a27ef777cc81c3e0587b32b5da8a46d6b9c8e0b3 100644 (file)
@@ -354,6 +354,7 @@ struct bcmgenet_mib_counters {
 #define EXT_GPHY_CTRL                  0x1C
 #define  EXT_CFG_IDDQ_BIAS             (1 << 0)
 #define  EXT_CFG_PWR_DOWN              (1 << 1)
+#define  EXT_CK25_DIS                  (1 << 4)
 #define  EXT_GPHY_RESET                        (1 << 5)
 
 /* DMA rings size */
index 446889cc3c6a207ebe4ef8a55ccee6a556e2fae4..f7d9d275314189b80cc7c8efce2b76e639273e4e 100644 (file)
@@ -178,7 +178,7 @@ static void bcmgenet_ephy_power_up(struct net_device *dev)
                return;
 
        reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
-       reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
+       reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | EXT_CK25_DIS);
        reg |= EXT_GPHY_RESET;
        bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
        mdelay(2);