ASoC: fsl_spdif: spba clk is needed by spdif device

SPDIF need to enable the spba clock, when sdma is using share peripheral
script. In this case, there is two spba master port is used, if don't
enable the clock, the spba bus will have arbitration issue, which may
cause read/write wrong data from/to SPDIF registers.

Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
index b5ee32ee370602bb9c56edf99f6d7df873aca538..4ca39ddc04172bcc4a56e41a193b7ea405ad82a7 100644 (file)
--- a/Documentation/devicetree/bindings/sound/fsl,spdif.txt
+++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
@@ -27,6 +27,11 @@ Required properties:
                          Transceiver Clock Diagram" of SoC reference manual.
                          It can also be referred to TxClk_Source bit of
                          register SPDIF_STC.
+       "spba"            The spba clock is required when SPDIF is placed as a
+                         bus slave of the Shared Peripheral Bus and when two
+                         or more bus masters (CPU, DMA or DSP) try to access
+                         it. This property is optional depending on the SoC
+                         design.
 
    - big-endian                : If this property is absent, the native endian mode
                          will be in use as default, or the big endian mode

diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
index 3d59bb6719f2b6fea0d7ed7137940bac88d99d6b..fa36e6753799bc13f8a354a3e82a68d0cc5ebf8c 100644 (file)
--- a/sound/soc/fsl/fsl_spdif.c
+++ b/sound/soc/fsl/fsl_spdif.c
@@ -88,6 +88,7 @@ struct spdif_mixer_control {
  * @rxclk: rx clock sources for capture
  * @coreclk: core clock for register access via DMA
  * @sysclk: system clock for rx clock rate measurement
+ * @spbaclk: SPBA clock (optional, depending on SoC design)
  * @dma_params_tx: DMA parameters for transmit channel
  * @dma_params_rx: DMA parameters for receive channel
  */
@@ -106,6 +107,7 @@ struct fsl_spdif_priv {
        struct clk *rxclk;
        struct clk *coreclk;
        struct clk *sysclk;
+       struct clk *spbaclk;
        struct snd_dmaengine_dai_dma_data dma_params_tx;
        struct snd_dmaengine_dai_dma_data dma_params_rx;
        /* regcache for SRPC */
@@ -474,6 +476,14 @@ static int fsl_spdif_startup(struct snd_pcm_substream *substream,
                        return ret;
                }
 
+               if (!IS_ERR(spdif_priv->spbaclk)) {
+                       ret = clk_prepare_enable(spdif_priv->spbaclk);
+                       if (ret) {
+                               dev_err(&pdev->dev, "failed to enable spba clock\n");
+                               goto err_spbaclk;
+                       }
+               }
+
                ret = spdif_softreset(spdif_priv);
                if (ret) {
                        dev_err(&pdev->dev, "failed to soft reset\n");
@@ -515,6 +525,9 @@ disable_txclk:
        for (i--; i >= 0; i--)
                clk_disable_unprepare(spdif_priv->txclk[i]);
 err:
+       if (!IS_ERR(spdif_priv->spbaclk))
+               clk_disable_unprepare(spdif_priv->spbaclk);
+err_spbaclk:
        clk_disable_unprepare(spdif_priv->coreclk);
 
        return ret;
@@ -548,6 +561,8 @@ static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
                spdif_intr_status_clear(spdif_priv);
                regmap_update_bits(regmap, REG_SPDIF_SCR,
                                SCR_LOW_POWER, SCR_LOW_POWER);
+               if (!IS_ERR(spdif_priv->spbaclk))
+                       clk_disable_unprepare(spdif_priv->spbaclk);
                clk_disable_unprepare(spdif_priv->coreclk);
        }
 }
@@ -1261,6 +1276,10 @@ static int fsl_spdif_probe(struct platform_device *pdev)
                return PTR_ERR(spdif_priv->coreclk);
        }
 
+       spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
+       if (IS_ERR(spdif_priv->spbaclk))
+               dev_warn(&pdev->dev, "no spba clock in devicetree\n");
+
        /* Select clock source for rx/tx clock */
        spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1");
        if (IS_ERR(spdif_priv->rxclk)) {