[ARM] cputype: separate definitions, use them

Add asm/cputype.h, moving functions and definitions from asm/system.h
there.  Convert all users of 'processor_id' to the more efficient
read_cpuid_id() function.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
new file mode 100644 (file)
index 0000000..7b9d27e
--- /dev/null
+++ b/arch/arm/include/asm/cputype.h
@@ -0,0 +1,64 @@
+#ifndef __ASM_ARM_CPUTYPE_H
+#define __ASM_ARM_CPUTYPE_H
+
+#include <linux/stringify.h>
+
+#define CPUID_ID       0
+#define CPUID_CACHETYPE        1
+#define CPUID_TCM      2
+#define CPUID_TLBTYPE  3
+
+#ifdef CONFIG_CPU_CP15
+#define read_cpuid(reg)                                                        \
+       ({                                                              \
+               unsigned int __val;                                     \
+               asm("mrc        p15, 0, %0, c0, c0, " __stringify(reg)  \
+                   : "=r" (__val)                                      \
+                   :                                                   \
+                   : "cc");                                            \
+               __val;                                                  \
+       })
+#else
+extern unsigned int processor_id;
+#define read_cpuid(reg) (processor_id)
+#endif
+
+/*
+ * The CPU ID never changes at run time, so we might as well tell the
+ * compiler that it's constant.  Use this function to read the CPU ID
+ * rather than directly reading processor_id or read_cpuid() directly.
+ */
+static inline unsigned int __attribute_const__ read_cpuid_id(void)
+{
+       return read_cpuid(CPUID_ID);
+}
+
+static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
+{
+       return read_cpuid(CPUID_CACHETYPE);
+}
+
+/*
+ * Intel's XScale3 core supports some v6 features (supersections, L2)
+ * but advertises itself as v5 as it does not support the v6 ISA.  For
+ * this reason, we need a way to explicitly test for this type of CPU.
+ */
+#ifndef CONFIG_CPU_XSC3
+#define cpu_is_xsc3()  0
+#else
+static inline int cpu_is_xsc3(void)
+{
+       if ((read_cpuid_id() & 0xffffe000) == 0x69056000)
+               return 1;
+
+       return 0;
+}
+#endif
+
+#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
+#define        cpu_is_xscale() 0
+#else
+#define        cpu_is_xscale() 1
+#endif
+
+#endif

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 514af792a5980bd384dc158124df7e9036bdc926..7aad78420f18df6b9e375d2023a8ccb998d528e0 100644 (file)
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -43,11 +43,6 @@
 #define CR_XP  (1 << 23)       /* Extended page tables                 */
 #define CR_VE  (1 << 24)       /* Vectored interrupts                  */
 
-#define CPUID_ID       0
-#define CPUID_CACHETYPE        1
-#define CPUID_TCM      2
-#define CPUID_TLBTYPE  3
-
 /*
  * This is used to ensure the compiler did actually allocate the register we
  * asked it for some inline assembly sequences.  Apparently we can't trust
@@ -61,36 +56,8 @@
 #ifndef __ASSEMBLY__
 
 #include <linux/linkage.h>
-#include <linux/stringify.h>
 #include <linux/irqflags.h>
 
-#ifdef CONFIG_CPU_CP15
-#define read_cpuid(reg)                                                        \
-       ({                                                              \
-               unsigned int __val;                                     \
-               asm("mrc        p15, 0, %0, c0, c0, " __stringify(reg)  \
-                   : "=r" (__val)                                      \
-                   :                                                   \
-                   : "cc");                                            \
-               __val;                                                  \
-       })
-#else
-extern unsigned int processor_id;
-#define read_cpuid(reg) (processor_id)
-#endif
-
-/*
- * The CPU ID never changes at run time, so we might as well tell the
- * compiler that it's constant.  Use this function to read the CPU ID
- * rather than directly reading processor_id or read_cpuid() directly.
- */
-static inline unsigned int read_cpuid_id(void) __attribute_const__;
-
-static inline unsigned int read_cpuid_id(void)
-{
-       return read_cpuid(CPUID_ID);
-}
-
 #define __exception    __attribute__((section(".exception.text")))
 
 struct thread_info;
@@ -131,31 +98,6 @@ extern void cpu_init(void);
 void arm_machine_restart(char mode);
 extern void (*arm_pm_restart)(char str);
 
-/*
- * Intel's XScale3 core supports some v6 features (supersections, L2)
- * but advertises itself as v5 as it does not support the v6 ISA.  For
- * this reason, we need a way to explicitly test for this type of CPU.
- */
-#ifndef CONFIG_CPU_XSC3
-#define cpu_is_xsc3()  0
-#else
-static inline int cpu_is_xsc3(void)
-{
-       extern unsigned int processor_id;
-
-       if ((processor_id & 0xffffe000) == 0x69056000)
-               return 1;
-
-       return 0;
-}
-#endif
-
-#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
-#define        cpu_is_xscale() 0
-#else
-#define        cpu_is_xscale() 1
-#endif
-
 #define UDBG_UNDEFINED (1 << 0)
 #define UDBG_SYSCALL   (1 << 1)
 #define UDBG_BADABORT  (1 << 2)

diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 2ca7038b67a7bf105df3529491e0f9858220ca76..fb04703f2a8c1303b4b57dd71e20f7791d06cae7 100644 (file)
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -26,6 +26,7 @@
 #include <linux/fs.h>
 
 #include <asm/cpu.h>
+#include <asm/cputype.h>
 #include <asm/elf.h>
 #include <asm/procinfo.h>
 #include <asm/setup.h>
@@ -280,9 +281,9 @@ static inline void dump_cache(const char *prefix, int cpu, unsigned int cache)
 
 static void __init dump_cpu_info(int cpu)
 {
-       unsigned int info = read_cpuid(CPUID_CACHETYPE);
+       unsigned int info = read_cpuid_cachetype();
 
-       if (info != processor_id) {
+       if (info != read_cpuid_id()) {
                printk("CPU%u: D %s %s cache\n", cpu, cache_is_vivt() ? "VIVT" : "VIPT",
                       cache_types[CACHE_TYPE(info)]);
                if (CACHE_S(info)) {
@@ -301,15 +302,15 @@ int cpu_architecture(void)
 {
        int cpu_arch;
 
-       if ((processor_id & 0x0008f000) == 0) {
+       if ((read_cpuid_id() & 0x0008f000) == 0) {
                cpu_arch = CPU_ARCH_UNKNOWN;
-       } else if ((processor_id & 0x0008f000) == 0x00007000) {
-               cpu_arch = (processor_id & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
-       } else if ((processor_id & 0x00080000) == 0x00000000) {
-               cpu_arch = (processor_id >> 16) & 7;
+       } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
+               cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
+       } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
+               cpu_arch = (read_cpuid_id() >> 16) & 7;
                if (cpu_arch)
                        cpu_arch += CPU_ARCH_ARMv3;
-       } else if ((processor_id & 0x000f0000) == 0x000f0000) {
+       } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
                unsigned int mmfr0;
 
                /* Revised CPUID format. Read the Memory Model Feature
@@ -346,10 +347,10 @@ static void __init setup_processor(void)
         * types.  The linker builds this table for us from the
         * entries in arch/arm/mm/proc-*.S
         */
-       list = lookup_processor_type(processor_id);
+       list = lookup_processor_type(read_cpuid_id());
        if (!list) {
                printk("CPU configuration botched (ID %08x), unable "
-                      "to continue.\n", processor_id);
+                      "to continue.\n", read_cpuid_id());
                while (1);
        }
 
@@ -369,7 +370,7 @@ static void __init setup_processor(void)
 #endif
 
        printk("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
-              cpu_name, processor_id, (int)processor_id & 15,
+              cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
               proc_arch[cpu_architecture()], cr_alignment);
 
        sprintf(init_utsname()->machine, "%s%c", list->arch_name, ENDIANNESS);
@@ -922,7 +923,7 @@ static int c_show(struct seq_file *m, void *v)
        int i;
 
        seq_printf(m, "Processor\t: %s rev %d (%s)\n",
-                  cpu_name, (int)processor_id & 15, elf_platform);
+                  cpu_name, read_cpuid_id() & 15, elf_platform);
 
 #if defined(CONFIG_SMP)
        for_each_online_cpu(i) {
@@ -949,30 +950,30 @@ static int c_show(struct seq_file *m, void *v)
                if (elf_hwcap & (1 << i))
                        seq_printf(m, "%s ", hwcap_str[i]);
 
-       seq_printf(m, "\nCPU implementer\t: 0x%02x\n", processor_id >> 24);
+       seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
        seq_printf(m, "CPU architecture: %s\n", proc_arch[cpu_architecture()]);
 
-       if ((processor_id & 0x0008f000) == 0x00000000) {
+       if ((read_cpuid_id() & 0x0008f000) == 0x00000000) {
                /* pre-ARM7 */
-               seq_printf(m, "CPU part\t: %07x\n", processor_id >> 4);
+               seq_printf(m, "CPU part\t: %07x\n", read_cpuid_id() >> 4);
        } else {
-               if ((processor_id & 0x0008f000) == 0x00007000) {
+               if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
                        /* ARM7 */
                        seq_printf(m, "CPU variant\t: 0x%02x\n",
-                                  (processor_id >> 16) & 127);
+                                  (read_cpuid_id() >> 16) & 127);
                } else {
                        /* post-ARM7 */
                        seq_printf(m, "CPU variant\t: 0x%x\n",
-                                  (processor_id >> 20) & 15);
+                                  (read_cpuid_id() >> 20) & 15);
                }
                seq_printf(m, "CPU part\t: 0x%03x\n",
-                          (processor_id >> 4) & 0xfff);
+                          (read_cpuid_id() >> 4) & 0xfff);
        }
-       seq_printf(m, "CPU revision\t: %d\n", processor_id & 15);
+       seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
 
        {
-               unsigned int cache_info = read_cpuid(CPUID_CACHETYPE);
-               if (cache_info != processor_id) {
+               unsigned int cache_info = read_cpuid_cachetype();
+               if (cache_info != read_cpuid_id()) {
                        seq_printf(m, "Cache type\t: %s\n"
                                      "Cache clean\t: %s\n"
                                      "Cache lockdown\t: %s\n"

diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index 082818aaa2056fe8cd0ee452d0f75f03ca4d2965..1845643ed635c7acfafb076e8289639fd0ec39b4 100644 (file)
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -27,6 +27,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
 #include <mach/hardware.h>
+#include <asm/cputype.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -49,8 +50,7 @@ static int force_ep80219;
 
 static int is_80219(void)
 {
-       extern int processor_id;
-       return !!((processor_id & 0xffffffe0) == 0x69052e20);
+       return !!((read_cpuid_id() & 0xffffffe0) == 0x69052e20);
 }
 
 static int is_ep80219(void)

diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 192538a045753e437df60c3054dd8212ab3257ed..f74a460d4a323c9a11fc4eed3b70baceb11b9e48 100644 (file)
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -27,6 +27,7 @@
 #include <linux/device.h>
 #include <asm/dma-mapping.h>
 
+#include <asm/cputype.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
@@ -366,15 +367,13 @@ void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size,
 
 void __init ixp4xx_pci_preinit(void)
 {  
-       unsigned long processor_id;
-
-       asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :);
+       unsigned long cpuid = read_cpuid_id();
 
        /*
         * Determine which PCI read method to use.
         * Rev 0 IXP425 requires workaround.
         */
-       if (!(processor_id & 0xf) && cpu_is_ixp42x()) {
+       if (!(cpuid & 0xf) && cpu_is_ixp42x()) {
                printk("PCI: IXP42x A0 silicon detected - "
                        "PCI Non-Prefetch Workaround Enabled\n");
                ixp4xx_pci_read = ixp4xx_pci_read_errata;

diff --git a/arch/arm/mach-ixp4xx/include/mach/cpu.h b/arch/arm/mach-ixp4xx/include/mach/cpu.h
index ff8aa2393bf94abd41bef12956686bedeecaa4de..51bd69c46d9433971932ce4244eb4e42d1fa7ce3 100644 (file)
--- a/arch/arm/mach-ixp4xx/include/mach/cpu.h
+++ b/arch/arm/mach-ixp4xx/include/mach/cpu.h
@@ -14,18 +14,19 @@
 #ifndef __ASM_ARCH_CPU_H__
 #define __ASM_ARCH_CPU_H__
 
-extern unsigned int processor_id;
+#include <asm/cputype.h>
+
 /* Processor id value in CP15 Register 0 */
 #define IXP425_PROCESSOR_ID_VALUE      0x690541c0
 #define IXP435_PROCESSOR_ID_VALUE      0x69054040
 #define IXP465_PROCESSOR_ID_VALUE      0x69054200
 #define IXP4XX_PROCESSOR_ID_MASK       0xfffffff0
 
-#define cpu_is_ixp42x()        ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
+#define cpu_is_ixp42x()        ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \
                          IXP425_PROCESSOR_ID_VALUE)
-#define cpu_is_ixp43x()        ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
+#define cpu_is_ixp43x()        ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \
                          IXP435_PROCESSOR_ID_VALUE)
-#define cpu_is_ixp46x()        ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
+#define cpu_is_ixp46x()        ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \
                          IXP465_PROCESSOR_ID_VALUE)
 
 static inline u32 ixp4xx_read_feature_bits(void)

diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index a5d4526ac4d6debdb1f0a0e0393bc37443e00bac..2fd8a2d71e560f05af3d029a700c1071e910ecc9 100644 (file)
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -15,6 +15,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 
+#include <asm/cputype.h>
 #include <asm/io.h>
 
 #include <mach/control.h>

diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index e89df4d0d23999278dfdab688ed76aa3ecfc07d9..a1a0a2ffd642299bcbf1cb498aa721a72b16ebe9 100644 (file)
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -62,6 +62,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <asm/cputype.h>
+
 #ifdef CONFIG_PXA25x
 #define __cpu_is_pxa21x(id)                            \
        ({                                              \

diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c
index da3a898a6d66e70c115a7e904efe7cede6ae8a39..f7fa03478efd9e7c203c72363696e8651209499d 100644 (file)
--- a/arch/arm/mach-sa1100/cpu-sa1100.c
+++ b/arch/arm/mach-sa1100/cpu-sa1100.c
@@ -88,6 +88,8 @@
 #include <linux/init.h>
 #include <linux/cpufreq.h>
 
+#include <asm/cputype.h>
+
 #include <mach/hardware.h>
 
 #include "generic.h"
@@ -240,7 +242,7 @@ static struct cpufreq_driver sa1100_driver = {
 
 static int __init sa1100_dram_init(void)
 {
-       if ((processor_id & CPU_SA1100_MASK) == CPU_SA1100_ID)
+       if (cpu_is_sa1100())
                return cpufreq_register_driver(&sa1100_driver);
        else
                return -ENODEV;

diff --git a/arch/arm/mach-sa1100/cpu-sa1110.c b/arch/arm/mach-sa1100/cpu-sa1110.c
index 029dbfbbafcf6e6d2ead0e6aa9ddb4b26a9ed22e..78d8294756ac2a023454d3cb61b2bf7206890cef 100644 (file)
--- a/arch/arm/mach-sa1100/cpu-sa1110.c
+++ b/arch/arm/mach-sa1100/cpu-sa1110.c
@@ -25,6 +25,7 @@
 #include <linux/init.h>
 
 #include <mach/hardware.h>
+#include <asm/cputype.h>
 #include <asm/mach-types.h>
 #include <asm/io.h>
 #include <asm/system.h>

diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h
index 62aaf04a390674b477c6d063165641ef428d3c53..4f7ea012e1e57e3f676db5f832579d9ed98e3f81 100644 (file)
--- a/arch/arm/mach-sa1100/include/mach/SA-1100.h
+++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h
@@ -2054,19 +2054,3 @@
                                        /* active display mode)            */
 #define LCCR3_OutEnH   (LCCR3_OEP*0)   /*  Output Enable active High      */
 #define LCCR3_OutEnL   (LCCR3_OEP*1)   /*  Output Enable active Low       */
-
-#ifndef __ASSEMBLY__
-extern unsigned int processor_id;
-#endif
-
-#define CPU_REVISION   (processor_id & 15)
-#define CPU_SA1110_A0  (0)
-#define CPU_SA1110_B0  (4)
-#define CPU_SA1110_B1  (5)
-#define CPU_SA1110_B2  (6)
-#define CPU_SA1110_B4  (8)
-
-#define CPU_SA1100_ID  (0x4401a110)
-#define CPU_SA1100_MASK        (0xfffffff0)
-#define CPU_SA1110_ID  (0x6901b110)
-#define CPU_SA1110_MASK        (0xfffffff0)

diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h
index 5976435f42c294c008d25d10518577371476b55d..b70846c096aa0f1755290fa1b5cdb2b4f837e5e4 100644 (file)
--- a/arch/arm/mach-sa1100/include/mach/hardware.h
+++ b/arch/arm/mach-sa1100/include/mach/hardware.h
@@ -36,8 +36,26 @@
 #define io_v2p( x )             \
    ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
 
+#define CPU_SA1110_A0  (0)
+#define CPU_SA1110_B0  (4)
+#define CPU_SA1110_B1  (5)
+#define CPU_SA1110_B2  (6)
+#define CPU_SA1110_B4  (8)
+
+#define CPU_SA1100_ID  (0x4401a110)
+#define CPU_SA1100_MASK        (0xfffffff0)
+#define CPU_SA1110_ID  (0x6901b110)
+#define CPU_SA1110_MASK        (0xfffffff0)
+
 #ifndef __ASSEMBLY__
 
+#include <asm/cputype.h>
+
+#define CPU_REVISION   (read_cpuid_id() & 15)
+
+#define cpu_is_sa1100()        ((read_cpuid_id() & CPU_SA1100_MASK) == CPU_SA1100_ID)
+#define cpu_is_sa1110()        ((read_cpuid_id() & CPU_SA1110_MASK) == CPU_SA1110_ID)
+
 # define __REG(x)      (*((volatile unsigned long *)io_p2v(x)))
 # define __PREG(x)     (io_v2p((unsigned long)&(x)))
 

diff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c
index 158bd96763d31bb5fe07792c0288e7c3fb6378bf..10b1bae1a258f782f0aaf67e128f8a8aef514672 100644 (file)
--- a/arch/arm/mm/cache-xsc3l2.c
+++ b/arch/arm/mm/cache-xsc3l2.c
@@ -18,10 +18,11 @@
  */
 #include <linux/init.h>
 #include <linux/spinlock.h>
+#include <linux/io.h>
 
 #include <asm/system.h>
+#include <asm/cputype.h>
 #include <asm/cacheflush.h>
-#include <asm/io.h>
 
 #define CR_L2  (1 << 26)
 

diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index b81dbf9ffb77b3f28a9b0ad872341fdad3656ca6..20e4454e452eee0d481fb1f1588fc7d481f4cdac 100644 (file)
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -25,6 +25,7 @@
 #include <linux/mm.h>
 #include <linux/vmalloc.h>
 
+#include <asm/cputype.h>
 #include <asm/cacheflush.h>
 #include <asm/io.h>
 #include <asm/mmu_context.h>

diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index 3f6dc40b835321fd469a23ce8ffa49089377e74b..28ead8393b5ac30594a023fe102ec19fabfceeb9 100644 (file)
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -6,6 +6,7 @@
 #include <linux/mman.h>
 #include <linux/shm.h>
 #include <linux/sched.h>
+#include <asm/cputype.h>
 #include <asm/system.h>
 
 #define COLOUR_ALIGN(addr,pgoff)               \
@@ -37,8 +38,8 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
         * caches alias.  This is indicated by bits 9 and 21 of the
         * cache type register.
         */
-       cache_type = read_cpuid(CPUID_CACHETYPE);
-       if (cache_type != read_cpuid(CPUID_ID)) {
+       cache_type = read_cpuid_cachetype();
+       if (cache_type != read_cpuid_id()) {
                aliasing = (cache_type | cache_type >> 12) & (1 << 11);
                if (aliasing)
                        do_align = filp || flags & MAP_SHARED;

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 25d9a11eb61750ade3ba77abd7771068ebe668ee..c2bbe3f311f0b91cfe881b639f274fde9d50a471 100644 (file)
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -15,6 +15,7 @@
 #include <linux/mman.h>
 #include <linux/nodemask.h>
 
+#include <asm/cputype.h>
 #include <asm/mach-types.h>
 #include <asm/setup.h>
 #include <asm/sizes.h>

diff --git a/arch/arm/oprofile/op_model_xscale.c b/arch/arm/oprofile/op_model_xscale.c
index 7c3289c2acd7d4b2add8364c502b368ac9e88d9e..724ab9ce252674ff02d0e319cc25cd2a7b22da01 100644 (file)
--- a/arch/arm/oprofile/op_model_xscale.c
+++ b/arch/arm/oprofile/op_model_xscale.c
@@ -22,7 +22,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 
-#include <asm/system.h>
+#include <asm/cputype.h>
 
 #include "op_counter.h"
 #include "op_arm_model.h"

diff --git a/drivers/watchdog/ixp4xx_wdt.c b/drivers/watchdog/ixp4xx_wdt.c
index 8302ef005be7fac9d04814f3f572deb261031277..147b4d5c63b3bc85a1a5dbc08404bc62c96e8f6b 100644 (file)
--- a/drivers/watchdog/ixp4xx_wdt.c
+++ b/drivers/watchdog/ixp4xx_wdt.c
@@ -174,10 +174,8 @@ static struct miscdevice ixp4xx_wdt_miscdev = {
 static int __init ixp4xx_wdt_init(void)
 {
        int ret;
-       unsigned long processor_id;
 
-       asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :);
-       if (!(processor_id & 0xf) && !cpu_is_ixp46x()) {
+       if (!(read_cpuid_id() & 0xf) && !cpu_is_ixp46x()) {
                printk(KERN_ERR "IXP4XXX Watchdog: Rev. A0 IXP42x CPU detected"
                        " - watchdog disabled\n");