return 1;
}
-static bool sh_pfc_gpio_is_pin(struct sh_pfc *pfc, unsigned int gpio)
-{
- return (gpio < pfc->info->nr_pins) &&
- (pfc->info->pins[gpio].enum_id != 0);
-}
-
static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
unsigned long reg_width)
{
sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
}
-static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
+static void sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
{
struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio];
struct pinmux_data_reg *data_reg;
int k, n;
- if (!sh_pfc_gpio_is_pin(pfc, gpio))
- return -1;
-
k = 0;
while (1) {
data_reg = pfc->info->data_regs + k;
gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
gpiop->flags &= ~PINMUX_FLAG_DBIT;
gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
- return 0;
+ return;
}
}
k++;
}
BUG();
-
- return -1;
}
static void sh_pfc_setup_data_regs(struct sh_pfc *pfc)
struct pinmux_data_reg *drp;
int k;
- for (k = 0; k < pfc->info->nr_pins; k++)
+ for (k = 0; k < pfc->info->nr_pins; k++) {
+ if (pfc->info->pins[k].enum_id == 0)
+ continue;
+
sh_pfc_setup_data_reg(pfc, k);
+ }
k = 0;
while (1) {
}
}
-int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
- struct pinmux_data_reg **drp, int *bitp)
+void sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
+ struct pinmux_data_reg **drp, int *bitp)
{
struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio];
int k, n;
- if (!sh_pfc_gpio_is_pin(pfc, gpio))
- return -1;
-
k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
*drp = pfc->info->data_regs + k;
*bitp = n;
- return 0;
}
static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos);
void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
unsigned long value);
-int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
- struct pinmux_data_reg **drp, int *bitp);
+void sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
+ struct pinmux_data_reg **drp, int *bitp);
int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type,
int cfg_mode);
static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
{
+ struct sh_pfc *pfc = gpio_to_pfc(gc);
+
+ if (pfc->info->pins[offset].enum_id == 0)
+ return -EINVAL;
+
return pinctrl_request_gpio(offset);
}
static void gpio_pin_set_value(struct sh_pfc *pfc, unsigned offset, int value)
{
- struct pinmux_data_reg *dr = NULL;
- int bit = 0;
-
- if (sh_pfc_get_data_reg(pfc, offset, &dr, &bit) != 0)
- BUG();
+ struct pinmux_data_reg *dr;
+ int bit;
+ sh_pfc_get_data_reg(pfc, offset, &dr, &bit);
sh_pfc_write_bit(dr, bit, value);
}
static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
{
struct sh_pfc *pfc = gpio_to_pfc(gc);
- struct pinmux_data_reg *dr = NULL;
- int bit = 0;
-
- if (sh_pfc_get_data_reg(pfc, offset, &dr, &bit) != 0)
- return -EINVAL;
+ struct pinmux_data_reg *dr;
+ int bit;
+ sh_pfc_get_data_reg(pfc, offset, &dr, &bit);
return sh_pfc_read_bit(dr, bit);
}