clk: qcom: fix RCG M/N counter configuration

Currently, a RCG's M/N counter (used for fraction division) is
set to either 'bypass' (counter disabled) or 'dual edge' (counter
enabled) based on whether the corresponding rcg struct has a mnd
field specified and a non-zero N.

In the case where M and N are the same value, the M/N counter is
still enabled by code even though no division takes place.
Leaving the RCG in such a state can result in improper behavior.
This was observed with the DSI pixel clock RCG when M and N were
both set to 1.

Add an additional check (M != N) to enable the M/N counter only
when it's needed for fraction division.

Signed-off-by: Archit Taneja <architt@codeaurora.org>
Fixes: bcd61c0f535a (clk: qcom: Add support for root clock
generators (RCGs))
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 742acfa18d63798c19c25884ef2b50d508965858..381f27469a9c2b2cfc6c4042533677924886bad8 100644 (file)
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -243,7 +243,7 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
        mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
        cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
        cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT;
-       if (rcg->mnd_width && f->n)
+       if (rcg->mnd_width && f->n && (f->m != f->n))
                cfg |= CFG_MODE_DUAL_EDGE;
        ret = regmap_update_bits(rcg->clkr.regmap,
                        rcg->cmd_rcgr + CFG_REG, mask, cfg);