ARM: dts: rockchip: add cpu enable method for rk3228 SoC

This patch sets PSCI as the default cpu enable-method for RK3228 SoC.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 003efe3ac2410a741a95af234fca27d9c62dee03..d565b9581b00ec2469e8300df104accd938e3870 100644 (file)
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -70,6 +70,7 @@
                        #cooling-cells = <2>; /* min followed by max */
                        clock-latency = <40000>;
                        clocks = <&cru ARMCLK>;
+                       enable-method = "psci";
                };
 
                cpu1: cpu@f01 {
@@ -78,6 +79,7 @@
                        reg = <0xf01>;
                        resets = <&cru SRST_CORE1>;
                        operating-points-v2 = <&cpu0_opp_table>;
+                       enable-method = "psci";
                };
 
                cpu2: cpu@f02 {
@@ -86,6 +88,7 @@
                        reg = <0xf02>;
                        resets = <&cru SRST_CORE2>;
                        operating-points-v2 = <&cpu0_opp_table>;
+                       enable-method = "psci";
                };
 
                cpu3: cpu@f03 {
@@ -94,6 +97,7 @@
                        reg = <0xf03>;
                        resets = <&cru SRST_CORE3>;
                        operating-points-v2 = <&cpu0_opp_table>;
+                       enable-method = "psci";
                };
        };
 
@@ -151,6 +155,11 @@
                interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
        };
 
+       psci {
+               compatible = "arm,psci-1.0", "arm,psci-0.2";
+               method = "smc";
+       };
+
        timer {
                compatible = "arm,armv7-timer";
                arm,cpu-registers-not-fw-configured;