powerpc/mpc85xx: Add new ext fields to Integrated FLash Controller

Freescale's Integrated Flash controller(IFC) v1.1.0 supports 40 bit
address bus width.
In case more than 32 bit address is used, the EXT registers should be set.

Add support of ext registers.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h
index b955012939a2708c7b650347823345f030d2921d..b8a4b9bc50b326b07efda9e6f82e59e16be3e318 100644 (file)
--- a/arch/powerpc/include/asm/fsl_ifc.h
+++ b/arch/powerpc/include/asm/fsl_ifc.h
@@ -768,22 +768,24 @@ struct fsl_ifc_gpcm {
  */
 struct fsl_ifc_regs {
        __be32 ifc_rev;
-       u32 res1[0x3];
+       u32 res1[0x2];
        struct {
+               __be32 cspr_ext;
                __be32 cspr;
-               u32 res2[0x2];
+               u32 res2;
        } cspr_cs[FSL_IFC_BANK_COUNT];
-       u32 res3[0x18];
+       u32 res3[0x19];
        struct {
                __be32 amask;
                u32 res4[0x2];
        } amask_cs[FSL_IFC_BANK_COUNT];
-       u32 res5[0x18];
+       u32 res5[0x17];
        struct {
+               __be32 csor_ext;
                __be32 csor;
-               u32 res6[0x2];
+               u32 res6;
        } csor_cs[FSL_IFC_BANK_COUNT];
-       u32 res7[0x18];
+       u32 res7[0x19];
        struct {
                __be32 ftim[4];
                u32 res8[0x8];